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KR100950201B1 - Method of forming via hole in semiconductor device - Google Patents

Method of forming via hole in semiconductor device Download PDF

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KR100950201B1
KR100950201B1 KR1020030012404A KR20030012404A KR100950201B1 KR 100950201 B1 KR100950201 B1 KR 100950201B1 KR 1020030012404 A KR1020030012404 A KR 1020030012404A KR 20030012404 A KR20030012404 A KR 20030012404A KR 100950201 B1 KR100950201 B1 KR 100950201B1
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via hole
metal line
interlayer insulating
forming
film
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KR20040077027A (en
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서을규
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은, 반도체소자의 비어홀 형성방법에 관한 것으로서, 특히, 반도체기판 상에 상,하부메탈라인을 적층하여 형성한 후, 상부메탈라인을 식각하고 질화막을 적층하고, 그 상부면에 층간절연막을 적층한 후, 상기 질화막을 개방하는 제1비어홀을 형성한 후, 제1비어홀로 노출된 질화막을 재차 식각하여 상부메탈라인을 개방하는 제2비어홀을 식각하여 형성하므로 하부메탈라인의 어택을 방지하도록 하는 매우 유용하고 효과적인 발명에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a via hole of a semiconductor device, and in particular, by forming upper and lower metal lines on a semiconductor substrate, and then etching upper metal lines and laminating nitride films, and forming an interlayer insulating film on the upper surface. After stacking, after forming the first via hole for opening the nitride film, the nitride film exposed to the first via hole is etched again to form the second via hole for opening the upper metal line to prevent attack of the lower metal line. To a very useful and effective invention.

비어홀 메탈라인 질화막 식각방지막 오버에치Via-hole Metalline Nitride Etching Overetch

Description

반도체소자의 비어홀 형성방법 { Method For Forming The Via Hole Of Semiconductor Device } Method for forming the via hole of semiconductor device             

도 1 내지 도 3은 종래의 비어홀 형성방법을 순차적으로 보인 도면이고,1 to 3 are views sequentially showing a conventional via hole forming method,

도 4 내지 도 9는 본 발명에 따른 반도체소자의 비어홀 형성방법을 순차적으로 보인 도면이다.
4 to 9 are views sequentially showing a method of forming a via hole of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명* * Description of the symbols for the main parts of the drawings *

10 : 반도체기판 12 : 하부메탈라인10: semiconductor substrate 12: lower metal line

14 : 산화막 16 : 상부메탈라인14 oxide film 16: upper metal line

18 : 반사방지막 20 : 질화막18: antireflection film 20: nitride film

22 : 층간절연막 24 : 감광막22 interlayer insulating film 24 photosensitive film

26 : 개방부위 28 : 제1비어홀26: open part 28: the first beer hole

30 : 제2비어홀
30: second beer hole

본 발명은 비어홀을 형성하는 방법에 관한 것으로, 특히, 반도체기판 상에 상,하부메탈라인을 적층하여 형성한 후, 상부메탈라인을 식각하고 질화막을 적층하고, 그 상부면에 층간절연막을 적층한 후, 상기 질화막을 개방하는 제1비어홀을 형성한 후, 제1비어홀로 노출된 질화막을 재차 식각하여 상부메탈라인을 개방하는 제2비어홀을 식각하여 형성하므로 하부메탈라인의 어택을 방지하도록 하는 반도체소자의 비어홀 형성방법에 관한 것이다.The present invention relates to a method for forming a via hole, and in particular, after forming upper and lower metal lines on a semiconductor substrate, the upper metal lines are etched and nitride films are stacked, and an interlayer insulating film is laminated on the upper surface. Thereafter, after forming the first via hole for opening the nitride film, the nitride film exposed to the first via hole is etched again to form the second via hole for opening the upper metal line, thereby preventing the attack of the lower metal line. A method of forming a via hole of an element is provided.

일반적으로, 반도체장치의 종류에는 여러 가지가 있고, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과트랜지스터(MOSFET; metal oxide semiconductor field effect transistor)와, 실리콘기판에 비하여 전자의 이동속도가 6배나 큰 갈륨아세나이드(GaAs)를 기판으로 사용하여 전계효과를 내는 메스형 전계효과트랜지스터(MESFET; metal semiconductor field effect transistor)와, 그 이외에 절연 게이트형 전계효과 트랜지스터(IGEFT; insulator gate field effect transistor) 등의 다양한 방식의 반도체장치가 사용되고 있다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, and the like formed in the semiconductor device. In recent years, MOS is formed by applying an oxide film on a semiconductor substrate to produce an electric field effect. MESH-type field effect transistors (MESFETs) and gallium arsenide (GaAs), which have six times the electrons' movement speed compared to silicon substrates, as a substrate. semiconductor devices of various types such as metal semiconductor field effect transistors and insulator gate field effect transistors (IGEFTs).

이와 같이, 반도체장치에는 배선라인과 배선라인을 서로 연결하기 위하여 텅스텐층을 증착한 후에 식각하여서 상부배선라인과 하부배선라인을 서로 연결시키는 텅스텐 플러그(Plug)를 형성시켜서 사용하게 되는 것으로, 이 플러그를 형성하기 위하여서는 식각공정을 통하여 절연막 상에 일정깊이 함몰된 비어홀(Via Hole)("콘 택홀"이라 칭하기도 함)을 형성하도록 한다.In this way, in the semiconductor device, a tungsten layer is deposited and then etched to form a tungsten plug which connects the upper wiring line and the lower wiring line to each other in order to connect the wiring line and the wiring line. In order to form a semiconductor device, a via hole (sometimes referred to as a "contact hole") is formed on the insulating layer through an etching process.

도 1 내지 도 3은 종래의 비어홀 형성방법을 순차적으로 보인 도면이다.1 to 3 are views sequentially showing a conventional method of forming a via hole.

종래의 비어홀 형성방법을 살펴 보면, 도 1에 도시된 바와 같이, 다양한 적층물이 형성된 반도체기판(1) 상에 하부메탈라인(2)을 형성하도록 한 후, 그 결과물 상에 제1층간절연막(3)과 상부메탈라인(4)을 연속하여 적층하도록 한다.Referring to the conventional method of forming a via hole, as shown in FIG. 1, after forming the lower metal line 2 on the semiconductor substrate 1 on which various laminates are formed, the first interlayer insulating film ( 3) and the upper metal line (4) to be stacked in succession.

그리고, 상기 상부메탈라인(4)을 식각한 후, 재차 제2층간절연막(5)을 적층하도록 한다.After the upper metal line 4 is etched, the second interlayer insulating film 5 is stacked again.

그리고, 도 2에 도시된 바와 같이, 상기 결과물 상에 감광막(6)을 적층한 후, 상부메탈라인(4)으로 연결되는 개방부위(7)를 형성하도록 한다.As shown in FIG. 2, after the photoresist film 6 is laminated on the resultant product, an open portion 7 connected to the upper metal line 4 is formed.

그리고, 도 3에 도시된 바와 같이, 상기 감광막(6)의 개방부위(7)를 통하여 식각하여 비어홀(8)을 형성하도록 한다.As shown in FIG. 3, the via hole 8 may be etched through the open portion 7 of the photosensitive film 6.

그런데, 상기한 바와 같이, 상기 비어홀(8)을 식각할 때, 상부메탈라인(4)의 측면부분으로 연결되는 보더리스 비아(Borderless Via)홀을 적용하는 경우, 미스얼라인(Mis align)이 발생되고, 비아홀의 식각이 적절하지 않은 경우, 비아 형상에 이상이 발생하며, 이로 인하여 도 3에서와 같이, 하측으로 절개되어 연결되는 단선부위(9)가 형성되어지며, 심한 경우에는 하부메탈라인(2)으로 연결되어 어택(Attack)이 발생되므로 반도체소자의 불량을 유발하는 문제점을 지닌다.
As described above, when etching the via hole 8, when a borderless via hole connected to the side portion of the upper metal line 4 is applied, a misalignment occurs. When the via hole is not properly etched, an abnormality occurs in the via shape. As a result, as shown in FIG. 3, a disconnection part 9 is formed to be cut and connected to the lower side. Since it is connected to (2) and an attack occurs, there is a problem that causes a defect of the semiconductor device.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판 상에 상,하부 메탈라인을 적층하여 형성한 후, 상부메탈라인을 식각하고 질화막을 적층하고, 그 상부면에 층간절연막을 적층한 후, 상기 질화막을 개방하는 제1비어홀을 형성한 후, 제1비어홀로 노출된 질화막을 재차 식각하여 상부메탈라인을 개방하는 제2비어홀을 식각하여 형성하므로 하부메탈라인의 어택을 방지하는 것이 목적이다.
The present invention has been made in view of this point, and after the upper and lower metal lines are laminated on the semiconductor substrate, the upper metal line is etched and the nitride film is laminated, and the interlayer insulating film is laminated on the upper surface. Since the first via hole for opening the nitride film is formed, the nitride film exposed to the first via hole is etched again to form the second via hole for opening the upper metal line, thereby preventing attack of the lower metal line.

이러한 목적은, 반도체기판 상에 식각공정으로 비어홀을 형성하는 방법에 있어서, 상기 반도체기판 상에 하부메탈라인, 제1층간절연막, 상부메탈라인 및 반사방지막을 순차적으로 적층한 후, 상기 상부메탈라인을 식각하는 단계와; 상기 단계 후에 상기 결과물 상에 질화막을 적층한 후, 그 상부면에 연속하여 층간절연막을 적층하고 평탄화하는 단계와; 상기 단계 후에 상기 층간절연막 상에 감광막을 적층한 후, 노광공정으로 개방부위를 형성하는 단계와; 상기 단계 후에 상기 개방부위를 통하여 상기 제2층간절연막을 식각하여 제1비어홀을 형성하는 단계와; 상기 단계 후에 상기 제1비어홀을 통하여 상기 질화막을 식각하여 상부메탈라인의 측면부분을 개방하도록 하는 단계로 이루어진 반도체소자의 비어홀 형성방법을 제공함으로써 달성된다.This object is a method of forming a via hole by an etching process on a semiconductor substrate, wherein a lower metal line, a first interlayer insulating film, an upper metal line, and an antireflection film are sequentially stacked on the semiconductor substrate, and then the upper metal line Etching the; Laminating a nitride film on the resultant after the step, and subsequently laminating and planarizing an interlayer insulating film on an upper surface thereof; Stacking a photoresist film on the interlayer insulating film after the step, and forming an open portion by an exposure process; Forming a first via hole by etching the second interlayer insulating layer through the open portion after the step; After the step is achieved by providing a method for forming a via hole of a semiconductor device comprising the step of etching the nitride film through the first via hole to open the side portion of the upper metal line.

그리고, 상기 질화막의 두께는, 200 ∼ 400Å의 범위에서 형성되는 것이 바람직 하다.And it is preferable that the thickness of the said nitride film is formed in the range of 200-400 GPa.

그리고, 상기 제1비어홀 형성시, 질화막을 식각방지막으로 하여 오버 에치(Over Etch)를 하도록 한다. When the first via hole is formed, an over etch is performed using the nitride film as an etch stop layer.                     

이하, 첨부한 도면에 의거하여 본 발명에 따른 비어홀 라운딩 형성방법에 대하여 상세히 살펴보도록 한다.Hereinafter, the via hole rounding method according to the present invention will be described in detail with reference to the accompanying drawings.

도 4 내지 도 9는 본 발명에 따른 반도체소자의 비어홀 형성방법을 순차적으로 보인 도면이다.4 to 9 are views sequentially showing a method of forming a via hole of a semiconductor device according to the present invention.

도 4에 도시된 바와 같이, 반도체기판(10) 상에 하부메탈라인(12), 제1층간절연막(14), 상부메탈라인(16) 및 반사방지막(18)을 순차적으로 적층한 후, 상기 상부메탈라인(16)을 식각하도록 한다.As shown in FIG. 4, after the lower metal line 12, the first interlayer insulating layer 14, the upper metal line 16, and the anti-reflection film 18 are sequentially stacked on the semiconductor substrate 10, the lower metal line 12 is sequentially stacked. The upper metal line 16 is etched.

도 5에 도시된 바와 같이, 상기 단계 후에 상기 결과물 상에 질화막(20)을 적층하도록 한다.As shown in FIG. 5, after the step, the nitride film 20 is laminated on the resultant product.

상기 질화막(20)의 두께는, 200 ∼ 400Å의 범위에서 형성되는 것이 바람직하고, 특히, 300Å의 두께로 형성하는 것이 가장 바람직 하다.It is preferable that the thickness of the said nitride film 20 is formed in the range of 200-400 kPa, Most preferably, it is formed in the thickness of 300 kPa.

도 6에 도시된 바와 같이, 상기 단계 후에 상기 질화막(20)의 상부면에 연속하여 층간절연막(22)을 적층한 후, 평탄화하도록 한다.As shown in FIG. 6, after the step, the interlayer insulating film 22 is successively stacked on the upper surface of the nitride film 20, and then planarized.

그리고, 도 7에 도시된 바와 같이, 상기 단계 후에 상기 층간절연막(22) 상에 감광막(24)을 적층한 후, 노광공정으로 개방부위(26)를 형성하도록 한다.As shown in FIG. 7, after the step, the photoresist layer 24 is laminated on the interlayer insulating layer 22, and then the open portion 26 is formed by an exposure process.

그리고, 도 8에 도시된 바와 같이, 상기 단계 후에 상기 개방부위(26)를 통하여 상기 제2층간절연막(22)을 식각하여 제1비어홀(28)을 형성하도록 한다.As illustrated in FIG. 8, after the step, the second interlayer insulating layer 22 is etched through the open portion 26 to form the first via hole 28.

이 때, 상기 제1비어홀(28) 형성시, 질화막(20)을 식각방지막으로 하여 오버 에치(Over Etch)를 하는 것이 바람직 하다.In this case, when the first via hole 28 is formed, it is preferable to overetch the nitride film 20 as an etch stop layer.

그리고, 도 9에 도시된 바와 같이, 상기 단계 후에 상기 제1비어홀(28)을 통 하여 상기 질화막(20)을 식각하여 상부메탈라인(16)의 측면부분을 개방하도록 한다.
As shown in FIG. 9, after the step, the nitride film 20 is etched through the first via hole 28 to open the side portion of the upper metal line 16.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 비어홀 형성방법을 사용하게 되면, 반도체기판 상에 상,하부메탈라인을 적층하여 형성한 후, 상부메탈라인을 식각하고 질화막을 적층하고, 그 상부면에 층간절연막을 적층한 후, 상기 질화막을 개방하는 제1비어홀을 형성한 후, 제1비어홀로 노출된 질화막을 재차 식각하여 상부메탈라인을 개방하는 제2비어홀을 식각하여 형성하므로 하부메탈라인의 어택을 방지하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the via hole forming method of the semiconductor device according to the present invention is used, upper and lower metal lines are formed on the semiconductor substrate by lamination, and the upper metal lines are etched to form a nitride film. After the interlayer insulating layer is stacked on the upper surface, the first via hole for opening the nitride film is formed, and the nitride film exposed to the first via hole is etched again to form the second via hole for opening the upper metal line. It is a very useful and effective invention to prevent attack of the line.

Claims (3)

반도체기판 상에 식각공정으로 비어홀을 형성하는 방법에 있어서,In the method of forming a via hole by an etching process on a semiconductor substrate, 상기 반도체기판 상에 하부메탈라인, 제1층간절연막, 상부메탈라인 및 반사방지막을 순차적으로 적층한 후, 상기 상부메탈라인을 식각하는 단계와;Sequentially depositing a lower metal line, a first interlayer insulating film, an upper metal line, and an anti-reflection film on the semiconductor substrate, and then etching the upper metal line; 상기 상부메탈라인의 식각 후에 노출되는 상기 제1층간절연막의 표면, 상기 반사 방지막 및 상기 상부메탈라인 측면을 덮는 질화막을 적층하는 단계와;Stacking a nitride film covering a surface of the first interlayer insulating film, the anti-reflection film, and side surfaces of the upper metal line exposed after etching the upper metal line; 상기 질화막 상에 제2층간절연막을 적층하고 평탄화하는 단계와;Stacking and planarizing a second interlayer insulating film on the nitride film; 상기 제2층간절연막 상에 감광막을 적층한 후, 노광공정으로 개방부위를 형성하는 단계와;Stacking a photosensitive film on the second interlayer insulating film and forming an open portion by an exposure process; 상기 질화막을 식각방지막으로 하여 상기 감광막의 개방부위를 통하여 상기 제2층간절연막을 식각하여 비어홀을 형성하는 단계와;Etching the second interlayer insulating layer through the open portion of the photosensitive layer using the nitride layer as an etch stop layer to form a via hole; 상기 질화막의 상기 비어홀에 노출되는 부분을 식각하여 상기 상부메탈라인의 측면 부분 및 상기 제1층간절연막의 표면 부분이 상기 비어홀에 개방되도록 하는 단계로 이루어진 것을 특징으로 하는 반도체소자의 비어홀 형성방법.And etching the portion of the nitride film exposed to the via hole to open the side portion of the upper metal line and the surface portion of the first interlayer insulating layer to the via hole. 제 1 항에 있어서, The method of claim 1, 상기 질화막의 두께는, 200 ∼ 400Å의 범위에서 형성되는 것을 특징으로 하는 반도체소자의 비어홀 형성방법.The thickness of said nitride film is formed in the range of 200-400 GPa. The via-hole formation method of a semiconductor element characterized by the above-mentioned. 삭제delete
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