KR100965080B1 - Nand Flash Memory Devices - Google Patents

Abstract

The present invention relates to a NAND flash memory device, wherein a program voltage can be applied differently for each word line by adjusting a threshold voltage of a transistor applying a global word line signal to a local word line, and the program of a cell connected to both word lines. By setting the threshold voltage equal to the program threshold voltage of the cell connected to the inner word line, the disturbance of the program threshold voltage of the programmed cell can be improved, and the program pulse can be reduced by improving the disturbance of the program threshold voltage. The present invention provides a NAND flash memory device capable of improving program characteristics by reducing program time by reducing program pulses.

Nand Flash, Program, Threshold, Disruptive, Pass Transistor

Description

NAND flash memory device             

1 is a conceptual diagram illustrating a program of a NAND flash memory device according to the present invention.

2 is a graph illustrating threshold voltages of programmed memory cells according to pass voltages.

3 is a distribution graph of threshold voltages of programmed memory cells shown for each word line in a single string.

4 is a circuit diagram of a NAND flash memory device according to the present invention.

5A and 5B are conceptual views illustrating a voltage application method of a pass transistor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: cell string 20: operating voltage generator

The present invention relates to a NAND flash memory device, and more particularly, to a NAND flash memory device capable of improving threshold voltage disturbance of a programmed cell by varying an X decoder internal transistor for each word line.

Unlike NOR flash, NAND flash memory cells have a cell string in which a plurality of cells are connected in a string form, and a structure including select transistors in drains and sources of the cell strings. After programming such a NAND cell, the program cell is identified through program confirmation. The disadvantage of NAND cells, however, is that program speed is governed by the slowest cell in a page. To solve this problem, if a higher voltage is applied to the word line of the cell to be programmed to increase the program speed, the overprogrammed cell is generated. When the erase cell in the string is read, the high threshold voltage of the overprogrammed cell is caused. An error will occur.

Accordingly, the present invention provides a NAND flash memory device capable of improving the threshold voltage disturbance of a programmed cell and reducing the program time by varying the threshold voltages of internal transistors of the X decoder of the NAND flash memory device. to provide.

According to the present invention, a plurality of memory cells each connected to a plurality of local word lines is applied to a plurality of local word lines according to a plurality of cell strings and operating voltages connected in a string form. A NAND flash memory device including a pass transistor and applying a different level of voltage to the plurality of local word lines by varying threshold voltages of each of the plurality of pass transistors is provided.

Preferably, threshold voltages of pass transistors for transmitting the global word line voltage to the local word lines respectively connected to the memory cells at both ends of the cell string may be set to the memory cells except for both ends of the cell string. It is effective to make it smaller than the threshold voltage of pass transistors which transfer the global word line voltage to the connected local word lines.

Preferably, the threshold voltages of the pass transistors for transmitting the global word line voltage to the local word lines connected to the memory cells at both ends of the cell string are set to Vt1, and except for both ends of the cell string. When the threshold voltage Vt2 of the pass transistors for transmitting the global wordline voltage to the local wordlines connected to the memory cells is set, it is effective that Vt2 is Vt1 + 0.3 to 0.5V.

Preferably, the plurality of drain select transistors are respectively connected to the drain terminals of the plurality of cell strings to transmit bit line signals according to local string select signals, and are connected to the source terminals of the plurality of cell strings. A source select transistor for transmitting a common source line signal, a string pass transistor for transmitting a global string selection signal according to an operating voltage, and a local source select signal for transmitting a global source selection signal according to the operating voltage; It is effective to further include a source pass transistor.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

In the NAND flash memory device, many errors occur during an erase or program check process due to a threshold voltage of a programmed cell. Therefore, it is very important to strictly control the threshold voltage disturbance of the programmed cell.

1 is a conceptual diagram illustrating a program of a NAND flash memory device according to the present invention.

Referring to FIG. 1, a program of a NAND flash memory cell according to the present invention applies a program voltage to a program cell gate, that is, a selected word line, among a plurality of cells of a cell string, and applies a program voltage to a pass cell gate, that is, a non-selected word line. Apply pass voltage. A ground power is applied to a bit line to which a cell to be programmed is connected so that FN tunneling occurs due to a voltage difference between the cell gate and the bulk, so that the program can be programmed. A power supply voltage is applied to a bit line to which a cell that is not to be programmed is connected to the channel line, thereby reducing the voltage difference between the cell gate and the bulk, thereby preventing FN tunneling. A voltage of 17 to 19 V is preferably used as the program voltage, and a voltage of 9 to 11 V is preferably used as the pass voltage.

The NAND flash memory device includes a cell string consisting of 16 or 32 cells in the form of a string, a string select transistor driven according to a string select signal between the drain terminal and the bit line of the cell string, a source terminal of the cell string and a common source. Between the lines includes a source select transistor for driving in accordance with the source select signal. In addition, the program of the NAND flash memory cell performs a program in units of pages. That is, in the case of a 512M NAND flash memory cell, the page unit is 512 bytes.

When the flash memory cell is programmed using the above-described structure and programming method, the threshold voltage of the memory cell to be programmed may not be programmed on both sides of the same bit line (string) as well as the program voltage applied to the memory cell to be programmed. The threshold voltage level of the programmed memory cell changes according to the pass voltage applied to the memory cell.

2 is a graph illustrating threshold voltages of programmed memory cells according to pass voltages.

Referring to FIG. 2, the threshold voltage of the programmed memory cell is about 1 V due to the pass voltage applied to the non-programmed cell. That is, as a result of measuring the threshold voltage of the programmed memory cell while changing the pass voltage from 0V to 10V, it can be seen that the threshold voltage of the programmed memory cell is increased by about 1V when the pass voltage is 0V. This is because the coupling of the pass voltage affects the memory cell to be programmed.

In addition, there is a relatively large difference in the time for programming a memory cell in a single string and the threshold voltage of the programmed memory cell.

3 is a distribution graph of threshold voltages of programmed memory cells shown for each word line in a single string.

Referring to FIG. 3, it can be seen that the program threshold voltage of the memory cells at both ends of the single string is relatively lower than that of the inner memory cell, and thus, the program speed of the cell is slow. That is, as a result of measuring the cell strings connected to the 16 word lines, the program threshold voltage of the memory cells connected to the first word line is about 1.65V, and the program threshold voltages of the memory cells connected to the 16th word line are about. It can be seen that the voltage is relatively lower than the program threshold voltage of the memory cell connected to the second to fifteenth word lines at 1.75V. This means that the inner memory cells connected to the second to fifteen word lines are coupled by the pass voltages of both sides of the cells as well as the program voltage during programming, while the opposite memory cells connected to the first and sixteen word lines are connected. Since there is only one side of the memory cell, the coupling voltage is relatively less affected by the pass voltage.

Therefore, in the present invention, the threshold voltage of the internal transistor of the X decoder that applies the external global word line voltage to the local word line may be adjusted to make the program rate of the memory cell and the threshold voltage of the programmed memory cell constant. That is, the threshold voltage of the pass transistor connected to both ends of the cell string memory cell is reduced relative to the threshold voltage of the pass transistor connected to the cell string inner memory cell, and the program voltage applied to both end memory cells is adjusted upward to increase the memory. The program speed of the cell and the threshold voltage of the programmed cell can be improved.

4 is a circuit diagram of a NAND flash memory device according to the present invention.

Referring to FIG. 4, the NAND flash memory device of the present invention includes a plurality of cell strings 10 in which a plurality of memory cells C1 to Cn connected to a plurality of local word lines WL0 to WLn are connected in a string form. And a plurality of pass transistors GWT1 to GWTn for applying the global word line signals GWL0 to GWLn to the local word lines WL0 to WLn according to the operating voltage VBSEL. Threshold voltages of the pass transistors GWL1 and GWLn transferring the global word line signals GWL0 and GWLn to the local word lines WL0 and WLn connected to the memory cells C1 and Cn at the end thereof are determined by the cell string 10. Pass transistors GWT2 through which the global word line signals GWL1 through GWLn-1 are transferred to the local word lines WL1 through WLn-1 connected to the memory cells C2 through Cn-1 except for both ends of the C1 through Cn-1. It is preferable to make it small compared with the threshold voltage of GWTn-1).

Also, a plurality of drain select transistors DST1 to DSTn connected to drain terminals of the plurality of cell strings 10 to transmit bit line BL0 to BLn signals according to the local string select signal DSL, Source selection transistors SST1 to SSTn connected to the source terminal of the cell string 10 to transmit the common source line CSL signal according to the local source selection signal SSL, and global string selection according to the operating voltage VBSEL. The string pass transistor GDST which transmits the signal GDSL as the local string selection signal DSL, and the source path which transmits the global source selection signal GSSL as the local source selection signal SSL according to the operating voltage VBSEL. It may further include a transistor GSST. In addition, an operation voltage generator 20 that receives an external address signal (not shown) and a high voltage (not shown) and generates an operating voltage VBSEL having a voltage level higher than that applied to the global word lines GWL0 to GWLn. ) May be further included. The apparatus may further include a page buffer (not shown) for buffering predetermined data from the bit lines BL0 to BLn or applying predetermined data to the bit lines BL0 to BLn according to an external address signal and a control signal. Can be.

As a result, the voltages applied to the gate terminals (word lines) of the memory cells C1 and Cn at both ends of the cell string 10 are excluded from the memory cells C2 to Cn except the memory cells at both ends of the cell string 10. It can be made relatively high compared with the voltage applied to the gate terminal of -1). That is, even when the global word lines GWL0 to GWLn are equally applied, the voltages applied to the local word lines WL0 to WLn while passing through the plurality of pass transistors GWT1 to GWTn are thresholds of the pass transistors GWT1 to GWTn. This can be caused by various voltages.

Hereinafter, a structure in which sixteen memory cells C1 to C16 form one cell string will be described as an example. That is, the first to sixteenth memory cells C1 to C16 include one string of cell strings, first to sixteenth local word lines WL0 to WL15 connected to each of them, and first to sixteenth local words. A description will be given based on the first to sixteenth pass transistors GWT1 to GWT16 respectively connected between the lines WL0 to WL15 and the first to sixteenth global word lines GWL0 to GWL15.

5A and 5B are conceptual views illustrating a voltage application method of a pass transistor according to the present invention.

4, 5A and 5B, the threshold voltages of the first and sixteenth pass transistors GWT1 and GWT16 are set to Vt1, and the threshold voltages of the second to fifteenth pass transistors GWT2 to GWT15 are set to Vt2. do. Vt1 preferably has a value smaller than Vt2. That is, it is preferable that Vt2 is Vt1 + 0.3-0.5V.

In this case, when Vpp + Vt1 is applied to the operating voltage VBSEL and a voltage of Vpp + Vt1 is applied to the first to sixteenth global word line GWL0 to GWL15 signals, the first and sixteenth pass transistors GWT1 and GWT16 are applied. A voltage of Vpp is applied to the first and sixteenth local word lines WL0 and WL15 through θ. That is, the values (Vpp + Vt1-Vt1) dropped by the threshold voltages of the first and sixteenth pass transistors GWT1 and GWT16 described above are applied (see FIG. 5A). Meanwhile, a voltage of Vpp + Vt1-Vt2 is applied to the second to fifteenth local word lines WL1 to WL14 through the second to fifteenth pass transistors GWT2 to GWT15 (see FIG. 5B).

As the program voltage is differentiated and applied to each word line, the program threshold voltage of the cell connected to both word lines may be the same as the program threshold voltage of the cell connected to the inner word line. This can improve the disturbance of the program threshold voltage of the programmed cell. The program pulse can be reduced by improving the discontinuity of the program threshold voltage, and the program time can be reduced by reducing the program pulse, thereby improving the characteristics of the device. It also reduces the test time of the device. The present invention can also be applied to a multilevel flash memory device having various states depending on the threshold voltage of the cell.

As described above, the present invention may apply the program voltage differently for each word line by adjusting the threshold voltage of the transistor applying the global word line signal to the local word line.

In addition, the disturbance of the program threshold voltage of the programmed cell can be improved by making the program threshold voltage of the cell connected to both word lines equal to the program threshold voltage of the cell connected to the inner word line.

In addition, it is possible to reduce the program pulse by improving the disturbance of the program threshold voltage, and to improve the characteristics of the device by reducing the program time by reducing the program pulse.

Claims (4)

A plurality of cell strings each having a plurality of memory cells connected to a plurality of local word lines in a string form; And A plurality of pass transistors for applying a plurality of global word line voltages to the plurality of local word lines in accordance with an operating voltage; And applying different levels of voltage to the plurality of local word lines by varying threshold voltages of the plurality of pass transistors. The method of claim 1, Threshold voltages of pass transistors for transmitting the global word line voltage to the local word lines respectively connected to the memory cells at both ends of the cell string, respectively connected to the memory cells except for both ends of the cell string. A NAND flash memory device having a smaller value than a threshold voltage of pass transistors for transmitting the global word line voltage to local word lines. The method of claim 2, The threshold voltages of the pass transistors for transmitting the global word line voltage to the local word lines connected to the memory cells at both ends of the cell string are set to Vt1, and the memory cells except for both ends of the cell string; And a threshold voltage Vt2 of the pass transistors for transmitting the global wordline voltage to the connected local wordlines, wherein Vt2 is 1.1 Vt1 to 3 Vt1. The method of claim 1, A plurality of drain select transistors respectively connected to drain terminals of the plurality of cell strings to transmit bit line signals according to local string select signals; A source select transistor connected to source terminals of the plurality of cell strings to transmit a common source line signal according to a local source select signal; A string pass transistor configured to transmit a global string select signal as a local string select signal according to an operating voltage; And And a source pass transistor configured to transmit a global source select signal as a local source select signal according to the operating voltage.

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