KR100980017B1 - Thin film transistor array panel - Google Patents

Abstract

The thin film transistor array panel according to the present invention overlaps with an insulating substrate, a gate line formed on the insulated substrate, a gate insulating film formed on the gate line, a semiconductor layer having a ring or band-shaped channel portion formed on the gate insulating film, and a semiconductor layer. A source electrode having a cutout portion exposing the channel portion, a data line connected to the source electrode and defining a pixel area crossing the gate line, and a drain formed on the semiconductor layer exposed by the cutout portion and maintaining a constant distance from the source electrode. And a red, green and blue color filter formed on the electrode and the pixel partitioned by the data line, and a pixel electrode formed on the color filter and connected to the drain electrode.

Thin Film Transistor, Color Filter, Opening Ratio, Channel

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3 is a cross-sectional view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

4A, 5A, 6A, 7A, and 8A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of FIG. 3.

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

FIG. 5B is a cross sectional view at the next step of FIG. 4B;

FIG. 6B is a cross sectional view at the next step of FIG. 5B;

FIG. 7B is a cross sectional view at the next step of FIG. 6B;

FIG. 8B is a cross sectional view at the next step of FIG. 7B;

9A and 9B are views for explaining the present invention in detail.

10 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line XI-XI ′ of FIG. 10;

12 is a cross-sectional view at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of FIG. 10.

13A is a layout view at the next step of FIG. 12,                 

FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb ′ of FIG. 13A;

FIG. 14A is a layout view at the next step of FIG. 13A, and FIG.

FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb ′ of FIG. 14A.

The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel including a color filter.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode, a color filter, and the like are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

The thin film transistor array panel may include a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to a gate line and a data line in each pixel, and a pixel electrode connected to the thin film transistor. And so on.

The liquid crystal display requires a constant storage capacitor (Cst) to maintain the alignment of the liquid crystal for a predetermined time, and includes a storage electrode overlapping the pixel electrode with a dielectric material therebetween to form the liquid crystal.                         

In this case, the drain electrode of the thin film transistor is connected to the pixel electrode through the contact hole, so that the drain electrode is extended to overlap the storage electrode in order to substantially form the storage capacitor. In addition, since the drain electrode extends from the contact hole connected to the pixel electrode to the channel of the thin film transistor, it causes a decrease in the aperture ratio of the pixel.

In addition, parasitic capacitances Cgs and Cgd are formed between the gate electrode, the source electrode, and the drain electrode, and the parasitic capacitance is changed according to the size of the overlapping area of the gate electrode, the source electrode, and the drain electrode. However, when the parasitic capacitance is severely misaligned due to misalignment during the manufacturing process, a flicker occurs and the image quality of the liquid crystal display is degraded.

The present invention has been made to solve the above problems, and provides a thin film transistor array panel which can secure high brightness by minimizing the change in parasitic capacitance due to misalignment and improving the aperture ratio of the pixel.

In order to solve this problem, the present invention provides the following thin film transistor array panel.

Specifically, an insulating substrate, a gate line formed on the insulating substrate, a gate insulating film formed on the gate line, a semiconductor layer having a ring or band-shaped channel portion formed on the gate insulating film, overlapping the semiconductor layer and exposing the channel portion A source electrode having a cutout portion; a data line connected to the source electrode and crossing the gate line to define a pixel region; and a drain electrode formed on a semiconductor layer exposed by the cutout portion and having a constant distance from the source electrode. And a red, green and blue color filter formed on the pixel partitioned by the pixel, and a pixel electrode formed on the color filter and connected to the drain electrode.

It is preferable to further include an ohmic contact layer formed between the semiconductor layer and the data line.

In this case, it is preferable that the data line, the source electrode, and the drain electrode have the same planar pattern as the ohmic contact layer, and the semiconductor layer has the same planar pattern except for the channel between the drain electrode and the source electrode.

It is preferable that a protective film made of an organic material is further formed between the color filter and the pixel electrode.

In addition, the cutout and the drain electrode are preferably formed in a circular shape, and it is preferable that the edges of adjacent color filters overlap on the data line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on top" of another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is 'just above' another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, the gate line 121 extending in one direction is formed on the transparent insulating substrate 110. A portion of the gate line 121 protrudes, and the protruding portion is used as the gate electrode 124 and has a semicircular shape.

One end of the gate line 121 is used to receive a signal transmitted from a gate driving circuit (not shown), and may have a width wider than the width of the gate line 121, and the gate driving circuit is formed on the upper portion of the substrate. If directly formed at the gate of the gate drive circuit is connected directly.

A gate insulating layer 140 formed of silicon nitride, silicon oxide, or the like is formed on the substrate 110 to cover them 121 and 124.

A semiconductor layer 154 made of amorphous silicon that is not doped with impurities is formed in a predetermined region of the gate insulating layer 140. The semiconductor layer 154 forms a channel between the source electrode 173 and the drain electrode 175 to be described later and overlaps the gate electrode 124 and has a circular shape.

In addition, ohmic contacts 161 and 165 including amorphous silicon or silicide doped with impurities are formed on the semiconductor layer 154. The ohmic contacts 161 and 165 may include a source ohmic contact 161 and a drain ohmic contact 165.

The source ohmic contact layer 161 has a circular band or ring shape, and the drain ohmic contact layer 165 is positioned in the center of the source ohmic contact layer 161 and has an island shape. , 165 are maintained at a constant interval, and the semiconductor layer 154 is exposed between them 161 and 165. These 161 and 165 have the same planar pattern as the semiconductor layer 154 except for a predetermined region of the semiconductor layer 154. The semiconductor layer 154 exposed between them 161 and 165 is a channel portion that forms a channel of the thin film transistor, and is formed in the form of a donut (or ring). In this case, the semiconductor layer 154 and the source portion resistivity The contact layer 161 may extend along the data line 171 formed later.

A data line 171 is formed on the gate insulating layer 140 to cross the gate line 121 and define a pixel area. A portion of the data line 171 protrudes, and the protruding portion has a ring shape and overlaps the ohmic contact layer 161 to be used as the source electrode 173 of the thin film transistor. At this time, the source electrode 173 has a cutout 176 exposing the cutout 601 of the source ohmic contact layer 161. One end portion 179 of the data line is formed wider than the width of the data line 171 to receive a signal transmitted from a data driving circuit (not shown).

An island shape is formed on the drain ohmic contact layer 165 at the center of the ring-shaped source electrode 173, and a drain electrode 175 facing the source electrode 173 is formed around the channel portion of the thin film transistor. have.

As such, by designing the channel portion of the thin film transistor between the drain electrode 175 and the source electrode 173 in a donut shape, the width of the channel portion can be maximized even in a small area, and W / L (W: thin film transistor) exhibiting characteristics of the thin film transistor. The width of the channel portion, L: the gap between the source electrode and the drain electrode, the channel portion depth of the thin film transistor) can be increased to maximize the charge rate of the pixel. In addition, since the drain electrode 175 is not formed beyond the semiconductor layer 154, the aperture ratio of the pixel may be maximized.

The passivation layer 180 is formed to cover the semiconductor layer 154 that is not covered by the source electrode 173 and the drain electrode 175. The passivation layer 180 is made of an inorganic material such as silicon oxide or silicon nitride, and is not necessary and is selected as necessary to protect the pigment from diffusing to the lower layer from the color filters 230R, 230G, and 230B described below.

Red, green, and blue color filters 230R, 230G, and 230B extend in a direction parallel to the data line 171 along a pixel column formed on the gate insulating layer 140 and partitioned by the data line 171. The red, green, and blue filters 230R, 230G, and 230B are alternately formed in the pixel column.

Here, the red, green, and blue filters 230R, 230G, and 230B are not formed at the end portion 179 of the gate line 121 or the data line 171 to be connected to an external circuit. The edges of these 230R, 230G, and 230B overlap the upper portion of the data line 171. As such, the edges of the color filters 230R, 230G, and 230B are formed to overlap each other, thereby blocking light leaking between the pixel areas, and the red, green, and blue color filters are combined at the upper portion of the data line 171. It can also be arranged in an overlap.

The pixel electrode 190 made of a transparent material such as ITO or IZO is formed on the color filters 230R, 230G, and 230B. The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 formed over the color filters 230R, 230G, and 230B and the passivation layer 180 to receive an image signal.

The pixel electrode 190 extends over the data line 171 to increase the aperture ratio of the pixel. In this case, the pixel electrode 190 and the data line 171 are provided with red, green, and blue color filters made of an insulating material having a low dielectric constant, so that a constant interval can be secured at a wide width. Parasitic doses occurring between can be minimized and parasitic dose variations can also be minimized.

On the color filter, there is also formed a contact auxiliary member 82 which is connected to one end 179 of the data line through the contact hole 182. When the end portion of the gate line 121 also has a structure for connecting with the driving circuit like the end portion 179 of the data line, a gate contact auxiliary member is formed on the passivation layer 180.

However, the gate driving circuit may be formed together with the thin film transistor on the substrate 110. In this case, since the gate line 121 and the thin film transistor are directly connected, a contact auxiliary member is not required.                     

The contact assisting member 82 is connected to one end 179 of the data line through the contact hole 182. The contact assisting member 82 is not essential to serve to complement the adhesion with the external circuit device and to protect the ends, and the application thereof is optional.

3 will be described another embodiment of the present invention.

3 is a diagram illustrating a structure of a thin film transistor array panel according to another exemplary embodiment, and is a cross-sectional view taken along the line II-II ′ of FIG. 1.

The embodiment shown in FIG. 3 further includes an interlayer insulating film 801 between the color filters 230R, 230G, 230B and the pixel electrode 190. The interlayer insulating layer 801 may be formed by coating an organic material having a low dielectric constant of 4.0 or less or by depositing an inorganic material by chemical vapor deposition. In the case of forming the organic material, the data line 171 and the pixel electrode ( It is possible to effectively prevent the coupling phenomenon by maintaining a greater distance between the 190) than the embodiment shown in FIG.

A method of manufacturing the TFT panel according to the exemplary embodiment of the present invention described above will be described in detail with reference to FIGS. 4A to 8B and FIGS. 1 and 3.

4A, 5A, 6A, and 7A are layout views at an intermediate stage in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 1 and 3, and FIG. 4B is a line IVb-IVb ′ of FIG. 4A. 5B is a sectional view at the next step of FIG. 4B, FIG. 6B is a sectional view at the next step of FIG. 5B, FIG. 7B is a sectional view at the next step of FIG. 6B, and FIG. 8B is FIG. 7B Is a cross-sectional view at the next step.                     

First, as shown in FIGS. 4A to 4B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. do. Thereafter, the metal layer is dry or wet etched by a photolithography process using a mask to form gate lines 121 and 124 on the substrate 110. At this time, the sidewalls of the 121 and 124 are formed to be tapered, and the tapered structure allows the upper layer formed thereon to closely adhere to the lower layer, and gently induces a profile of the upper layer.

Next, as shown in FIGS. 5A and 5B, a gate insulating film 140 made of silicon nitride or silicon oxide, a semiconductor such as hydrogenated amorphous silicon, and an amorphous silicon doped at high concentration with n-type impurities such as phosphorus (P) are used. Continuous deposition using chemical vapor deposition and patterning by a photolithography process using a mask, patterning an amorphous silicon layer doped with impurities and an amorphous silicon layer not doped with impurities in order to form a channel layer on the semiconductor layer 154 and the upper portion thereof. The ohmic contact layer 160 is connected.

6A and 6B, a conductive layer such as a metal is deposited by sputtering or the like, and then patterned by a photolithography process using a mask to form a data line 171 and a drain electrode having the source electrode 173. 175 is formed. At this time, the cutout 176 of the source electrode 173 is formed.

Subsequently, the ohmic contact layer 160 that is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175 to expose the ohmic contact layer 160. ) Into two parts (161, 165).                     

Although the source electrode 173 is formed in a ring shape and misalignment occurs, the overlapping areas of the source electrode 173 and the gate electrode 124 are compensated for each other to maintain a uniform parasitic capacitance Cgs. That is, as shown in Fig. 9A, when the source electrode 173 is vertically moved by L1 from the original position due to misalignment, the parasitic capacitance of the L1 portion is reduced. However, the source electrode 173 forms a new overlapping region L2 by the reduced L1, so that a new parasitic capacitance is generated by the reduced parasitic capacitance. Thus, the overall parasitic capacity remains uniform. This change in parasitic capacitance is equally applied to cases where misalignment occurs in the horizontal direction, as in FIG. 9B.

Next, as shown in FIGS. 7A to 7B, an inorganic material such as silicon nitride or silicon oxide is laminated to form the passivation layer 180. Thereafter, a photosensitive organic material including red, green, and blue pigments is sequentially applied on the passivation layer 180, and red, green, and blue color filters 230R, 230G, and 230B are sequentially formed through a photographic process.

When the red, green, and blue color filters 230R, 230G, and 230B are formed by a photo process using a mask, the openings 235 are formed in portions corresponding to the drain electrodes 175.

When the interlayer insulating film 801 is added as shown in FIG. 3, an organic material having a low dielectric constant of 4.0 or less is coated on the color filters 230R, 230G, and 230B, or an inorganic material is deposited by chemical vapor deposition to form an interlayer insulating film ( 801.

The interlayer insulating layer 801 and the passivation layer 180 are then patterned by a photolithography process using a mask to expose the contact hole 185 exposing the opening 235 and one end portion 179 of the data line 171. The contact hole 182 is formed.                     

1 and 3, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the substrate 110 and patterned by a photolithography process using a mask. ) And a pixel electrode 190 connected to the drain electrode 175 through the contact hole 185 and a contact auxiliary member 82 connected to one end portion 179 of the data line through the contact hole 182. .

The thin film transistor array panel according to the above embodiments may be manufactured by a photolithography process using each photoresist layer except for color filters using different photoresist patterns as an etching mask. The thin film transistor array panel may be completed through a manufacturing method according to another embodiment. Can be. In this case, the thin film transistor array panel has a structure different from the above embodiment, which will be described in detail with reference to the accompanying drawings.

FIG. 10 is a layout view of a thin film transistor array panel according to another exemplary embodiment, and FIG. 11 is a cross-sectional view taken along the line XI-XI ′ of FIG. 10.

First, the structure of the completed thin film transistor array panel will be described in detail with reference to FIGS. 10 and 11. In the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 10 and 11, most single layer structures are the same as those of FIGS. 1 and 2. That is, the gate line 121 is formed on the insulating substrate 110, the gate insulating layer 140 is formed to cover the gate line 121, and the semiconductor layer 154 and the ohmic contact layer are formed on the gate insulating layer 140. 161 and 165 are formed, and the data line 175 and the drain electrode 175 are formed on the ohmic contact layers 161 and 165, and the passivation layer 180 is formed to cover the 171 and 175. The pixel electrode 190 connected to the drain electrode 175 is formed on the passivation layer 180.

However, the data line 171 and the drain electrode 175 have the same planar pattern as the ohmic contacts 161 and 165, and the semiconductor layer 154 has a channel portion between the source electrode 173 and the drain electrode 175. It has the same planar pattern as the ohmic contacts 161 and 165 except that it is connected.

Next, a method of manufacturing the thin film transistor array panel according to the exemplary embodiment illustrated in FIGS. 10 and 11 will be described in detail with reference to the accompanying drawings of FIGS. 4A, 4B, and 12 to 14B.

12 is a cross-sectional view at an intermediate stage of the method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, FIG. 13 is a cross-sectional view at a next stage of FIG. 12, FIG. 14A is a layout view at a next stage of FIG. 13, FIG. 14B is a cross-sectional view taken along the line XIVb-XIVb ′ of FIG. 14A. First, as shown in FIGS. 4A and 4B, a metal such as chromium, molybdenum, aluminum, silver, or an alloy thereof is deposited on the transparent insulating substrate 110 by sputtering to form a single layer or a plurality of gate metal layers. . Thereafter, the metal layer is dry or wet etched by a photolithography process to form gate lines 121 and 124 on the substrate 110. Sidewalls of these 121 and 124 are formed to be tapered during etching, and the tapered shape allows the layers formed thereon to be in close contact with each other.

Subsequently, as shown in FIG. 12, an insulating material such as silicon nitride covering the gate lines 121 and 124 is deposited to form the gate insulating layer 140, and then an amorphous dopant is not doped on the gate insulating layer 140. By depositing silicon and an amorphous silicon doped with impurities, an amorphous silicon film 150 not doped with impurities and an amorphous silicon film 160 doped with impurities are sequentially stacked. The amorphous silicon film 150 not doped with impurities is formed of hydrogenated amorphous silicon, and the like, and the amorphous silicon film 160 doped with impurities is heavily doped with an n-type impurity such as phosphorus (P). It is formed of silicon or silicide.

After depositing a metal such as aluminum, silver, chromium, molybdenum or an alloy thereof by sputtering on the amorphous silicon film 160 doped with impurities in succession to form a single layer or a plurality of metal films 170, A photosensitive material is coated on the metal layer 170 to form a photoresist film, and then exposed and developed to form photoresist patterns 52 and 54 having different thicknesses.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.                     

Given the appropriate process conditions, the underlying layers may be selectively etched due to the difference in thickness of the photoresist pattern 52, 54.

For convenience of description, a portion of the conductor layer 170 positioned at the portion where the wiring is to be formed, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 without doping impurities are referred to as the wiring portion A. The portion of the conductor layer 170, the impurity doped amorphous silicon layer 160 and the impurity doped amorphous silicon layer 150 located at the portion where the channel is formed is called a channel portion B, and the channel and wiring portions A portion of the conductor layer 170, the amorphous silicon layer 160 doped with impurities, and the amorphous silicon layer 150 not doped with impurities is located in the other region (C).

One example of the order of forming such a structure is as follows.

First, (1) removing the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other part (C), (2) removing the photoresist film 54 located in the channel part B. , (3) removing the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel portion B, and (4) removing the photosensitive film 52 located in the wiring portion A.

Other methods include (1) removing the conductor layer 170 located in the other portion (C), (2) removing the photosensitive film 54 located in the channel portion (B), and (3) impurity amorphous in the other portion (C). Removal of the silicon layer 160 and the amorphous silicon layer 150, (4) removal of the conductor layer located in the channel portion B, (5) removal of the photosensitive film 52 located in the wiring region A, and (6) channel portion. It may also proceed in order to remove the impurity amorphous silicon layer 160 located in (B).

This section describes the first example.                     

First, as shown in FIGS. 13A and 13B, the data line 171 including the source electrode 173, the drain electrode 175, the ohmic contacts 161 and 165, and the semiconductor layer 154 are formed through a series of etching steps. ).

In more detail, first, the conductive layer 170 exposed to the other region C is removed by wet etching or dry etching, and the other portion C of the amorphous silicon layer 160 doped with impurities thereunder. Expose

The data line 171 and the drain electrode 175 are still attached. In the case of using dry etching, the upper portions of the photoresist films 52 and 54 may be cut to a certain thickness.

Next, the amorphous silicon layer 160 doped with impurities in the other portion C and the amorphous silicon layer 150 without dopants under the impurities are removed, and the photoresist film 54 of the channel portion B is removed. It removes to expose the lower conductor 170.

Removal of the photoresist of the channel portion B may be performed simultaneously with or separately from the removal of the amorphous silicon layer 160 doped with impurities in the other region C and the amorphous silicon layer 150 without the impurities. Residue of the photoresist film 54 remaining in the channel region B is removed by ashing. In this step, the semiconductor layer 154 is completed.

If the conductor layer 170 is a material that can be dry etched, the manufacturing process may be performed by successively dry etching the amorphous silicon layer 160 doped with impurities below and the amorphous silicon layer 150 doped with impurities. In this case, it may or may not be performed in an in-situ manner in which dry etching is sequentially performed on the three layers 170, 160, and 150 in the same etching chamber.

The conductor 170 located in the next channel portion B and the amorphous silicon layer 160 doped with impurities are etched and removed. Further, the photosensitive film 52 of the remaining wiring portion A is also removed.

In this case, the upper portion of the amorphous silicon layer which is not doped with impurities in the channel portion B may be partially removed to reduce the thickness, and the photoresist layer 52 of the wiring portion A may be etched to some extent.

In this way, each of the conductors 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175. In this case, the source electrode 173 has a circular cutout 176. The amorphous silicon layer 160 doped with impurities is also divided into two portions 161 and 165 by the cutout 601.

The data lines 171, 173, and 179 and the drain electrode 175 may also be formed in a tapered shape like the gate lines 121 and 124 to increase adhesion to the upper layer.

Next, as shown in FIGS. 14A and 14B, the protective layer 180 is formed by stacking silicon nitride or silicon oxide so as to cover the semiconductor layer 154 that is not covered by the data lines 171 and 173 and the drain electrode 175. Form.

Thereafter, the photosensitive organic materials including red, green, and blue pigments are sequentially applied, and red, green, and blue color filters 230R, 230G, and 230B are sequentially formed through a photographic process.

When the red, green, and blue color filters 230R, 230G, and 230B are formed in the photolithography process, the openings 235 are formed in portions corresponding to the drain electrodes 175.

Subsequently, as shown in FIGS. 10 and 11, a transparent conductive material such as ITO or IZO is deposited on the substrate 110, and is etched by a photolithography process using a mask to etch one end of the data line through the contact hole 182. The pixel electrode 190 connected to the drain electrode 175 is formed through the contact auxiliary member 82, the contact hole 185, and the opening 235.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Through the above configuration, the width of the channel portion can be maximized even in a small area, and the charge rate of the pixel can be maximized by increasing the W / L indicating the characteristics of the thin film transistor. In addition, since the drain electrode is positioned only on the semiconductor layer, the aperture ratio of the pixel may be maximized.

In addition, by forming a source electrode having a circular cutout, the parasitic capacitance between the source electrode and the gate electrode may be kept constant to minimize the deterioration of image quality, thereby providing a high quality thin film transistor array panel.

Claims (8)

Insulation board, A gate line formed on the insulating substrate, A gate insulating film formed on the gate line, A semiconductor layer having a ring or band-shaped channel portion formed on the gate insulating film, A source electrode overlapping the semiconductor layer and having a cutout portion exposing the channel portion; A data line connected to the source electrode, A drain electrode formed on the semiconductor layer exposed by the cutout and maintaining a constant distance from the source electrode; Red, green and blue color filters formed on the substrate, A pixel electrode formed on the color filter and connected to the drain electrode; The pixel electrode covers the entire channel portion. In claim 1, And a resistive contact layer formed between the semiconductor layer and the data line. The method of claim 1 or 2, A thin film transistor array panel further comprising a passivation layer formed between the color filter and the pixel electrode. In claim 2, The data line, the source electrode and the drain electrode have the same planar pattern as the ohmic contact layer. The semiconductor layer includes a channel portion corresponding to the drain electrode and the source electrode, and a wiring portion overlapping the data line, the source electrode, and the drain electrode. The wiring portion of the semiconductor layer has the same planar pattern as the data line, the source electrode, and the drain electrode. In claim 3, The cutout and the drain electrode have a circular shape. In claim 3, Edges of the color filters adjacent to each other overlap the upper portion of the data line. In claim 3, The passivation layer is formed of an organic material. In claim 1, A boundary line of the pixel electrode is disposed on the data line and the gate line.

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