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KR101016338B1 - Transistor manufacturing method of semiconductor device - Google Patents

Transistor manufacturing method of semiconductor device Download PDF

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KR101016338B1
KR101016338B1 KR1020030073076A KR20030073076A KR101016338B1 KR 101016338 B1 KR101016338 B1 KR 101016338B1 KR 1020030073076 A KR1020030073076 A KR 1020030073076A KR 20030073076 A KR20030073076 A KR 20030073076A KR 101016338 B1 KR101016338 B1 KR 101016338B1
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gate
thickness
conductivity type
well
active region
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KR20050037803A (en
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백성학
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0179—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 NMOS 트랜지스터의 게이트 도핑 효율을 향상시키면서 얕은 접합을 용이하게 구현함과 동시에 PMOS 트랜지스터에서의 보론 침투를 효과적으로 방지할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공한다.The present invention provides a method of manufacturing a transistor of a semiconductor device capable of easily implementing shallow junctions while effectively improving the gate doping efficiency of an NMOS transistor and at the same time effectively preventing boron penetration in the PMOS transistor.

본 발명은 제 1 도전형 제 1 웰 및 제 1 도전형과 반대의 제 2 도전형 제 2 웰이 형성되고, 필드절연막에 의해 제 1 웰에는 제 1 액티브 영역이 정의되고 제 2 웰에는 제 2 액티브 영역이 정의된 반도체 기판을 준비하는 단계; 기판 상에 게이트 절연막과 제 1 두께의 폴리실리콘막을 순차적으로 형성하는 단계; 및 제 1 액티브 영역 상의 폴리실리콘막을 소정 두께만큼 제 1 식각하는 단계; 및 폴리실리콘막을 제 2 식각하여 제 1 및 제 2 액티브 영역 상에 제 1 두께보다 낮은 제 2 두께를 가지는 제 1 게이트와 제 1 두께를 가지는 제 2 게이트를 각각 형성하는 단계를 포함한다. 바람직하게, 제 1 도전형은 P형이고, 제 2 도전형은 N형이다.
According to the present invention, a first conductivity type first well and a second conductivity type second well opposite to the first conductivity type are formed, a first active region is defined in the first well and a second is formed in the second well by the field insulating film. Preparing a semiconductor substrate in which an active region is defined; Sequentially forming a gate insulating film and a polysilicon film of a first thickness on the substrate; First etching the polysilicon film on the first active region by a predetermined thickness; And etching second the polysilicon layer to form a first gate having a second thickness lower than the first thickness and a second gate having the first thickness on the first and second active regions, respectively. Preferably, the first conductivity type is P type and the second conductivity type is N type.

NMOS, PMOS, 트랜지스터, 얕은 접합, 게이트NMOS, PMOS, Transistor, Shallow Junction, Gate

Description

반도체 소자의 트랜지스터 제조방법{METHOD OF MANUFACTURING TRANSISTOR FOR SEMICONDUCTOR DEVICE} METHODS OF MANUFACTURING TRANSISTOR FOR SEMICONDUCTOR DEVICE             

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a transistor manufacturing method of a semiconductor device in accordance with an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

10 : 반도체 기판 11A : P웰10: semiconductor substrate 11A: P well

11B : N웰 12 : 필드절연막11B: N well 12: field insulating film

13 : 게이트 절연막 14 : 폴리실리콘막13 gate insulating film 14 polysilicon film

14A, 14B : 제 1 및 제 2 게이트14A, 14B: first and second gate

15, 16 : 제 1 및 제 2 포토레지스트 패턴15, 16: first and second photoresist pattern

17 : N＋ 소오스/드레인 접합영역17: N + source / drain junction region

18 : P＋ 소오스/드레인 접합영역
18: P + source / drain junction region

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 서로 다른 두께의 듀얼(dual) 게이트를 적용한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a transistor of a semiconductor device in which dual gates having different thicknesses are applied.

일반적으로, 서브 마이크론(sub micron) 이하의 고집적 반도체 소자의 트랜지스터 제조시 이온주입에 의해 도핑된 폴리실리콘막으로 게이트를 형성하고, 이온주입 시 접합영역을 동시에 형성하고 있다.In general, a gate is formed of a polysilicon film doped by ion implantation during the fabrication of a transistor of a sub-micron or less highly integrated semiconductor device, and a junction region is simultaneously formed during ion implantation.

한편, NMOS 트랜지스터의 경우에는 얕은 접합(shallow junction) 구현을 위해 도즈(dose) 및 에너지를 게이트 도핑 효율까지 만족시키기가 어렵기 때문에 별도의 마스크 제작 및 이온주입 등의 부가공정을 더 수행하여야 하고, 이러한 부가공정을 배제하기 위해서는 게이트 두께를 낮추어야 한다.On the other hand, in the case of the NMOS transistor, it is difficult to satisfy the dose and energy to the gate doping efficiency in order to implement a shallow junction, so additional processing such as fabrication of a separate mask and ion implantation should be further performed. To eliminate this additional process, the gate thickness must be lowered.

그러나, 게이트 두께를 낮추게 되면 PMOS 트랜지스터에서 보론(Boron; B) 침투가 유발되어 소자 특성이 저하되는 또 다른 문제가 발생하게 된다.
However, lowering the gate thickness causes boron (B) penetration in the PMOS transistor, resulting in another problem of deterioration of device characteristics.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, NMOS 트랜지스터의 게이트 도핑 효율을 향상시키면서 얕은 접합을 용이하게 구현함과 동시에 PMOS 트랜지스터에서의 보론 침투를 효과적으로 방지할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.

The present invention has been proposed to solve the above problems of the prior art, a semiconductor device capable of easily implementing a shallow junction while effectively improving the gate doping efficiency of an NMOS transistor and at the same time effectively preventing boron penetration in a PMOS transistor. Its purpose is to provide a method for manufacturing a transistor.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 제 1 도전형 제 1 웰 및 제 1 도전형과 반대의 제 2 도전형 제 2 웰이 형성되고, 필드절연막에 의해 제 1 웰에는 제 1 액티브 영역이 정의되고 제 2 웰에는 제 2 액티브 영역이 정의된 반도체 기판을 준비하는 단계; 기판 상에 게이트 절연막과 제 1 두께의 폴리실리콘막을 순차적으로 형성하는 단계; 및 제 1 액티브 영역 상의 폴리실리콘막을 소정 두께만큼 제 1 식각하는 단계; 폴리실리콘막을 제 2 식각하여 제 1 및 제 2 액티브 영역 상에 제 1 두께보다 낮은 제 2 두께를 가지는 제 1 게이트와 제 1 두께를 가지는 제 2 게이트를 각각 형성하는 단계; 제 1 및 제 2 게이트 측벽에 스페이서를 형성하는 단계; 제 1 액티브 영역으로 제 2 도전형 불순물이온을 주입하여 제 1 접합영역을 형성함과 동시에 상기 제 1 게이트를 도핑하는 단계; 및 제 2 액티브 영역으로 제 1 도전형 불순물이온을 주입하여 제 2 접합영역을 형성함과 동시에 제 2 게이트를 도핑하는 단계를 포함하는 반도체 소자의 트랜지스터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is the first conductivity type first well and the second conductivity type second well opposite to the first conductivity type is formed, the field Preparing a semiconductor substrate having a first active region defined in a first well and a second active region defined in a second well by an insulating film; Sequentially forming a gate insulating film and a polysilicon film of a first thickness on the substrate; First etching the polysilicon film on the first active region by a predetermined thickness; Etching the polysilicon film to form a first gate having a second thickness lower than the first thickness and a second gate having the first thickness on the first and second active regions, respectively; Forming spacers on the first and second gate sidewalls; Implanting a second conductivity type impurity ion into a first active region to form a first junction region and simultaneously doping the first gate; And implanting the first conductivity type impurity ions into the second active region to form a second junction region and simultaneously doping the second gate.

바람직하게, 폴리실리콘막의 제 1 식각과 제 1 접합영역 형성은 동일 마스크를 이용하여 수행한다.Preferably, the first etching and the first junction region formation of the polysilicon film are performed using the same mask.

더욱 바람직하게, 제 1 도전형은 P형이고, 제 2 도전형은 N형이다.More preferably, the first conductivity type is P type and the second conductivity type is N type.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다. Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.                     

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a transistor manufacturing method of a semiconductor device in accordance with an embodiment of the present invention.

도 1a에 도시된 바와 같이, P웰(11A) 및 N웰(11B)이 형성된 반도체 기판(10)에 필드 산화막(12)을 형성하여 P웰(11A) 및 N웰(11B)에 NMOS 트랜지스터용 제 1 액티브 영역과 PMOS 트랜지스터용 제 2 액티브 영역을 각각 정의한다. 그 다음, 기판 전면 상에 게이트 절연막(13)을 형성하고, 그 상부에 제 1 두께로 폴리실리콘막(14)을 증착한다.As shown in FIG. 1A, a field oxide film 12 is formed on a semiconductor substrate 10 on which P wells 11A and N wells 11B are formed, thereby forming an NMOS transistor for P wells 11A and N wells 11B. The first active region and the second active region for the PMOS transistor are defined, respectively. Next, a gate insulating film 13 is formed on the entire surface of the substrate, and a polysilicon film 14 is deposited on the top thereof with a first thickness.

도 1b에 도시된 바와 같이, 폴리실리콘막(14) 상부에 통상의 N＋ 소오스/드레인 마스크(미도시)를 이용하여 포토리소그라피에 P웰(11A)의 제 1 액티브 영역만을 오픈시키는 제 1 포토레지스트 패턴(15)을 형성한다. As shown in FIG. 1B, a first photo opening only the first active region of the P well 11A in photolithography using a conventional N + source / drain mask (not shown) on the polysilicon film 14. The resist pattern 15 is formed.

도 1c에 도시된 바와 같이, 제 1 포토레지스트 패턴(15)을 이용하여 오픈된 영역의 폴리실리콘막(14)을 소정 두께, 바람직하게 200 내지 400Å 정도 식각하여 제 1 두께보다 낮은 제 2 두께가 되도록 한다.As shown in FIG. 1C, the polysilicon film 14 of the open region is etched by a predetermined thickness, preferably about 200 to 400 microns, using the first photoresist pattern 15 to obtain a second thickness lower than the first thickness. Be sure to

도 1d에 도시된 바와 같이, 공지된 방법에 의해 제 1 포토레지스트 패턴(15)을 제거하고, 폴리실리콘막(14) 상부에 게이트 마스크(미도시)를 이용하여 포토리소그라피에 의해 폴리실리콘막(14)을 소정 부분 마스킹하는 제 2 포토레지스트 패턴(16)을 형성한다. As shown in FIG. 1D, the first photoresist pattern 15 is removed by a known method, and a polysilicon film (not shown) is formed by photolithography using a gate mask (not shown) on the polysilicon film 14. A second photoresist pattern 16 is formed to partially mask 14).

도 1e에 도시된 바와 같이, 제 2 포토레지스트 패턴(16)을 이용하여 폴리실리콘막(14)을 식각하여 P웰(11A) 및 N웰(11B)의 제 1 및 제 2 액티브 영역 상에 제 2 두께를 가지는 제 1 게이트(14A)와 제 1 두께를 가지는 제 2 게이트(14B)를 각각 형성한 후, 공지된 방법에 의해 제 2 포토레지스트 패턴(16)을 제거한다.As shown in FIG. 1E, the polysilicon film 14 is etched using the second photoresist pattern 16 to form the first and second active regions of the P well 11A and the N well 11B. After forming the first gate 14A having the second thickness and the second gate 14B having the first thickness, respectively, the second photoresist pattern 16 is removed by a known method.

도 1f에 도시된 바와 같이, 기판 전면 상에 절연막을 증착하고 블랭킷 (blanket) 식각하여 제 1 및 제 게이트(14A, 14B) 측벽에 스페이서(19)를 형성한다. 그 다음, 상기 N＋ 소오스/드레인 마스크를 재사용하여 포토리소그라피에 의해 P웰(11A)의 제 1 액티브 영역만을 오픈시키는 제 3 포토레지스트 패턴(미도시)을 형성하고, 오픈된 영역으로 N＋ 불순물이온을 이온주입하여 얕은 깊이의 N＋ 소오스/드레인 접합영역(17)을 형성함과 동시에 제 1 게이트(14A)를 도핑한 후, 공지된 방법에 의해 제 3 포토레지스트 패턴을 제거한다. 그 다음, P＋ 소오스/드레인 마스크(미도시)를 사용하여 포토리소그라피에 의해 N웰(11B)의 제 2 액티브 영역만을 오픈시키는 제 4 포토레지스트 패턴(미도시)을 형성하고, 오픈된 영역으로 보론 등의 P＋ 불순물이온을 이온주입하여 P＋ 소오스/드레인 접합영역(18)을 형성함과 동시에 제 2 게이트(14B)를 도핑한 후, 공지된 방법에 의해 제 4 포토레지스트 패턴을 제거한다.As shown in FIG. 1F, an insulating film is deposited on the entire surface of the substrate and blanket etched to form spacers 19 on the sidewalls of the first and first gates 14A and 14B. Then, the N + source / drain mask is reused to form a third photoresist pattern (not shown) that opens only the first active region of the P well 11A by photolithography, and the N + impurities into the opened region. Ions are implanted to form an N + source / drain junction region 17 having a shallow depth and doped with the first gate 14A, and then the third photoresist pattern is removed by a known method. Then, using a P + source / drain mask (not shown), a fourth photoresist pattern (not shown) for opening only the second active region of the N well 11B by photolithography is formed, and then into the open region. P + impurity ions such as boron are ion-implanted to form the P + source / drain junction region 18 and doped with the second gate 14B, and then the fourth photoresist pattern is removed by a known method. .

상기 실시예에 의하면, PMOS 트랜지스터의 게이트 두께는 감소시키지 않으면서 NMOS 트랜지스터의 게이트 두께를 낮춤에 따라, NMOS 및 PMOS 트랜지스터의 게이트 도핑 및 소오스/드레인 접합영역을 각각 1회의 이온주입만으로 수행하더라도 NMOS 트랜지스터에서는 얕은 접합을 구현하면서 게이트 도핑 효율을 향상시킬 수 있고, PMOS 트랜지스터에서는 보론 침투 등의 문제를 방지할 수 있게 된다. According to the above embodiment, as the gate thickness of the NMOS transistor is lowered without reducing the gate thickness of the PMOS transistor, the NMOS transistor is performed even if the gate doping and the source / drain junction regions of the NMOS and PMOS transistors are performed only once in each ion implantation. In addition, the gate doping efficiency can be improved while implementing a shallow junction, and problems such as boron penetration can be prevented in the PMOS transistor.

또한, 통상의 N＋ 소오스/드레인 마스크를 이용하여 NMOS 트랜지스터의 게이트 두께만을 감소시키기 때문에 별도의 마스크 제작이 요구되지 않으므로 제조비용이 증가되지는 않게 된다.In addition, since only the gate thickness of the NMOS transistor is reduced by using a conventional N + source / drain mask, a separate mask fabrication is not required, and thus a manufacturing cost does not increase.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 듀얼 게이트 적용시 NMOS 트랜지스터의 게이트 도핑 효율을 향상시키면서 얕은 접합을 용이하게 구현함과 동시에 PMOS 트랜지스터에서의 보론 침투를 효과적으로 방지할 수 있으므로 소자 특성을 향상시킬 수 있다.According to the present invention, a shallow junction can be easily implemented while improving the gate doping efficiency of the NMOS transistor when dual gate is applied, and boron penetration can be effectively prevented in the PMOS transistor, thereby improving device characteristics.

Claims (4)

제 1 도전형 제 1 웰 및 상기 제 1 도전형과 반대의 제 2 도전형 제 2 웰이 형성되고, 필드절연막에 의해 상기 제 1 웰에는 제 1 액티브 영역이 정의되고 상기 제 2 웰에는 제 2 액티브 영역이 정의된 반도체 기판을 준비하는 단계;A first conductivity type first well and a second conductivity type second well opposite to the first conductivity type are formed, a first active region is defined in the first well by a field insulating film, and a second in the second well. Preparing a semiconductor substrate in which an active region is defined; 상기 기판 상에 게이트 절연막과 제 1 두께의 폴리실리콘막을 순차적으로 형성하는 단계;Sequentially forming a gate insulating film and a polysilicon film of a first thickness on the substrate; 상기 제 1 액티브 영역만을 오픈시키기 위해 상기 제 1 두께의 폴리실리콘막 상부에 제 1 포토레지스트 패턴을 형성하는 단계;Forming a first photoresist pattern on the polysilicon film of the first thickness to open only the first active region; 상기 제 1 액티브 영역 상의 폴리실리콘막을 소정 두께만큼 제 1 식각하는 단계; 및First etching the polysilicon layer on the first active region by a predetermined thickness; And 상기 폴리실리콘막을 제 2 식각하여 상기 제 1 및 제 2 액티브 영역 상에 상기 제 1 두께보다 낮은 제 2 두께를 가지는 제 1 게이트와 상기 제 1 두께를 가지는 제 2 게이트를 각각 형성하는 단계를 포함하는 반도체 소자의 트랜지스터 제조방법.Etching the polysilicon layer to form a first gate having a second thickness lower than the first thickness and a second gate having the first thickness on the first and second active regions, respectively; Method for manufacturing a transistor of a semiconductor device. 제 1 항에 있어서, The method of claim 1, 상기 제 1 및 제 2 게이트 측벽에 스페이서를 형성하는 단계;Forming spacers on sidewalls of the first and second gates; 상기 제 1 액티브 영역으로 제 2 도전형 불순물이온을 주입하여 제 1 접합영역을 형성함과 동시에 상기 제 1 게이트를 도핑하는 단계; 및 Implanting a second conductivity type impurity ion into the first active region to form a first junction region and simultaneously doping the first gate; And 상기 제 2 액티브 영역으로 제 1 도전형 불순물이온을 주입하여 제 2 접합영 역을 형성함과 동시에 상기 제 2 게이트를 도핑하는 단계를 더 포함하는 반도체 소자의 트랜지스터 제조방법.Implanting a first conductivity type impurity ion into the second active region to form a second junction region and simultaneously doping the second gate. 제 2 항에 있어서, The method of claim 2, 상기 폴리실리콘막의 제 1 식각과 상기 제 1 접합영역 형성은 동일 마스크를 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.And forming the first junction region and the first junction region of the polysilicon layer using the same mask. 제 3 항에 있어서, The method of claim 3, wherein 상기 제 1 도전형은 P형이고, 상기 제 2 도전형은 N형인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.And wherein the first conductivity type is P type and the second conductivity type is N type.
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KR19980058454A (en) * 1996-12-30 1998-10-07 김영환 Manufacturing method of semiconductor device
KR20010108658A (en) * 2000-05-30 2001-12-08 윤종용 Memory merged logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and Method of manufacturing the same
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Publication number Priority date Publication date Assignee Title
KR19980058454A (en) * 1996-12-30 1998-10-07 김영환 Manufacturing method of semiconductor device
KR20010108658A (en) * 2000-05-30 2001-12-08 윤종용 Memory merged logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and Method of manufacturing the same
KR20030047555A (en) * 2001-12-11 2003-06-18 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device

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