KR101016991B1 - Active Matrix Electroluminescent Displays, and Fabrication thereof - Google Patents

Abstract

Physical barriers 210 exist between the adjacent pixels 200 on the circuit board 100 in the active-matrix electroluminescent display, particularly the LEDs 25 of organic semiconductor materials. The present invention provides these barriers 210 with a first circuit element 21, 4, 5, 6, 140, 150, 160, T1, T2, Tm, Tg, Ch and a second circuit element 400 of the circuit board. , 400s, 23, for example, metal or other electrically conductive material 240 that acts as an interconnect between the sensors 400s of the sensor array supported on the circuit array. The conductive barrier metal 240 is insulated from the sides of the barriers adjacent to the LEDs 40 and has a non-insulated top connection region 240t to which the second circuit element is connected to the conductive barrier material 240.

Organic semiconductor material, conductive barrier material, pixel region, bulk, core

Description

Active matrix electroluminescent display devices, and their manufacture

FIELD OF THE INVENTION The present invention relates to active matrix electroluminescent displays, and more particularly, to light emitting diodes of semiconducting conjugated polymers or other organic semiconductor materials. The invention also relates to methods of manufacturing such devices.

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The active-matrix electroluminescent displays are known, including an array of pixels on a circuit board, each pixel typically comprising an electroluminescent element of an organic semiconductor material. The electroluminescent elements are connected to a circuit in a substrate, for example a drive circuit comprising a supply line and a matrix addressing circuit comprising addressing (row) and signal (column) lines. These lines are generally formed by thin film conductor layers in the substrate.

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The circuit board also includes addressing and driving elements (usually thin film transistors, referred to herein as " TFTs ") for each pixel.

In many such arrays, in at least one direction of the array, there are physical barriers of insulating material between neighboring pixels. Examples of such barriers are published UK patent application GB-A-2 347 017, published PCT patent application WO-A1-99 / 43031, published European patent application EP-A-0 895 219, EP-A-1 096. 568, and EP-A-1 102 317, the entire contents of which are incorporated herein by reference.

Such barriers are also referred to as "walls", "partitions", "banks", "ribs", "separators", or "dams", for example. As can be seen from the cited references, they can provide some functionality. They can be used to define electroluminescent layers and / or electrode layers of individual pixels and / or pixel columns in manufacturing. Thus, for example, the barriers prevent pixel overflow of conjugated polymeric materials that can be ink-jet printed for red, green and blue pixels of colored markings or spin-coated for monochrome markings. . Barriers in the fabricated device can provide distinct optical separation of pixels. They may also include or include a conductive material (such as the upper electrode material of the electroluminescent element) as an auxiliary line for reducing the resistance (and therefore the voltage drops across it) of the common upper electrode of the electroluminescent elements.

It is an object of the present invention to improve the functions and / or performance of active-matrix electroluminescent display devices so as to be compatible with the basic device structure, its layout and its electronics.

According to one aspect of the present invention, an active-matrix electroluminescent display device having the features disclosed in claim 1 is provided.                 

According to the present invention, physical barriers between pixels are used to provide interconnections between the first circuit element of the circuit board and the second circuit element connected to the top of the barrier. Accordingly, these pixel barriers are composed of an electrically conductive material (usually a metal) that provides a partial (or even majority) interconnection, and at least the sides of the barriers adjacent to the electroluminescent elements are also insulated.

Many flexibility is possible according to the present invention. Depending on the circuit elements being interconnected, various layout features can be adopted for the pixel barriers. Accordingly, the conductive barrier material may provide interconnections, for example, localized to individual pixels or groups of pixels, or interconnects that may lie outside the pixel array. Thus, each non-insulated top connection region may itself be limited as part of a connection pattern along the top of the barriers, and / or the interconnectivity conductive barrier material is for example in individually insulated lengths of the barriers. It may be localized.

The first and second circuit elements can take various forms, depending on whether particular improvements or enhancements or adaptations are made. Usually, the first circuit element of the circuit board includes a conductor layer; Electrode connection; Supply line; Addressing lines; Signal line; Thin film transistors; It may be one or more thin film elements of the group comprising thin film capacitors. The second circuit element may be an electrode connection of another such thin film element in the circuit board and / or an electroluminescent element of an added component, for example, each pixel or sensor.

The last possibility makes it possible to integrate various forms of the sensor array with the pixel array. The sensor array can be integrated into the circuit board. However, the sensor array may be supported on top of the barriers and above the pixel array. This provides a compact layout and is particularly suitable for direct pen input and / or fingerprint sensing. The sensor array may share a matrix addressing circuit of the pixel array in the circuit board. This simplifies the integration of the sensor array and the pixel array. Sharing can be accomplished, for example, in a manner similar to that disclosed in US Pat. Nos. US-A-5,386,543 and US-A-5,838,308 (Philips references: PHB33816 and PHB33715). The entire contents of US-A-5,386,543 and US-A-5,838,308 are incorporated herein by reference.

In addition to using barriers to provide interconnections in accordance with the present invention, the barriers (or at least other individually insulated lengths of the barriers) may provide other functions. They can be used, for example, to form components such as capacitors or inductors or transformers, and / or to substitute or replace thin film conductor lines of a circuit board. These alternative or replacement lines can be, for example, an address line, a signal line or a supply line.

According to another aspect of the present invention, there are also provided methods which are advantageous for manufacturing such an active-matrix electroluminescent display.

Various advantageous features and combinations of features according to the invention are disclosed in the appended claims.

These and others are shown in the embodiments of the invention described by way of example with reference to the accompanying schematic drawings.

These and others are represented within the embodiments of the invention now described with reference to, for example, the accompanying schematic drawings.
1 is a circuit diagram of four pixel regions of an active-matrix electroluminescent display in which interconnects may be provided, in accordance with the present invention;

FIG. 2 is a cross sectional view of a portion of a pixel array and circuit board of one embodiment of such a device, showing an example of a conductive barrier structure for forming interconnects to a TFT source or drain line, in accordance with the present invention; FIG.

3 is a cross-sectional view of a portion of a pixel array and a circuit board of a similar embodiment of such a device, showing another example of a conductive barrier structure for forming interconnects to a TFT gate line, in accordance with the present invention;

4 is a cross-sectional view of an interconnection of an embodiment such as that of FIG. 2 or 3, illustrating an example of a modified conductive barrier structure using a metal coating to form interconnects, in accordance with the present invention.

FIG. 5 is a cross-sectional view of a portion of a device such as that of FIG. 2 or FIG. 3, showing the interconnections according to the invention for a pressure sensor integrated with an electroluminescent device. FIG.

FIG. 6 is a cross-sectional view of a portion of a device such as that of FIG. 2 or FIG. 3, showing the interconnections according to the invention for a capacitive sensor integrated with an electroluminescent device. FIG.

FIG. 7 is a cross-sectional view of a portion of a device such as that of FIG. 2 or FIG. 3, showing the interconnections according to the invention for a direct input sensor integrated with an electroluminescent device. FIG.

FIG. 8 is a cross-sectional view of a portion of a device such as that of FIG. 2 or FIG. 3, showing the interconnections according to the invention between the upper and lower electrodes of adjacent pixels or sub-pixels. FIG.

9 is a plan view of four pixel regions showing a specific example of layout features of a particular embodiment of the device according to the present invention with side by side conductive barriers.

FIG. 10 is a cross-sectional view of the sidewalls of FIG. 9 taken in X-X ray. FIG.

11 is a plan view of another example of layout features of a particular embodiment of the device according to the present invention, through which conductive barriers are traversed.

12 is a cross-sectional view of another example device portion of a conductive barrier structure for forming interconnects in accordance with the present invention.

13-16 are cross-sectional views of portions of an apparatus such as that of FIG. 2 or 3 at stages of manufacture by a particular embodiment according to the present invention.

FIG. 17 is a cross-sectional view of the device portion in an isolation step, showing a change in the insulation of conductive barrier interconnects in accordance with the present invention. FIG.

It should be noted that all drawings are schematic. The relative sizes and proportions of parts of these figures are shown in the figures exaggerated or reduced in size for clarity and convenience. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments.

1 to 4 Examples

The active-matrix electroluminescent display of each of the embodiments of FIGS. 1 to 4 includes a pixel array 200 on a circuit board 100 having a matrix addressing circuit. Physical barriers 210 are between at least some neighboring pixels in at least one direction of the array. At least some of these barriers 210 are comprised of a conductive barrier material 240 used as an interconnect in accordance with the present invention. Departing from the use of these particular structures and barriers 210 in accordance with the present invention, the indication may be constructed using known device techniques and circuit techniques, for example, as in the references of the background art mentioned above.

The matrix addressing circuit includes a plurality of sets of addressing (row) and signal (column) lines 150, 160 in the transverse direction, as shown in FIG. 1. The addressing element T2 (commonly referred to as thin film transistor, hereinafter referred to as "TFT") is disposed at each intersection of these lines 150 and 160. 1 shows one specific pixel circuit configuration as an example. Other pixel circuit configurations other than for active matrix electroluminescent displays are known. It will be readily appreciated that the present invention can be applied to the pixel barriers of such a device regardless of the particular pixel circuit configuration of the device.

Each pixel 200 includes current driven electroluminescent elements 25 (21, 22 and 23), which are typically light emitting diodes (LEDs) of organic semiconductor material. The LED 25 is connected in series with the drive element T1 (typically TFT) between two voltage supply lines 140 and 230 of the array. These two supply lines are typically power supply line 140 (with voltage Vdd) and ground line 230 (also referred to as a "return line"). The light emission from the LED 25 is controlled by the current flow through the LED 25, which is changed by each driving TFT T1.

Each row of pixels is addressed in turn in the frame period by a selection signal applied to the associated row conductor 150 (and thus to the gate of the addressing TFTs T2 of the pixels in this row). This signal turns on the addressing TFT T2, so that respective data signals from the column conductors 160 are loaded into the pixels in this row. These data signals are applied to the gates of the individual driving TFTs T1 of each pixel. In order to maintain the resulting conductive state of the driving TFT T1, this data signal is held on the gate 5 by a holding capacitor Ch coupled between the gate 5 and the driving lines 140,240. Is kept on. Therefore, the driving current flowing through the LED 25 of each pixel 200 is controlled by the driving TFT T1 based on the driving signal applied in the preceding address period and stored as a voltage in the associated capacitor Ch. In the specific example of FIG. 1, T1 is shown as a P-channel TFT and T2 is shown as an N-channel TFT.

This circuit can be constructed by known thin film techniques. The substrate 100 may have an insulating glass base 10 on which an insulating surface-buffer layer 11 of silicon oxide is deposited, for example. The thin film circuit is formed on the layer 11 in a known manner.

2 and 3 show Tm and Tg as examples of TFTs, each of which comprises an active semiconductor layer 1 (usually polysilicon); Gate dielectric layer 2 (usually silicon dioxide); Gate electrode 5 (usually aluminum or polysilicon); And metal electrodes 3, 4 in contact with the doped source and drain regions of the semiconductor layer 1 through windows (vias) in the insulating layer (s) 2, 8 overlying it. (Usually aluminum). Extensions of the electrodes 3, 4 and 5 may be chosen depending on the circuit function provided by a particular TFT (e.g., drive element T1 or addressing element T2 or another TFT on a circuit board). For example, interconnections may be formed between at least some of the elements T1, T2, Ch, and LED 25, and / or conductor lines 140, 150, and 160. The holding capacitor Ch may be similarly formed as a thin film structure in the circuit board 100 in a known manner.

The LED 25 typically includes a light emitting organic semiconductor material 22 between the lower electrode 21 and the upper electrode 23. In certain preferred embodiments, semiconductor conjugated polymers may be used for the electroluminescent material 22. In an LED that emits light 250 through the substrate 100, the lower electrode 21 may be an anode of indium tin oxide (ITO), and the upper electrode 23 may comprise, for example, calcium and aluminum. It may be a cathode. 2 and 3 show the LED structure in which the lower electrode 21 is formed as a thin film in the circuit board 100. The deposited organic semiconductor material 22 then contacts this thin film electrode layer 21 in a window 12a in a flat insulating layer 12 (eg, silicon nitride) that extends over the thin film structure of the substrate 100.

As in known devices, the devices of FIGS. 1-4 in accordance with the present invention include physical barriers 210 between at least some of the neighboring pixels in at least one direction of the array. These barriers 210 may also be referred to as "walls", "bulges", "banks", "ribs", "separators", or "dams", for example. According to certain device embodiments and their preparation, they are for example known in the art,

During the provision of the semiconductor polymer layers 22, isolation between the individual pixels 200 and / or regions of each of the columns of pixels 200 to prevent overflow of the polymer solution;

Self-patterning ability (as well as pixels) on the substrate surface in the definition of a semiconducting polymer or other electroluminescent layers 22 for the individual pixels 200 and / or columns of pixels 200. Individual electrodes of the pores, for example self-separation of individual bottom layers of the upper electrodes 23);

Acts as a spacer for the mask on the substrate surface during deposition of at least the organic semiconductor material 22 and / or the electrode material;

When light 250 is emitted through (or instead of, or in addition to, the lower substrate 100), it can be used to form opaque barriers 210 for clear optical separation of pixels 200 in the array. Can be.

Whatever their particular use in these known methods, at least some insulated portions of the physical barriers 210 in embodiments of the present invention are configured and used in a particular manner. Accordingly, the pixel barriers 210 of FIGS. 2-4 are insulated from the LEDs 25 and provide a metal 240 that provides an interconnection between the first circuit element of the circuit board 100 and the second circuit element of the device. (Or other electrically conductive material 240). These circuit elements are connected to the non-insulated lower and upper contact regions 240b and 240t of the conductive barrier material 240.

The first and second circuit elements can take various forms depending on the particular improvement or enhancement or adaptation made. Usually, the first circuit element of the circuit board 100 may include a conductor layer and / or electrode connections 4, 5 and 6; Supply line 140; Addressing line 150; Signal line 160; Thin film transistors T1, T2, Tm and Tg; One or more thin film elements in the group including the thin film capacitor Ch may be used. The second circuit element may be another such thin film element in the circuit board 100 and / or an electrode connection of an LED 25 of an added component, such as, for example, each pixel or sensor.

2 to 4 show a non-insulated upper connection region 240t, in which no particular second circuit element (upper circuit element 400) is connected. Specific examples of the second circuit element are described below with reference to FIGS. 5 to 8. However, it will be readily appreciated that the present invention may be applied to the interconnection of various upper circuit elements 400 in circuitry in circuit board 100 by such pixel barriers 210 in accordance with the present invention.

In the embodiment of Fig. 2, the first circuit element is an extension of the source and / or drain electrode of the TFT Tm. This may for example form a signal (column) line 160 of the substrate circuit when Tm is T2, or drive line 140 when Tm is T1. In the embodiment of Fig. 3, the first circuit element is an extension of the gate electrode 5 of the TFT (Tg). This may form, for example, the addressing (row) line 150 of the substrate circuit when Tg is T2.

2 and 3 show the bottom connection of the conductive barrier material 240 to the first circuit elements 4, 5 in the connection windows 12b in the intermediate insulating layer 12. However, note that these windows 12b may not be often coplanar with the TFTs (Tm, Tg). In particular, the spacing between the source electrode 3 and the drain electrode 4 of the TFT (Tg) is generally insufficient to accommodate the window 12b. Accordingly, the window 12b is shown in phantom in FIG. 3 to indicate that it lies outside the plane of the drawing.

In the embodiments of FIGS. 2-4 the pixel barriers 210 are mainly made of an electrically conductive material 240, 240x, preferably with a very low resistivity metal (eg aluminum or copper or nickel or Is made of) The barriers 210 of FIGS. 2 and 3 provide the interconnect 240 and have a conductive material on the sides and on top (except where the top connection area 240t is exposed) with an insulating coating 40. Bulk or core. Barrier 210 of FIG. 4 includes a bulk or core of conductive material 240x with an insulating coating 40x on its sides and top. The conductive material providing interconnect 240 in FIG. 4 is a metal coating extending over insulating coating 40x. The insulating coating 40 extends over the sides and top of the metal coating 240, except where the top connection area 240t is exposed. This structure of FIG. 4 is more versatile than FIGS. 2 and 3. This allows the metal core 240x to be used for another purpose, for example to replace or replace the lines 140, 150, or 160 so that their line resistance can be reduced. The interconnect metal coating 240 may be localized at specific locations along the barrier 210 where such interconnect is needed, for example in individual pixels or sub-pixels.

sensor Arrays  5 to 7 with Examples

In each of the embodiments of FIGS. 5-7, the sensor 400s array is integrated with the pixel array 200. Sensors 400s provide second circuit elements 400 that are connected to the first circuit element of circuit board 100 by conductive barrier material 240. Various sensor arrays may be integrated with the display in accordance with the present invention. Thus, the sensing array may have a short-circuit touch input, or a pressure input, or a capacitive input, or a light-pen input, for example.

In the individual interconnections from the two-dimensional sensor array, the conductive barrier material 240 is generally divided into respective insulated lengths in the barriers 210 corresponding to the individual sensors 400s.

In this integrated sensor state, the first circuit element may be, for example, the source / drain 4 or the gate 5 of the TFT in the substrate 100. Preferably, the first circuit element is part of a matrix addressing circuit for both the array of pixels 200 and the array 200s of sensors. Thus, the first circuit element may be the source / drain lines 4 and 160 of the TFT T2 for pixel addressing.

In each of the embodiments of FIGS. 5-7, a sensing function is provided on the front side of the display from which light 250 is emitted. The sensor array is supported on top of the barriers 210 and on the pixel array. An insulating planarization layer 412 is on the pixel array, with a thickness that extends over the barriers 210 to support the sensor array on the pixel array. While FIGS. 5-8 illustrate an interconnect metal-core structure as in FIGS. 2 and 3, variations are possible using, for example, an interconnect metal-coated structure as in FIG. 4.

5 illustrates a pressure sensor structure that includes a compressible layer 422 of a dielectric or high resistive material. The compressible layer is deposited between the transparent upper electrode layer 423, for example ITO, and the underlying conductive barrier material 240 and the insulating planarization layer 412. The upper electrode layer 423 is covered with the protective layer 440. When a pressure 500 is applied to this stack, the gap between the electrode layer 423 and the conductive barrier material changes to cause a measurable capacity change in the dielectric or a decrease in resistance in the high resistance material. This is the most advantageous embodiment in that the electrode layer 423 also provides ESD protection for circuit inputs.

6 shows a capacitive sensor, for example a fingerprint sensor. An array of electrode pads 421 of ITO or metal is connected on top of a corresponding array of conductive barrier material 240 to form one plate of each capacitor with a capacitor dielectric layer 430. The other plate of the capacitor is formed by a finger or other object that will be detected when placed over the dielectric layer 430.

7 illustrates a direct input sensor with electrode pads 424 of ITO connected on top of a corresponding array of conductive barrier material 240. The direct input may be a current or voltage input from the wired pen touching the pads 424. Alternatively, direct input may simply be performed between neighboring pads 424, for example, between pad 424 connected to row conductor 150 and pad 424 connected to column conductor 160 (in line). It may be a short-circuit by means of a conductive pen (not connected). The current flow due to this short-circuit can be measured around the display to determine which pixel is shorted.

serve- Pixel  8 with interconnects Example

In the embodiment of FIG. 8, the second circuit element is the upper electrode 23 of the LED 25, connected by the conductive barrier material 240 to the thin film element of the circuit board 100. This interconnection allows the circuit to be integrated with both electrodes 21, 23 of a given LED 25.

However, in the particular embodiment shown in FIG. 8, the bottom connection of conductive barrier material 240 is a connection to a thin film element that forms an electrode underneath a neighboring LED 25. This configuration can be adopted for display in which each pixel includes side by side sub-pixels via barriers 210, for example. In this case, the conductive barrier material 240 connects the upper electrode 23 of one sub-pixel 200b to the lower electrode 21 of the adjacent sub-pixel 200a.

9 and 10 and the layout of FIG. Examples

The invention allows a wide variety of layout configurations for the interconnect barrier material 240 in the devices. Advantageously, interconnect barrier material 240 may be combined with other portions of the barrier 210x between pixels in the composite layer.

9 and 10 illustrate one composite layout in which the conductive barrier material 240x of the added barrier portions 210x may substitute or replace the drive supply lines 140 of the substrate 100. . The matrix thin film circuit region is shown as 120 in FIG. 9. In this particular example, the insulated lengths of interconnect barrier material 240 extend parallel to the added barrier lines 210x and 140.

FIG. 11 shows another composite layout with added barrier portions 210x (240x, 40x) traversing interconnect barrier material 240. In this case, the conductive barrier material 240x of the additional barrier portions 210x may substitute or replace the lines 140 or 150 or 160 of the substrate 100. Alternatively, conductive barrier material 240x of additional barrier portions 210x may form cross interconnections to the direct input sensor array as shown in FIG. 7.

Modified Barrier of Figure 12 Example

In the embodiments of FIGS. 2-8 and 10, the barriers 210, 210x are shown as being primarily of conductive material 240, 240x. 12 illustrates a modified embodiment in which the barrier 210 is primarily of insulating material 244. In this case, vias 244b are etched or milled through insulating material 244 to circuit elements 4 and 5 in circuit board 100. The metal coating 240 provides a conductive barrier material that extends over and into the vias 244b on top of the insulating barrier 210.

The metal coating 240 of the barrier 210 may be formed simultaneously with the main portion 23a of the upper electrode 23 of the LED 25 in a self-aligning manner. Accordingly, as shown in FIG. 12, the metal coating 240 and the metal layer for the electrode 23 isolated by the shadow-masking effect of the protruding shape in the side surface of the barrier 210 may be deposited simultaneously. . This is one possible process embodiment for forming barrier interconnects 210 and 240 according to the present invention. 14-17 illustrate other process embodiments for barrier interconnects 210, 240, predominantly of metal.

13-16 process Example

Aside from constructing and using barriers 210 with interconnect material 240, the active-matrix electroluminescent display of the device according to the invention is known device, for example as in the references cited in the background. It may be constructed using techniques and circuit techniques.

13-16 illustrate novel process steps in certain manufacturing embodiments. The thin film circuit board 100 having the upper flat insulating layer 12 (for example, silicon nitride) is manufactured in a known manner. The connection windows (such as vias 12a, 12b, 12x, etc.) are opened in layer 12 by known methods, for example photolithographic masking and etching, but manufacturing the device according to the invention. To do this, the pattern of these vias includes vias 12b, 12x exposing elements 4, 5, 150, etc. for bottom connection with conductive barrier material 240, 240x. This step is common, regardless of whether the barriers 210 are primarily of conductive material, as in FIGS. 2-8 and 10, or of primarily insulating material, as in FIG. 12.

The formation of barriers 210, mainly of insulating material, has been described above with reference to FIG. Suitable process steps for the barriers 210 of predominantly conductive material (as in FIGS. 2-8 and 10) will now be described with reference to FIGS. 14-16.

In this case, an electrically conductive material for the barriers 210 is deposited on the insulating layer 12 in at least the vias 12a, 12b, 12x, and the like. Desired lengths and layout pattern for the barriers 210 are obtained using known masking techniques. FIG. 14 illustrates an embodiment in which a bulk 240 (eg, copper or nickel or silver) of conductive barrier material is deposited by plating. In this case, for example, a thin seed layer 240a of copper or nickel or silver is first deposited on the insulating layer 12 and its vias 12a, 12b, 12x, etc., and the barrier layout pattern is photoetched. Defined using a mask, the bulk 240 of conductive barrier material is then plated to the desired thickness. The resulting structure is shown in FIG.

Subsequently, an insulating material (eg, silicon dioxide or silicon nitride) is deposited for the insulating coating 40 using CVD (chemical vapor deposition). The deposited material is left on the sides and top of the conductive barrier material by patterning using known photolithographic masking and etching techniques. Subsequently, manufacturing continues in a known manner to form the LEDs 25. Accordingly, for example, the conjugated polymer materials 22 may be ink-jet printed or spin-coated with respect to the pixels 200. In order to prevent polymer overflow from the pixel regions between the physical barriers 240, 40, barriers 240, 40 with an insulating coating 40 can be used. Upper electrode material 23 is deposited on layer 22. The resulting structure is shown in FIG.

Subsequently, for the sensors of FIGS. 5-7, a layer of planarization material 412 ′ is placed on the LEDs 25. This layer 412 ′ may be etched back to expose the insulating coating 40 on top of the barriers 210. The top of this exposed insulating coating 40 may be etched to form a non-insulated top connection region 240t of the barrier 210 as shown in FIG. 16. A sensor structure is then provided on top of this connection area 240t and planarization layer 412.

Modified Process of Figure 17 Example

This embodiment uses anodization (instead of deposition) to provide an insulating coating 40 on at least sides of the barriers 210 adjacent the pixel regions. Typically, conductive barrier material 240 may comprise aluminum. Desired lengths and layout patterns of the deposited aluminum can be defined using known photolithographic masking and etching techniques. 17 shows an etchant-mask 44 defined by photolithography retained on top of the aluminum barrier pattern 240.

An anodically insulating coating of aluminum oxide is then formed on at least sides of the aluminum barrier material 240 using known anodization techniques. Thus, no separate mask is needed for the layout definition for this coating 40.

As shown in FIG. 17, the mask 44 may be preserved during this anodization in areas where it is desired to protect and form the non-insulated top connection area 240t. In these areas, an anode coating is formed only on the sides of the aluminum barrier pattern 240. The mask 44 may be removed in areas where anode coating is needed on both the sides and top of the aluminum barrier pattern 240 prior to such anodization. Alternatively, a mask 44 made of insulating polymer, or silicon dioxide or silicon nitride, for example, may be preserved in these areas where insulation is required on top of barriers 210 (240, 40) in the fabricated device. It can also be.

In the embodiments described so far, the conductive barrier material 240 is a thick opaque metal, such as aluminum, copper, nickel or silver. However, other conductive materials 240 may also be used, for example metal silicide or (but less effective) degenerately-doped polysilicon whose surface may be oxidized to form an insulating coating 40. have. If transparent barriers 210 are desired, ITO may be used for the conductive barrier material 240. Furthermore, note that the line resistance can be significantly reduced by using conductive barrier materials 240, 240x to replace or substitute for conductor lines (eg, 140, 150, or 160) of the circuit board 10. do. Thus, along a given line, the conductive barrier material 240 may be a typical conductor layer (e.g., source / drain lines 4, 6) 140, 160 of the TFT (Tm) or It may have a cross-sectional area that is at least twice as large (or in size) than the gate lines 5 and 150 of the TFT (Tg). Typically, conductive barrier material 240 may have a thickness Z that is two times or more (eg, at least five times) greater than the thickness z of this TFT conductor layer in circuit board 100. In specific examples Z may be between 2 μm and 5 μm relative to z of 0.5 μm or less. Typically, conductive barrier material 240 may have a line width Y that is the same width (or at least twice as large) as the line width y of the TFT conductor layer. As a specific example, Y may be 20 μm compared with 10 μm of y.

Having read this disclosure, other variations and modifications will become apparent to those skilled in the art. Such variations and modifications may involve equivalents and other features that are already known in the art (eg, in references cited in the background) and that may be used in place of or in addition to the features described herein.

Although the claims are formulated herein with specific combinations of features, the disclosure scope of the present invention is directed to how any new feature or any new combination of features disclosed explicitly or implicitly is the same as currently claimed in any claim. It will be appreciated that this includes any or all of the same technical problems as the present invention.

The Applicant notes that new claims may be formulated with any such features and / or combinations of such features in the course of this application or any other application thereof.

Claims (19)

In an active-matrix electroluminescent display device: A circuit board with said pixel array having physical barriers between at least some of the neighboring pixels in at least one direction of a pixel array; Each pixel comprises an electroluminescent element; The circuit board comprises a circuit to which the electroluminescent elements are connected; The physical barriers comprise a conductive material that acts as an interconnect between a first circuit element and a second circuit element of the circuit board of the device; A conductive barrier material is insulated on at least sides of the barriers adjacent the electroluminescent elements, the first and second circuit elements having non-insulated top and bottom connection regions connected to the conductive barrier material, Active-matrix electroluminescent display. The method of claim 1, And the first circuit element of the circuit board is at least one thin film element of a group including a conductor layer, an electrode connection, a supply line, an addressing line, a signal line, a thin film transistor, and a thin film capacitor. . The method of claim 1, And the second circuit element is an upper electrode of the electroluminescent element, and the first circuit element is at least one thin film element of the circuit board. The method of claim 3, Each pixel comprises side-by-side sub-pixels interposed between the barriers and the conductive barrier material connects an upper electrode of one sub-pixel to a lower electrode of an adjacent sub-pixel, wherein the lower and upper electrodes are arranged in the first electrode. And second circuit elements. The method according to claim 1 or 2, A sensor array is integrated with the pixel array, the sensors providing the second circuit elements connected to the first circuit element of the circuit board by the conductive barrier material. The method according to any one of claims 1 to 4, A sensor array is integrated with the pixel array, the circuit board includes matrix addressing circuitry for both the pixel array and the sensor array, and the conductive barrier material connects the array sensors to the matrix addressing circuitry. Matrix electroluminescent display. The method of claim 5, And the sensor array is supported on top of the barriers and on the pixel array. The method of claim 7, wherein And a planarization layer is on the pixel array with a thickness that extends above the barriers to support the sensor array on the pixel array. The method according to any one of claims 1 to 4, And insulated lengths of the barriers are the conductive barrier materials. The method according to any one of claims 1 to 4, And said barrier comprises a metal core connected to said first circuit element and providing said conductive barrier material with an insulating coating on at least sides thereof. The method according to any one of claims 1 to 4, And said barrier comprises a metal coating connected to said first circuit element and providing said conductive barrier material with an insulating coating on at least sides thereof. The method according to any one of claims 1 to 4, The physical barrier is an insulating material through which vias extend for connection with the circuit element in the circuit board, and the metallic coating providing the conductive barrier material is formed on top of the physical barrier and through the physical barrier. An active-matrix electroluminescent display that extends into vias. The method according to any one of claims 1 to 4, And the electroluminescent element is a current-driven light emitting diode of an organic semiconductor material. The method according to any one of claims 1 to 4, Under the conductive barrier material, there are connection windows in an intermediate insulating layer on the circuit board to permit connection with the first circuit element. The method of manufacturing an active-matrix electroluminescent display device according to any one of claims 1 to 4, (a) forming an electrically conductive material deposited on electrode connections to a first circuit element of a circuit board, and physical barriers having insulation on at least sides of physical barriers adjacent to pixel regions, wherein the physical barrier Forming the physical barriers on top of the barriers, the non-insulating top connection region for the conductive barrier material; (b) providing at least some of said electroluminescent elements in said pixel regions between said physical barriers; And (c) providing the second circuit element connected with the conductive barrier material to the non-isolated top connection region of the barriers. The method of claim 15, And the insulation comprises an insulating coating deposited on at least sides and top of the conductive barrier material and subsequently etched from the top connection region. The method of claim 15, The conductive barrier material comprises aluminum and the insulation comprises an insulating coating formed on the sides of the aluminum barrier material by anodization while masking the upper connection area for anodization. Method of manufacturing a light emitting display device. 16. The method of claim 15, wherein step (a) comprises forming the physical barrier of insulating material through which vias are formed for connection with the circuit element in the connection windows on the circuit board, An electrically conductive material is deposited as a conductive coating on top of the physical barrier and in the vias penetrating the physical barrier. The method of claim 18, An active-matrix electroluminescence of the upper electrode of the electroluminescent element and the conductive coating for the physical barrier are deposited simultaneously and separated by a shadow-masking effect of a shape projecting within the side of the physical barrier Display device manufacturing method.

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