KR101036716B1 - CMOS thin film transistor and its manufacturing method - Google Patents

Abstract

A CMOS thin film transistor of the present invention and a method for manufacturing the same, comprising: a substrate in which an NMOS region and a PMOS region are defined, an active layer formed in the NMOS and PMOS regions, a gate electrode formed on the active layer, and the active layer in the NMOS region An interlayer insulating film formed on an entire surface of the substrate, the first source and drain regions formed on both sides, second source and drain regions formed on both sides of the active layer of the PMOS region, and gate electrodes formed on the NMOS and PMOS regions; A first contact hole exposing the first source region of the region and a second source region of the PMOS region, a second contact hole exposing the first drain region of the NMOS region and the second drain region of the PMOS region simultaneously; One source hole of the NMOS and PMOS connected to the first source region of the NMOS region and the second source region of the PMOS region through a contact hole and the second contact hole, respectively. And a drain electrode of the NMOS and the PMOS which simultaneously connect the first drain region of the NMOS region and the second drain region of the PMOS region, wherein the first drain region of the NMOS region and the second drain region of the PMOS region are separated from each other. Their boundaries contact each other without areas.

Description

CMOS thin film transistor and its manufacturing method {COMPLEMENTARY THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THEREOF}

1 is a plan view showing a general layout of a conventional inverter device.

2 is a plan view showing a general layout of a conventional transfer gate device.

3 is a plan view showing a general layout of the inverter device according to the present invention.

4 is a graph showing the area occupied by a conventional inverter device and the inverter device of the present invention on a substrate as the number of inverter devices increases.

5 is a plan view showing a general layout of a transfer gate device according to the present invention.

6 is a graph showing the area occupied by a conventional transfer gate element and a transfer gate element of the present invention on a substrate as the number of transfer gate elements increases.

FIG. 7 is a cross-sectional structure of a CMOS thin film transistor showing a cross section taken along line II ′ of FIG. 5.

DESCRIPTION OF REFERENCE NUMERALS

121n, 121p, 131n, 131p, 231n, 231p: gate electrode

122n, 122p, 132n, 132p, 232n, 232p: Source area

123n, 123p, 133n, 133p, 233n, 233p: drain area

124n, 124p, 134n, 134p, 234n, 234p: source electrode                 

125n, 125p, 135n, 135p, 235n, 235p: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS thin film transistor and a method of manufacturing the same. In particular, an area occupied by a CMOS thin film transistor by connecting a n + region of an NMOS and a p + region of a PMOS through a contact hole in a CMOS thin film transistor constituting a driving circuit. The present invention relates to a CMOS thin film transistor and a method of manufacturing the same.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

In this case, a thin film transistor (TFT) is generally used as a switching element of the liquid crystal display, and amorphous silicon or polycrystalline silicon is used as a channel layer of the thin film transistor. .

In particular, a liquid crystal display device using a polysilicon thin film transistor has a structure in which a driving circuit portion and a pixel portion are incorporated in a glass substrate, and the driving circuit integrated liquid crystal display device is formed for each pixel to drive the pixel. The thin film transistor for driving and the pixel driving thin film transistor for driving the pixel driver may be divided into a thin film transistor for a driving circuit for applying a signal to a gate line and a data line, which will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically illustrating a structure of a general liquid crystal display device, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the drawing, the driving circuit-integrated liquid crystal display device 5 is largely a liquid crystal layer formed between the array substrate 10 and the color filter substrate 20, and the array substrate 10 and the color filter substrate 20. Not shown).

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix form, a gate driving circuit portion 34 and a data driving circuit portion 33 positioned outside the pixel portion 35. It consists of a driving circuit part.

In this case, although not shown in the drawings, the pixel units 35 of the array substrate 10 are arranged horizontally and horizontally on the substrate 10 to define a plurality of gate lines and data lines, and the gate lines and data. A thin film transistor, which is a switching element formed in an intersection region of a line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

In the driving circuit units 33 and 34 of the array substrate 10, the data driving circuit unit 33 is positioned at one long side of the array substrate 10 protruding from the color filter substrate 20. The gate driving circuit unit 34 is positioned at one end side of the array substrate 10.

In this case, the gate driving circuit 34 and the data driving circuit 33 use a thin film transistor having a CMOS structure to properly output the input signal.

The CMOS thin film transistor can be used as an inverter or a transfer gate. For reference, the CMOS is a type of integrated circuit having a MOS structure which is used for a thin film transistor of a driving circuit unit requiring high speed signal processing. And N-channel transistors are required, and the speed and density characteristics represent an intermediate form of NMOS and PMOS.

1 shows a layout of a CMOS used as an inverter, and FIG. 2 shows a layout of a CMOS used as a transfer gate.

First, as shown in FIG. 1, when CMOS is used as an inverter, gate electrodes 21n and 21p of NMOS and PMOS are connected to an input line Vin connected to an external input terminal (not shown). The drain electrode 25n and the drain electrode 25p of the PMOS are commonly connected to an output line Vout connected to an external output terminal (not shown). At this time, the drain electrode 25n of the NMOS is connected to the drain region 23n through the first drain contact hole 29n, and the drain electrode 25p of the PMOS is connected through the second drain contact hole 29p. It is connected to the drain region 23p.

The source electrode 24n of the NMOS is connected to the ground line GND, and the source electrode 24p of the PMOS is connected to the power line Vdd. At this time, the source electrode 24n of the NMOS is connected to the source region 22n through the first source contact hole 28n, and the source electrode 24p of the PMOS is connected through the second source contact hole 28p. It is connected to the source region 22p.

On the other hand, when the CMOS thin film transistor is used as a transfer gate, the gate electrodes 31n and 31p of the NMOS and PMOS are separately connected to respective power sources having complementary gate voltages, and the source electrode 34n of the NMOS The source electrode 34p of the PMOS is connected to the input line Vin. In this case, the source electrode 34n of the NMOS is connected to the lower source region 32n through the first source contact hole 38n, and the source electrode 34p of the PMOS is connected to the second source contact hole 38p. It is connected to the lower source region 32p through the above.

The NMOS drain electrode 35n and the PMOS drain electrode 35p are commonly connected to the output line Vout, and the NMOS drain electrode 35n is connected to the drain region through the first drain contact hole 39n. The drain electrode 35p of the PMOS is connected to the drain region 33p through the second drain contact hole 39p.

However, in the conventional CMOS device (Figs. 1 and 2) configured as described above, the drain electrodes 25n and 35n of the NMOS and the drain electrodes 25p and 35p of the PMOS are separately formed and commonly connected to the output line Vout. Therefore, in order to connect the drain electrodes 25n, 35n / 25p, 35p of the NMOS / PMOS with the drain regions 23p, 33p formed thereunder, the first drain contact holes 29n, 39n and the second drain contact. Holes 29p and 39p should be formed respectively. Therefore, as the first and second drain contact holes 29n, 39n / 29p, and 39p are formed independently, the area occupied by the CMOS device becomes large.

Accordingly, the present invention has been made to solve the above problems, and to provide a CMOS thin film transistor and a method of manufacturing the same that can minimize the area occupied by the CMOS device in the driving circuit.

Other objects and features of the present invention will be described in detail in the configuration and claims of the invention to be described later.

The CMOS thin film transistor of the present invention for achieving the above object is a substrate in which an NMOS region and a PMOS region are defined, an active layer formed in the NMOS and PMOS region, a gate electrode formed on the active layer, the active layer of the NMOS region An interlayer insulating film formed on an entire surface of the substrate, the first source and drain regions formed on both sides, second source and drain regions formed on both sides of the active layer of the PMOS region, and gate electrodes formed on the NMOS and PMOS regions; A first contact hole exposing the first source region of the region and a second source region of the PMOS region, a second contact hole exposing the first drain region of the NMOS region and the second drain region of the PMOS region simultaneously; One source hole of the NMOS and PMOS connected to the first source region of the NMOS region and the second source region of the PMOS region through a contact hole and the second contact hole, respectively. And a drain electrode of the NMOS and the PMOS for simultaneously connecting the first drain region of the NMOS region and the second drain region of the PMOS region, wherein the first drain region of the NMOS region and the second drain region of the PMOS region are separated from each other. Their boundaries contact each other without areas.
Gate electrodes of the NMOS and PMOS regions are connected to an external input terminal, source electrodes of the NMOS and PMOS regions are connected to a power line, drain electrodes of the NMOS and PMOS regions are connected to an external output terminal, and the active layer And a gate insulating film interposed between the gate electrode and the gate electrode.
The gate electrodes of the NMOS and PMOS regions are separately connected to respective power sources having complementary gator voltages.
A first contact hole exposing the first drain region of the NMOS region and the second drain region of the PMOS region, a second contact hole exposing the first source region of the NMOS region and the second source region of the PMOS region simultaneously; A drain electrode of an NMOS and a PMOS connected to the first drain region of the NMOS region and a second drain region of the PMOS region through the first contact hole, and a first source region of the NMOS region through the second contact hole; An NMOS and a PMOS source electrode for simultaneously connecting a second source region of the PMOS region, wherein the first source region of the NMOS region and the second source region of the PMOS region are in contact with each other without a separation region.
In addition, the method of manufacturing a CMOS thin film transistor of the present invention comprises the steps of preparing a substrate defined NMOS region and PMOS region, forming an active layer in the NMOS and PMOS region, forming a gate electrode on the active layer Forming first source and drain regions on both sides of the active layer of the NMOS region, forming second source and drain regions on both sides of the active layer of the PMOS region, and gates formed on the NMOS and PMOS regions Forming an interlayer insulating film over the substrate including an electrode, forming a first contact hole exposing a first source region of the NMOS region and a second source region of the PMOS region, respectively, and first forming the NMOS region Forming a second contact hole for simultaneously exposing a drain region and a second drain region of the PMOS region, and through the first contact hole, a first source region and a PM of the NMOS region Forming a source electrode of an NMOS and a PMOS respectively connected to a second source region of an OS region and an NMOS simultaneously connecting a first drain region of the NMOS region and a second drain region of the PMOS region through the second contact hole; And forming a drain electrode of the PMOS, wherein an interface between the first drain region of the NMOS region and the second drain region of the PMOS region is in contact with each other without a separation region.
The gate electrodes of the NMOS and PMOS regions are separately connected to respective power sources having complementary gator voltages.
After forming an interlayer insulating layer over the substrate, forming a first contact hole exposing a first drain region of the NMOS region and a second drain region of the PMOS region, a first source region of the NMOS region, and Forming a second contact hole for simultaneously exposing a second source region of the PMOS region, the NMOS and the PMOS respectively connected to the first drain region of the NMOS region and the second drain region of the PMOS region through the first contact hole Forming a drain electrode of the NMOS and a PMOS source electrode simultaneously connecting the first source region of the NMOS region and the second source region of the PMOS region through the second contact hole; A boundary between the first source region of the NMOS region and the second source region of the PMOS region is in contact with each other without a separation region.

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As described above, the present invention does not insulate the source region of NMOS and PMOS or the drain regions of NMOS and PMOS according to the use of a CMOS thin film transistor, and subsequently forms the source region or drain of the NMOS and PMOS. By using the source electrode or the drain electrode connected to the region in common, the area occupied by the CMOS element on the substrate can be reduced.

That is, in the related art, contact holes exposing the source region and the drain region are formed for the NMOS and PMOS thin film transistors, respectively. Thus, four contact holes are formed per unit CMOS thin film transistor. However, in the present invention, the N ⁺ region of the NMOS and the P ⁺ region of the PMOS, which are electrically connected through two contact holes, are connected through one contact hole, thereby reducing the area occupied by one contact hole as compared with the conventional art. There is a number. At this time, the contact hole is formed in the interface of the N ⁺ region and a P ⁺ region, thereby exposing the N ⁺ region and a P ⁺ region at the same time. The contact hole forms a drain electrode or a source electrode which is in contact with the N ⁺ region and the P ⁺ region at the same time.

Therefore, in the present invention, by reducing the area occupied by the CMOS element on the substrate, the degree of integration of the element can be further improved.

Hereinafter, a CMOS thin film transistor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 shows a plan view of a CMOS thin film transistor according to the present invention, and in particular, shows a CMOS device used as an inverter.

As shown in the figure, the inverter device according to the present invention is composed of an NMOS thin film transistor and a PMOS thin film transistor. The thin film transistor is a field effect transistor, which is the source region 122n of the NMOS region supplying electrons and the source region 122p of the PMOS region supplying holes, and the channel region through which the electrons or holes pass ( In the drawing, the gate electrodes are covered by the gate electrodes 121n and 121p), and the drain regions 122n and 122p through which electrons or holes passing through the channel exit.

In this case, gate electrodes 121n and 121p are formed on the channel region (not shown) with a gate insulating film interposed therebetween, thereby controlling the flow of electrons or holes by changing the potential of the channel. have.

First contact holes 128n and 128p and second contact holes 129n and 129p are formed on the source regions 122n and 122p and the drain regions 123n and 123p, respectively. In addition, source electrodes 124n and 124p are formed on the source regions 122n and 122p to be connected to the source regions 122n and 122p through the first contact holes 128n and 128p. Drain electrodes 125n and 125p are formed on 123p to connect with the drain regions 123n and 123p through the second contact holes 129n and 129p.

At this time, the interface between the drain region 123n of the NMOS and the drain region 123p of the PMOS is in contact with each other, and the second contact hole 129 exposing the drain regions 123n and 123p of the NMOS and PMOS is a drain region. A portion of the drain region 123n of the NMOS and a part of the drain region 123p of the PMOS are simultaneously exposed, including an interface between them 123n and 123p. That is, the second contact hole 129 may expose the first drain contact hole portion 129n and the drain region 123p of the PMOS to expose the drain region 123n of the NMOS around the interface between the drain regions 123n and 123p. ) Is divided into a second drain contact hole portion 129p. Accordingly, the first drain contact hole part 129n and the second drain contact hole part 129p are connected to each other to form one second contact hole 129.

Meanwhile, the gate electrodes 121n and 121p of the NMOS and PMOS are connected to an input line Vin connected to an external input terminal (not shown), and the drain electrode 125n of the NMOS and the drain electrode 125p of the PMOS are external. Commonly connected to the output line (Vout) is connected to the output terminal (not shown).

The source electrode 124n of the NMOS is connected to the ground line GND, and the source electrode 124p of the PMOS is connected to the power line Vdd.

In the inverter 100 of the present invention configured as described above, the drain region 123n of the NMOS and the drain region 123p of the PMOS are adjacent to each other without a spaced region, and contact holes exposing the drain region 123n are formed separately. Instead, since the drain regions 123n and 123p of the NMOS and the PMOS are simultaneously exposed through one second contact hole 129, the area occupied by the inverter element in the substrate is reduced.                     

That is, conventionally, the drain region of the NMOS and the drain region of the PMOS are spaced apart by a predetermined interval, and contact holes exposing each drain region are formed separately, whereas in the present invention, the drain region of the NMOS and the drain region of the PMOS are Since they are contacted without a spaced area, they can be exposed even with a single contact hole. Accordingly, the present invention reduces the number of contact holes exposing the drain region as compared with the related art, thereby improving the degree of integration of the device.

Figure 4 shows the area occupied by the conventional inverter and the inverter device of the present invention on the substrate, in particular a graph showing the change of the area occupied by the device according to the number of devices, the area occupied by the device as the number of inverter devices increases It can be seen that the relative decrease compared to the prior art. For reference, the solid line on the drawing shows the area change according to the number of inverter devices of the present invention, the dotted line shows the area change according to the number of conventional inverter devices.

Meanwhile, the present invention as described above may be applied to a transfer gate as well as an inverter.

5 is a plan view schematically showing a plane of a transfer gate device according to the present invention.

As shown in the figure, the transfer gate device according to the present invention is composed of an NMOS thin film transistor and a PMOS thin film transistor, and a PMOS supplying a source region 132n and a hole of an NMOS region for supplying electrons. The source region 132p of the region and the channel region through which the electrons or holes pass (obscured by the gate electrodes 131n and 131p on the drawing), and the drain regions 132n and 132p through which the electrons or holes passing through the channel escape. It consists of.

In this case, gate electrodes 121n and 121p are formed on the channel region (not shown) with a gate insulating film interposed therebetween, thereby controlling the flow of electrons or holes by changing the potential of the channel. have.

First contact holes 138n and 138p and second contact holes 139n and 139p are formed on the source regions 132n and 132p and the drain regions 133n and 133p, respectively. In addition, source electrodes 134n and 134p connected to the source regions 132n and 132p through the first contact hole 138 are formed on the source regions 132n and 132p, and the drain regions 133n and 133p. Drain electrodes 135n and 135p connected to the drain regions 133n and 133p are formed on the second contact holes 139n and 139p.

In this case, an interface between the NMOS source region 132n and the PMOS source region 132p is in contact with each other, and the first contact hole 138 exposing the NMOS and PMOS source regions 132n and 132p is a source region. A portion of the NMOS source region 132n and the PMOS source region 132p are simultaneously exposed, including an interface between the two 132n and 132p. That is, the first contact hole 138 exposes the source region 132n of the NMOS around the interface between the source regions 132n and 132p and the source region 138p of the PMOS. ) Is divided into a second drain contact hole portion 138p. Therefore, the first source contact hole portion 138n and the second source contact hole portion 138p are connected to each other to form one second contact hole 128.

On the other hand, the gate electrodes 131n and 131p of the NMOS and PMOS are separately connected to respective power sources having complementary gate voltages, and the source electrode 134n of the NMOS and the source electrode 134p of the PMOS are input lines Vin. Are connected in common. The drain electrode 135n of the NMOS and the drain electrode 135p of the PMOS are commonly connected to the output line Vout.

In addition, as mentioned, the source electrode 134n of the NMOS is connected to the source region 132n below the source electrode 134n through the first source contact hole 138n, and the source electrode 134p of the PMOS. Is connected to the lower source region 132p through the second source contact hole portion 138p.

As described above, the transfer gates according to the present invention are adjacent to each other without a separation area between the source region 132n of the NMOS and the source region 132p of the PMOS, and the first contact hole 138 is the source of the NMOS and the PMOS. Since the regions 132n and 132p are simultaneously exposed, the number of contact holes can be reduced as compared with the prior art, thereby reducing the area occupied by the transfer gate element on the substrate. That is, conventionally, contact holes for exposing the source region of the NMOS and the source region of the PMOS are separately provided, whereas in the present invention, since the source regions of the NMOS and the PMOS are simultaneously exposed through one contact hole, the contact holes are exposed simultaneously. The area occupied by the device is reduced.

6 is a graph showing the area occupied by a conventional transfer gate device and a transfer gate device of the present invention on a substrate. In particular, the graph shows a change in the area occupied by a device according to the number of devices. It can be seen that the area occupied in the phase is relatively reduced in comparison with the prior art. That is, as the number of devices increases, the difference in device integration between the conventional and the present invention becomes larger. For reference, the solid line on the drawing shows the area change according to the number of inverter devices of the present invention, the dotted line shows the area change according to the number of conventional inverter devices.

FIG. 7 illustrates a CMOS thin film transistor having a cutting plane taken along the line II ′ of FIG. 5. As illustrated in FIG. 5, the CMOS thin film transistor 200 includes NMOS and PMOS.

NMOS and PMOS are formed on the substrate 210 with active layers divided into channel regions 230n and 230p and source regions 232n and 232p and drain regions 233n and 233p on both sides of the channel regions 230n and 230p, respectively. Gate electrodes 231n and 231p are formed on the channel regions 230n and 230p. In this case, a first insulating layer 241 is formed between the channel regions 230n and 230p and the gate electrodes 231n and 231p, and the first insulating layer 241 is formed on the entire surface of the substrate 210 including the active layer. It is formed over.

In addition, a second insulating layer 242 is formed on the entire surface of the substrate 210 including the gate electrodes 231n and 231p, and source regions 232n and PMOS of the NMOS and PMOS are formed in the first and second insulating layers 241 and 242. First contact holes 238 exposing 232p at the same time and second contact holes 239n and 239p exposing portions of the drain regions 233n and 233p are formed.

On the second insulating layer 242, source electrodes 234n and 234p contacting source regions 232n and 232p of NMOS and PMOS through the first contact hole 238, and the second contact hole 239n and Drain electrodes 235n and 235p are formed in contact with the drain regions 233n and 233p through 239p.

In this case, the NMOS source region 232n and the PMOS source region 232p are adjacent to each other, and their interface faces each other, and the second contact hole 238 opens the NMOS and PMOS source regions 232n and 232p. It will be exposed at the same time.                     

As described above, according to the present invention, the N ⁺ region (source region of NMOS; 232n) and the P ⁺ region (PMOS region) of the NMOS and PMOS source regions 232n and 232p are simultaneously exposed through the second contact hole 238. Source regions 232p are formed adjacent to each other.

Meanwhile, an undoped region is formed in a predetermined portion between the channel region and the source / drain region of the NMOS region to form an offset, or a lightly doped drain (LDD) region that is lightly doped to form an off current. You can also reduce and minimize the reduction of on current.

The CMOS thin film transistor of the present invention configured as described above is manufactured through the following process.

First, a transparent substrate 210 is prepared, and then a polysilicon film is formed on the substrate 210 and then panned to form an active layer. After forming a first insulating film () on the entire surface of the substrate including the active layer, gate electrodes 231n and 231p are formed on the first insulating film 241 corresponding to the active layer.

Next, after blocking the PMOS region, N + impurity ions are doped on both sides of the active layer using the gate electrode 231n of the NMOS as a mask to form N + regions, that is, source and drain regions 232n and 233n.

After the NMOS region is blocked, P + regions, that is, source and drain regions 232p and 233p are formed on both sides of the active layer using the gate electrode 231p of the PMOS region as a mask.                     

At this time, the source region 232n of the NMOS and the source region 232p of the PMOS are adjacent to each other.

Subsequently, after the second insulating layer 242 is formed on the entire surface of the substrate including the gate electrodes 231n and 231p, portions of the first and second insulating layers 241 and 242 are removed to remove the source region 232n, First contact holes 238 exposing 232p and second contact holes 239n and 239p exposing drain regions 233n and 233p are formed. In this case, the first contact hole 238 is formed at the interface between the source region 232p of the PMOS and the source region 232n of the NMOS to expose them simultaneously.

Subsequently, the first contact hole 238 is drained through the source electrodes 234n and 234p contacting the NMOS source region 232n and the PMOS source region 232p and the second contact holes 239n and 239p. The drain electrode 235n of the NMOS and the drain electrode 235p of the PMOS are formed in contact with the regions 233n and 233p, respectively.

In this case, the source electrodes 234n and 234p are connected to an external input terminal, and the drain electrodes 235n and 235p of the NMOS and PMOS are connected to an external output terminal.

Meanwhile, when the CMOS thin film transistor is used as an inverter device, the source electrode 234n of the NMOS is grounded, the source electrode 234p of the PMOS is connected to a power supply, and the drain electrode Ensure that (235n, 235p) is commonly connected to the external output.

Therefore, when the inverter device is manufactured, the drain electrode is formed in common.                     

As described above, the present invention provides a CMOS thin film transistor and a method of manufacturing the device can reduce the area on the substrate. Meanwhile, in the present invention, the inverter device and the transfer gate device have been described as an example. However, the present invention is not limited to the above two devices, and the present invention is not limited to the two devices, but may be applied to all devices capable of connecting two source or drain regions through one contact hole. Will include.

As described above, the CMOS thin film transistor and the method of manufacturing the same according to the present invention, the source region or the drain region of the NMOS or PMOS are formed adjacent to each other, and the source of the NMOS and PMOS through one contact hole By simultaneously exposing the region or the drain region, the area occupied by the element can be reduced as compared with the conventional art.

As described above, the present invention has an effect of further improving the adhesion of the device by reducing the area occupied by the device on the substrate.

Claims (11)

A substrate in which an NMOS region and a PMOS region are defined; An active layer formed in the NMOS and PMOS regions; A gate electrode formed on the active layer; First source and drain regions formed on both sides of the active layer of the NMOS region; Second source and drain regions formed on both sides of the active layer of the PMOS region; An interlayer insulating film formed on the entire surface of the substrate including gate electrodes formed on the NMOS and PMOS regions; A first contact hole exposing a first source region of the NMOS region and a second source region of the PMOS region, respectively; A second contact hole exposing the first drain region of the NMOS region and the second drain region of the PMOS region simultaneously; Source electrodes of NMOS and PMOS connected to the first source region of the NMOS region and the second source region of the PMOS region, respectively, through the first contact hole; And A drain electrode of an NMOS and a PMOS simultaneously connecting the first drain region of the NMOS region and the second drain region of the PMOS region through the second contact hole; And the first drain region of the NMOS region and the second drain region of the PMOS region are in contact with each other without a separation region. The CMOS thin film transistor of claim 1, wherein the gate electrodes of the NMOS and PMOS regions are connected to an external input terminal. The CMOS thin film transistor of claim 1, wherein the source electrodes of the NMOS and PMOS regions are connected to a power line. The CMOS thin film transistor of claim 1, wherein the drain electrodes of the NMOS and PMOS regions are connected to an external output terminal. The CMOS thin film transistor according to claim 1, further comprising a gate insulating film interposed between the active layer and the gate electrode. The CMOS thin film transistor according to claim 1, wherein the gate electrodes of the NMOS and PMOS regions are separately connected to respective power sources having complementary gate voltages. The method of claim 6, A first contact hole exposing a first drain region of the NMOS region and a second drain region of the PMOS region, respectively; A second contact hole exposing the first source region of the NMOS region and the second source region of the PMOS region simultaneously; Drain electrodes of NMOS and PMOS connected to the first drain region of the NMOS region and the second drain region of the PMOS region through the first contact hole; And A source electrode of an NMOS and a PMOS simultaneously connecting the first source region of the NMOS region and the second source region of the PMOS region through the second contact hole; And the interface between the first source region of the NMOS region and the second source region of the PMOS region is in contact with each other without a separation region. delete Preparing a substrate in which an NMOS region and a PMOS region are defined; Forming active layers in the NMOS and PMOS regions; Forming a gate electrode on the active layer; Forming first source and drain regions on both sides of the active layer of the NMOS region; Forming second source and drain regions on both sides of the active layer of the PMOS region; Forming an interlayer insulating film on the entire surface of the substrate including gate electrodes formed on the NMOS and PMOS regions; Forming a first contact hole exposing a first source region of the NMOS region and a second source region of the PMOS region, respectively; Forming a second contact hole for simultaneously exposing a first drain region of the NMOS region and a second drain region of the PMOS region; Forming source electrodes of NMOS and PMOS respectively connected to the first source region of the NMOS region and the second source region of the PMOS region through the first contact hole; And Forming a drain electrode of the NMOS and the PMOS simultaneously connecting the first drain region of the NMOS region and the second drain region of the PMOS region through the second contact hole, And the interface between the first drain region of the NMOS region and the second drain region of the PMOS region is in contact with each other without a separation region. 10. The method of claim 9, And the gate electrodes of the NMOS and PMOS regions are separately connected to respective power sources having complementary gator voltages. 10. The method of claim 9, After the step of forming an interlayer insulating film on the entire surface of the substrate, Forming a first contact hole exposing a first drain region of the NMOS region and a second drain region of the PMOS region, respectively; Forming a second contact hole for simultaneously exposing a first source region of the NMOS region and a second source region of the PMOS region; Forming drain electrodes of the NMOS and the PMOS connected to the first drain region of the NMOS region and the second drain region of the PMOS region through the first contact hole; And Forming source electrodes of NMOS and PMOS simultaneously connecting the first source region of the NMOS region and the second source region of the PMOS region through the second contact hole; And the interface between the first source region of the NMOS region and the second source region of the PMOS region is in contact with each other without a spaced region.

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