KR101046084B1 - Metal core substrate and multilayer printed circuit board including the same and method for manufacturing same - Google Patents

Abstract

The present invention relates to a metal core substrate, a multilayer printed circuit board including the same, and a method of manufacturing the same. The metal core substrate according to the present invention includes a metal core layer having via holes formed therein; First insulating resin layers formed on both sides of the metal core layer and via holes, the first insulating resin layers being formed to have a smaller cross-sectional area at a central portion than both end portions of the via holes; And a circuit pattern formed on the first insulating resin layer and electrically connected by the via hole. The metal core substrate according to the present invention does not require an additional process for forming a via hole in an insulating layer, and has excellent via fill performance. The multilayer printed circuit board including the same has excellent heat dissipation characteristics and interlayer connection reliability.

Metal core substrate, resin deposition, multilayer printed circuit board.

Description

Metal core board and multilayer printed circuit board including the same and method for manufacturing the same {Metal core board and multilayer printed circuit board comprising the same and manufacturing method

The present invention relates to a metal core substrate, a multilayer printed circuit board including the same, and a method of manufacturing the same. More specifically, a metal core substrate having excellent processing accuracy, and a multilayer printed circuit board having excellent interlayer connection reliability including the same, and their It relates to a manufacturing method.

With the trend toward miniaturization, thinning, high density, and packaging of electronic products, printed circuit boards are also undergoing fine patterns, miniaturization, and packaging. In order to increase the fine pattern formation, reliability, and design density of printed circuit boards, there is a change in a structure in which the layer structure of the circuit is combined with the change of raw materials. As the parts are also changed from DIP (Dual In-Line Package) type to Surface Mount Technology (SMT) type, their mounting density is also increasing.

In addition to the portableization of electronic products, high-performance, Internet, video, and high-capacity data transmission and transmission have complicated the design of printed circuit boards and require high-tech technologies.

Printed circuit boards include single-sided PCBs with wires formed on only one side of the insulated board, double-sided PCBs with wires formed on both sides, and MLBs (multilayer printed circuit boards) wired in multiple layers. In the past, single-sided PCBs were used because of their simple components and simple circuit patterns. Recently, double-sided PCBs or MLBs have been used due to the increased complexity of circuits and the increasing demand for high density and miniaturized circuits.

The MLB is an additional wiring layer formed to enlarge the wiring area. Specifically, the MLB is divided into an inner layer and an outer layer, and a thin core (Thin Core) is used as the inner layer material, and a four-layer MLB (two inner layers and two outer layers) having a structure in which the outer layer and the inner layer are bonded by a preplex is used. do. Depending on the complexity of the circuit, it may be composed of six, eight, and ten or more layers.

A power circuit, a ground circuit, a signal circuit, and the like are formed in the inner layer, and insulation and adhesion are performed between the inner layer and the outer layer or the outer layer, and wiring of each layer is connected using via holes.

MLB has the great advantage that it can significantly increase the wiring density, but the manufacturing process has a complex disadvantage. In particular, since the inner layer is not deformable when the process is completed according to the conventional build-up method, if there is an error in the inner layer, all the finished products become defective. Therefore, in order to improve the quality of MLB, it is necessary to raise the processing accuracy of an inner layer. In addition, as the number of chips mounted on a printed circuit board and the density thereof increase, the need for a printed circuit board having high heat dissipation characteristics also increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a metal core substrate having excellent processing precision and heat dissipation characteristics, a multilayer printed circuit board including the same, and a manufacturing method thereof.

One embodiment of the present invention is a metal core layer with a via hole formed; First insulating resin layers formed on both sides of the metal core layer and via holes, the first insulating resin layers being formed to have a smaller cross-sectional area at a central portion than both end portions of the via holes; And a circuit pattern formed on the first insulating resin layer and electrically connected by the via holes.

The via hole may gradually decrease in cross-sectional area from both ends to the center.

Both vias may be symmetrical with respect to the center of the via hole.

The metal core may be made of any one of aluminum (Al), magnesium (Mg), titanium (Ti), zinc (Zn), tantalum (Ta), iron (Fe), nickel (Ni), and alloys thereof.

The first insulating resin may be any one of epoxy, polyester, bismaleimide triazine, polyimide, polytetrafluoroethylene, and liquid crystal polymer.

Another embodiment of the present invention is a metal core layer having a via hole, a first insulating resin layer formed on both sides and via holes of the metal core layer, the cross-sectional area of the center portion being smaller than both ends of the via hole, and the first insulating layer. A metal core substrate formed on an insulating resin layer, the metal core substrate including an inner circuit pattern to be electrically connected by the via hole; Second insulating resin layers formed on both surfaces of the metal core substrate; And an outer layer circuit pattern formed on the second insulating resin layer and electrically connected to the inner layer circuit pattern.

The outer circuit pattern may include a stack via connected to a via hole of a metal core substrate.

Another embodiment of the present invention includes forming via holes in the metal core layer; Forming a first insulating resin layer on both sides of the metal core layer and the via hole, wherein the first insulating resin layer is formed to have a smaller cross-sectional area at a central portion than both end portions of the via hole; And forming a circuit pattern formed on the first insulating resin layer and electrically connected by the via hole.

The formation of the first insulating resin layer may be performed by a resin deposition method, and the thickness of the first insulating resin layer may be adjusted according to the viscosity and the deposition time of the resin.

Another embodiment of the present invention includes forming via holes in the metal core layer; Forming a first insulating resin layer on both sides of the metal core layer and the via hole, wherein the first insulating resin layer is formed to have a smaller cross-sectional area at a central portion than both end portions of the via hole; Forming an inner circuit pattern formed on the first insulating resin layer and electrically connected to the via hole; Forming a second insulating resin layer on the first insulating resin layer; And forming an outer layer circuit pattern formed on the second insulating resin layer and electrically connected to the inner layer circuit pattern.

As described above, the metal core substrate according to the present invention does not require an additional process for forming a via hole in the insulating layer, thereby reducing cost and lead time. In addition, the via fill performance is excellent and the machining precision is improved. Therefore, the multilayer printed circuit board including the same has excellent heat dissipation characteristics and excellent interlayer connection reliability.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

1 is a schematic cross-sectional view showing a metal core substrate according to one embodiment of the present invention. Referring to FIG. 1, the metal core substrate according to the present embodiment may include a metal core layer 10 having an interstitial via hole (IVH) 20 formed therein; First insulating resin layers 30 formed on both sides of the metal core layer and via holes 20, and having a cross-sectional area of the central portion 20b smaller than both end portions 20a of the via holes 20; And a circuit pattern 41 formed on the first insulating resin layer 30 and electrically connected by the via hole 20.

The metal core 11 used in the metal core layer 10 may be, but is not limited to, aluminum (Al), magnesium (Mg) titanium (Ti), zinc (Zn), tantalum (Ta), iron (Fe), Nickel (Ni) and alloys thereof. As commercially available products, Invar may be used.

The thickness of the metal core 11 is not particularly limited, but may have a thickness of 30 to 100 μm. It is preferable that the metal core 11 is surface-treated 12 in order to improve the adhesion reliability with the insulated resin layer. The surface treatment may be an oxide film layer, a Cu sputter or a copper plating layer.

The first insulating resin layer 30 is formed on both surfaces of the metal core layer 10 and the via holes 20. 2 shows an enlarged view of the via hole 20 region. Referring to this, the via hole 20 in which the first insulating resin layer 30 is formed has a smaller cross-sectional area of the central portion 20b than both of the terminal portions 20a. That is, the thickness of the first insulating resin layer formed on both end portions 20a of the via hole 20 is greater than the thickness of the first insulating resin layer formed on the central portion 20b of the via hole 20.

The via hole 20 having a smaller cross-sectional area of the center portion 20b than both of the end portions 20a is advantageous for via fill.

In general, the via fill is different depending on the thickness of the substrate, but when the thickness is large and the size of the via hole is large, defects are likely to occur. However, the via fill performance is improved by the shape of the via hole as described above.

The cross-sectional area may gradually decrease from both end portions 20a of the via hole 20 toward the center portion 20b. In addition, both ends 20a of the via hole 20 may be symmetrical with respect to the center portion 20b.

The shape of the via hole as described above may be adjusted according to the viscosity and deposition time of the first insulating resin, which will be described in detail later.

The first insulating resin layer 30 is not limited thereto, but thermosetting resins such as epoxy, polyester, bis maleimide triazine (BT) or polyimide, and polytetrafluoroethylene (PTFE: Thermoplastic resins such as polytetrafluoroethylene (LCP) and liquid crystal polymer (LCP) may be used.

The circuit pattern 41 is formed on the first insulating resin layer 30, the via holes 20 are filled with a conductive material, and the circuit patterns formed on both surfaces of the metal core layer are electrically connected by the via holes 20. In other words, the present embodiment corresponds to a double-sided PCB in which circuit patterns are formed on both surfaces of the metal core layer 10.

3 is a schematic cross-sectional view illustrating a multilayer printed circuit board according to an exemplary embodiment of the present invention.

Referring to Figure 3, the multilayer printed circuit board of the present invention is a metal core substrate; It includes an outer layer circuit layer formed on both sides of the metal core substrate. The outer circuit layer may be formed by a buildup method. The buildup method refers to a manufacturing method of a method in which an insulating layer and a conductive layer are stacked one by one on an inner layer where a circuit pattern is formed.

In this embodiment, the multilayer printed circuit board includes metal core layers 10 and 11 having via holes 20 formed therein; First insulating resin layers 30 formed on both sides of the metal core layer and via holes, and formed to have a smaller cross-sectional area of the central portion 20b than both end portions 20a of the via hole; A metal core substrate formed on the first insulating resin layer 30 and including an inner circuit pattern 41 that is electrically connected by the via hole; And an outer layer circuit pattern 81 formed on the second insulation resin layer 60 formed on both surfaces of the metal core substrate and the second insulation resin layer 60 and electrically connected to the inner layer circuit pattern.

The outer circuit pattern includes a blind via hole 70 for electrical connection with the circuit pattern 41 formed on the metal core substrate. The blind via hole 70 may be formed as a stack via.

Although the present embodiment is illustrated as a four-layer printed circuit board, the insulating layer and the conductive layer may be additionally formed on the outer circuit layer, and thus may be implemented as six or eight layers.

Hereinafter, a method of manufacturing a metal core substrate and a multilayer printed circuit board according to the present invention will be described with reference to FIGS. 4 and 5.

4A to 4G are cross-sectional views illustrating processes for manufacturing a metal core substrate according to one embodiment of the present invention.

First, as shown in FIG. 4A, a metal core 11 is provided. It is preferable that the metal core 11 is subjected to the surface treatment 12 in order to improve the adhesion reliability with the insulating resin layer. The surface treatment method is not particularly limited as long as it is a method capable of forming roughness on the surface of the metal core. For example, an oxide film layer may be formed, or Cu sputtering or copper plating may be performed.

Next, as shown in FIG. 4B, a via hole 20 is formed for connection between both layers of the metal core 11. The method of forming the via hole 20 is not particularly limited as long as it is known in the art, but may be formed by etching or drilling.

Thereafter, as shown in FIG. 4C, the first insulating resin layer 30 is formed on both surfaces of the metal core 11 and the via holes 20. 4D is an enlarged view of the region of the via hole 20 in which the first insulating resin layer is formed. Referring to this, the first insulating resin layer 30 is formed to have a smaller cross-sectional area of the central portion 20b than both end portions 20a of the via hole 20 formed in the metal core 11. The cross-sectional area may gradually decrease from both end portions 20a of the via hole 20 to the center portion 20b, and both ends 20a of the via hole 20 may be symmetrical with respect to the center portion 20b. .

The shape of the via hole as described above may be adjusted according to the viscosity and deposition time of the first insulating resin.

Although the deposition of the first insulating resin is not limited thereto, a method such as dip coating, vapor deposition, or electrodeposition may be used.

Dip coating is carried out by impregnating a metal core at a constant rate into a tank containing a resin and then drying. In addition, electrodeposition is a method of depositing a resin on the metal core by applying a current to the metal core as a positive electrode or a negative electrode in a solution in which the resin is dissolved.

In the case of electrodeposition, an insulation resin layer having a thickness of 5 to 20 µm may be formed by applying a current of 0.5 to 5 A for 20 minutes.

After filling the vias by laminating an insulating layer on the metal core on which the via holes are formed, when machining the holes in the insulating layer by mechanical drilling or the like, the machining accuracy may be lowered and the alignment may be misaligned when the both surfaces are processed.

However, in the present embodiment, the via hole forming step of the insulating layer is not required because the via hole is not completely filled in the formation of the first insulating resin layer.

In addition, the via fill is generally different depending on the thickness of the substrate, but when the thickness is large and the holes are large, or when the via holes are aligned, no via fill or dimple And seam voids may occur. However, the via fill performance is improved by the shape of the via hole as described above.

In addition, the insulating resin layer can be formed thin, and a thin film substrate can be formed.

Next, as shown in FIG. 4E, a first conductive layer 40 is formed in the via hole 20 and the first insulating resin layer 30.

Although not limited thereto, the first conductive layer 40 may be formed by electroless plating after electroless plating. Electroless plating has the disadvantage of being difficult to process and borderless, and therefore, the conductive portion of the circuit pattern is preferably formed by electroplating. Therefore, in order to form the electroconductive film necessary for electrolytic plating in the 1st insulating resin layer 30, electroless plating can be performed thinly by the preprocess.

In addition, fine roughness may be formed in the first insulating resin layer 30 in order to improve the adhesive strength before the electroless plating. The method of forming the roughness is not particularly limited, but for example, wet-desmear or plasma treatment may be used.

In the plating process, the via holes 20 are filled to electrically connect circuit patterns formed on both sides of the metal core. As described above, the shape of the cross-sectional area of the central portion 20b of the via hole 20 smaller than the both end portions 20a of the via hole 20 is excellent in fill performance and thus lowers the occurrence rate of plating defects.

After that, a circuit pattern is formed on the first conductive layer 40. The circuit pattern formation method may use a method known in the art. In this embodiment, the method by etching is demonstrated. As shown in FIG. 4F, an etching resist pattern 50 for forming a circuit pattern is formed on the first conductive layer 40.

In order to form the etching resist pattern, the circuit pattern printed on the artwork film must be transferred onto the first conductive layer 40. There are various methods of transferring, but the most commonly used method is to use a photosensitive dry film. Instead of dry film, LPR (Liquid Photo Resist) can be used.

The dry film or the LPR, to which the circuit pattern is transferred, acts as an etching resist, and as shown in FIG. 4G, the conductive layer 40 in the region 50a in which the etching resist pattern 50 is not formed is removed by etching. The predetermined circuit pattern 41 is formed.

5A to 5C are cross-sectional views of processes illustrating a method of manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention.

First, as shown in FIG. 5A, second insulating layers 60 are formed on both surfaces of the metal core substrate. The metal core substrate can be manufactured by the method mentioned above.

Next, a blind via hole 70 is formed on the second insulating layer 60 for electrical connection between the inner layer and the outer layer. Although FIG. 5A illustrates only the blind via hole 70 formed in the second insulating layer 60 formed on one surface of the metal core substrate, the blind via hole 70 is also formed in the second insulating layer 60 formed on the other surface. The blind via hole 70 is illustrated as being formed of a stack via, but is not limited thereto.

The formation of the blind via hole may be formed using silver mechanical drilling or laser. The laser may use a YAG laser or a CO 2 laser.

Thereafter, as shown in FIG. 5B, the second conductive layer 80 is formed in the blind via hole 70 and the second insulating layer 60. The formation method of the 2nd conductive layer 80 is not specifically limited, As mentioned above, an electroless plating and an electrolytic plating process can be used.

Next, as illustrated in FIG. 5C, an outer circuit pattern 81 is formed on the second conductive layer 80. Although the formation of the outer layer circuit pattern 81 is not particularly limited, as described above, it can be formed using an etching resist.

Although not shown, the outer circuit layer may be formed of Resin Coated Copper (RCC) in which a copper foil layer is formed on only one surface of the resin layer.

Although not shown, a solder resist may be formed on the outer circuit pattern 81 except for a portion connected to the semiconductor chip. The solder resist may be formed using a screen printing method or a roll coating printing method. The solder bumps may be formed using a solder screen printing method or a solder plating method according to a connection method with a semiconductor chip.

As described above, the manufacturing process of the four-layer printed circuit board has been described, but the six-layer, eight-layer, etc. may be manufactured by additionally forming the outer circuit layer.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

1 is a schematic cross-sectional view showing a metal core substrate according to one embodiment of the present invention.

2 is an enlarged cross-sectional view showing a via hole region of a metal core substrate according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a multilayer printed circuit board according to an exemplary embodiment of the present disclosure.

4A to 4G are cross-sectional views illustrating processes for manufacturing a metal core substrate according to one embodiment of the present invention.

5A and 5C are cross-sectional views illustrating processes for manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: metal core layer 20: via hole

30: first insulating resin layer 40: first conductive layer

41: circuit pattern 50: etching resist

60: first insulating resin layer 70: blind via hole

80: second conductive layer 81: outer circuit pattern

Claims (11)

A metal core layer having via holes formed therein; First insulating resin layers formed on both surfaces of the metal core layer and via holes, and formed by a resin deposition method such that a cross-sectional area of the center portion is smaller than both ends of the via hole; And A circuit pattern formed on the first insulating resin layer and electrically connected by the via holes; Metal core substrate comprising a. The method of claim 1, The via hole is a metal core substrate, characterized in that the cross-sectional area gradually decreases from both ends to the center. The method of claim 1, The via hole is a metal core substrate, characterized in that both ends are symmetrical with respect to the center portion. The method of claim 1, The metal core layer is made of any one of aluminum (Al), magnesium (Mg) titanium (Ti), zinc (Zn), tantalum (Ta), iron (Fe), nickel (Ni) and alloys thereof. Metal core substrate. The method of claim 1, The first insulating resin layer is any one of epoxy, polyester, bismaleimide triazine, polyimide, polytetrafluoroethylene and liquid crystal polymer. A first insulating resin layer formed by a resin deposition method and a first insulating resin formed on a metal core layer having via holes formed on both sides of the metal core layer and via holes, and having a cross-sectional area of a central portion smaller than both ends of the via holes. A metal core substrate formed on the ground layer, the metal core substrate including an inner circuit pattern to be electrically connected by the via hole; Second insulating resin layers formed on both surfaces of the metal core substrate; And An outer circuit pattern formed on the second insulating resin layer and electrically connected to the inner circuit pattern; Multilayer printed circuit board comprising a. The method of claim 6, The outer circuit pattern may include a stack via connected to a via hole of a metal core substrate. Forming via holes in the metal core layer; Forming a first insulating resin layer on both surfaces of the metal core layer and the via hole, wherein the first insulating resin layer is formed by a resin deposition method so that the cross-sectional area of the center portion is smaller than both ends of the via hole; And Forming a circuit pattern formed on the first insulating resin layer and electrically connected to the via hole; Method of manufacturing a metal core substrate comprising a. delete The method of claim 8, The first insulating resin layer is a method of manufacturing a metal core substrate, characterized in that the thickness is adjusted according to the viscosity and the deposition time of the resin. Forming via holes in the metal core layer; Forming a first insulating resin layer on both surfaces of the metal core layer and the via hole, wherein the first insulating resin layer is formed by a resin deposition method so that the cross-sectional area of the center portion is smaller than both ends of the via hole; Forming an inner circuit pattern formed on the first insulating resin layer and electrically connected to the via hole; Forming a second insulating resin layer on the first insulating resin layer; And Forming an outer circuit pattern formed on the second insulating resin layer and electrically connected to the inner circuit pattern; Method of manufacturing a multilayer printed circuit board comprising a.

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