KR101046747B1 - Method of forming fine pattern of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a fine pattern of a semiconductor device that can improve the non-uniformity of the critical dimension of the line line width due to two times the mask operation during the DEET (Double Exposure Etch Technology) process, To this end, the present invention comprises the steps of forming a first hard mask on the etched layer, forming a second hard mask on the first hard mask, forming a sacrificial film on the second hard mask, Locally etching the sacrificial layer to form a sacrificial pattern; forming an insulating film along an upper surface of the second hard mask including the sacrificial pattern; partially etching the insulating film on both sidewalls of the sacrificial pattern; Forming a spacer, removing the sacrificial pattern, and etching the second hard mask using the spacer as an etch barrier layer to form a first spacer. Forming a hard mask pattern, removing the spacers, etching the first hard mask using the first hard mask pattern as an etch barrier layer, and forming a second hard mask pattern; And etching the layer to be etched using a second hard mask pattern.

 Semiconductor devices, fine patterns, DEET

Description

METHOD FOR FORMING MICROPATTERN IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a fine pattern of a semiconductor device.

Recently, as semiconductor devices have been highly integrated, lines and spaces of 40 nm or less (hereinafter, referred to as LS) are required. However, it is very difficult to form 'LS' of 60 nm or less due to the limitations of the exposure equipment currently developed and commercialized. Accordingly, the DEET (Double Exposure Etch Technology) process technology has been proposed to realize a fine 'LS' of 60 nm or less while using a commercially available exposure equipment.

Hereinafter, a method of forming a fine pattern of a semiconductor device according to the related art to which the DEET process is applied will be described with reference to FIGS. 1A to 1D. 1A to 1D are cross-sectional views of the process.

First, as shown in FIG. 1A, first and second hard masks 102 and 103 formed of heterogeneous materials are sequentially formed on the semiconductor substrate 100 on which the etched layer 101 is formed.

Subsequently, a photoresist film is coated on the second hard mask 103, and then a mask process including an exposure and development process using a photomask is performed to form a photoresist pattern 104 (hereinafter referred to as a first photoresist pattern). .

Subsequently, as illustrated in FIG. 1B, the second hard mask 103 (see FIG. 1A) is etched by performing an etching process using the first photoresist pattern 104. As a result, the second hard mask pattern 103A is formed.

Subsequently, as illustrated in FIG. 1C, a mask process is performed to form a photosensitive film pattern 105 (hereinafter referred to as a second photosensitive film pattern) between the second hard mask patterns 103A.

Subsequently, as illustrated in FIG. 1D, an etching process using the second hard mask pattern 103A (see FIG. 1C) and the second photoresist pattern 105 (see FIG. 1C) as an etching mask is performed to form the first hard mask 102. , See FIG. 1C). As a result, the first hard mask pattern 102A is formed.

Subsequently, an etching process using the first hard mask pattern 102A as an etching mask is performed to etch the etching target layer 101. As a result, fine patterns (or lines) (not shown) are formed.

As such, in the method of forming a micropattern of a semiconductor device according to the prior art to which the DEET process technology is applied, a major problem is that the linewidth uniformity of the micropattern depends on the overlay accuracy of the first and second masks. . In order to secure the line width uniformity of the micro pattern suitable for the device characteristics, the alignment of the first mask and the second mask should be controlled to 4 nm or less on the basis of '│Me│ + 3σ'. Because it can only control the equipment development is required, but it is not implemented due to technical limitations. Furthermore, as shown in FIG. 1C, the second hard mask pattern 103A is lost by forming the second photoresist pattern 105 through a mask process in a state where the second hard mask pattern 103A is formed, thereby causing the second hard mask pattern 103A to be lost. The critical dimension of the hard mask pattern 103A is deformed.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and provides a method of forming a fine pattern of a semiconductor device capable of improving the critical dimension nonuniformity of the line width due to two mask operations performed during the DEET process. Its purpose is to.

According to an aspect of the present invention, there is provided a semiconductor device comprising: forming a first hard mask using an oxide film on an etched layer formed of an amorphous carbon film; Forming a second hard mask on the first hard mask by using a polysilicon film; Forming a sacrificial pattern on the second hard mask by using an amorphous carbon film; Forming a spacer on both sidewalls of the sacrificial pattern by using a nitride film; Removing the sacrificial pattern; Etching the second hard mask with the spacer as an etch barrier layer to form a first hard mask pattern; Removing the spacers; And etching the first hard mask and the etched layer using the first hard mask pattern as an etch barrier layer, forming the sacrificial pattern, forming the first hard mask pattern, and forming the etched layer. Etching step provides a method of forming a fine pattern of a semiconductor device proceeding by adding a passivation gas to obtain a vertical profile.

According to the present invention including the above-described configuration, the following effects can be obtained.

First, according to the present invention, it is possible to implement a fine pattern like the DEET process with only one mask process.

Second, according to the present invention, it is possible to improve the non-uniformity of the line critical dimension due to the misalignment caused by the two mask process performed during the general DEET process.

Third, according to the present invention, by improving the yield by improving the asymmetry problem generated in the prior art of etching the spacer layer by the etching barrier layer by etching the etching target layer with the lower hard mask pattern as an etching barrier layer after removing the spacer. You can.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

2A to 2G are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention. Here, as an example, a method of forming a fine pattern of a semiconductor device using a hard mask formed on the gate electrode as an etched layer will be described.

First, as shown in FIG. 2A, an etched layer 201, which is a hard mask, is formed on a semiconductor substrate 200 on which a gate electrode (not shown) is formed. In this case, the etching target layer 201 may be formed of any one selected from materials having a high etching selectivity with respect to the gate electrode. For example, the etched layer 201 is formed of an oxide film or a nitride film containing silicon, or is formed of any one selected from a film containing carbon, a polycrystalline silicon film, or a laminated film in which these layers are stacked. Here, as an example, the etched layer 201 is formed of a carbon-containing film, that is, an amorphous carbon film, and is formed at a thickness of 3000 kPa to 6000 kPa, preferably 4500 kPa.

The gate electrode may be formed of a transition metal, a polycrystalline silicon film, a metal silicide layer, or a laminated film in which the gate electrode is stacked. In this case, as the transition metal, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg are used. In addition, the metal silicide layer is formed through the reaction of the above-described transition metal and silicon, for example, a tungsten silicide layer.

Next, a first hard mask 202 is formed on the etched layer 201. In this case, the first hard mask 202 may be formed of any one selected from a heterogeneous material different from the etched layer 201, more specifically, a heterogeneous material having a high etching selectivity with the etched layer 201. For example, when the etched layer 201 is formed of an amorphous carbon film, the first hard mask 202 is formed of an oxide film, specifically, TEOS (Tetra Ethyle Ortho Silicate). It is formed to a thickness of about 400 GPa, in addition to USG (Un-doped Silicate Glass), BPSG (BoroPhosphoSilicate Glass), PSG (PhosphoSilicate Glass), BSG (BoroSilicate Glass) and HDP (High Density Plasma). It may be.

Next, a second hard mask 203 is formed on the first hard mask 202. In this case, the second hard mask 203 may be formed of one of different materials different from the first hard mask 202, more specifically, different materials having high etching selectivity with the first hard mask 202. Can be. For example, when the first hard mask 202 is formed of an oxide film, the first hard mask 202 is formed of a polysilicon film having a high etching selectivity with respect to the oxide film. The second hard mask 203 is formed to have the same thickness as that of the first hard mask 202, preferably 300 μs to 500 μs.

Subsequently, a sacrificial film 204 is formed on the second hard mask 203. In this case, the sacrificial layer 204 may be formed of any one of different materials different from the second hard mask 203, more specifically, different materials having high etching selectivity with the second hard mask 203. . For example, the sacrificial film 204 is formed of an amorphous carbon film which is relatively easy to remove through a dry etching process. The sacrificial film 204 is formed to a thickness of about 1000 kPa to 2000 kPa, preferably 1500 kPa.

Subsequently, an anti-reflection layer 207 may be formed on the sacrificial layer 204. In this case, the anti-reflective layer 207 is formed of a single layer of BARC (Bottom Anti-Reflective Coating) 206, or is a DARC (Dielectric Anti-Reflective) deposited by Chemical Vapor Deposition (CVD). The coating 205 and the BARC 206 may be formed as a laminated film. Here, the CVD-DARC 205 is formed of a material having a refractive index of 1.95 and an extinction coefficient of 0.53, and the BARC 206 is formed of an organic material. For example, when the sacrificial film 204 is made of an amorphous carbon film (absorption system), the CVD-DARC 205 is formed of a silicon oxynitride film (SiON) which is an interferometer antireflection film.

Next, a photosensitive film pattern (not shown) is formed on the antireflection layer 207. In this case, the exposure process for forming the photoresist layer pattern is performed so that the 'LS' ratio of the final etched layer is 1: 3 (L: S), and 1: 2.5 to 1: 3.5 (L: S) in consideration of process variability. It is carried out within the range of).

Subsequently, as shown in FIG. 2B, the anti-reflection layer 207 (see FIG. 2A) and the sacrificial layer 204 (see FIG. 2A) are etched using the photoresist pattern. In this case, the etching process may be performed by a dry etching process or a wet etching process using the second hard mask 203 as an etching barrier layer. However, the etching process may be performed by a dry etching process to obtain a vertical profile. . For example, a dry etching process is a main etching gas O ₂ or H ₂ In order to use a gas, and to obtain a vertical profile, in addition to these main etching gases, N ₂ , COS, SO ₂ , CO, Ar used as a passivation gas, or a mixed gas of two or more kinds thereof added by adding use. As a result, the sacrificial pattern 204A is formed.

Subsequently, when the photoresist pattern and the BARC 206 (see FIG. 2A) remain on the CVD-DARC film 205A, they may be removed by an ashing process using an O ₂ plasma.

Subsequently, as shown in FIG. 2C, the CVD-DARC film 205A (see FIG. 2B) can be selectively removed. As a result, the sacrificial pattern 204A remains on the second hard mask 203.

Next, a spacer insulating film 208 is formed on the second hard mask 203 including the sacrificial pattern 204A. In this case, the spacer insulating layer 208 is formed in a liner type having a uniform thickness along the upper surface of the second hard mask 203 including the sacrificial pattern 204A, and thus a vertical profile after the subsequent etching process. to have a (vertical profile). In addition, the spacer insulating layer 208 may be formed of any one selected from materials having a high etching selectivity with the sacrificial pattern 204A and the second hard mask 203, respectively.

For example, the spacer insulating film 208 is formed of a nitride film when the sacrificial pattern 204A is formed of an amorphous carbon film and the second hard mask 203 is formed of a polycrystalline silicon film. Specifically, the silicon film is formed of a silicon film (Si _x N _y ), where x and y are natural numbers. Preferably, the silicon nitride film is formed of Si ₃ N ₄ . At this time, it is preferable that the spacer insulating film 208 is formed to have a step coverage rate of 90% or more. Here, the coverage refers to a thickness uniformity indicating a certain degree of thickness for each part of the material to be deposited. That is, the ratio of the thickness T1 deposited on the sacrificial pattern 204A (or the second hard mask 203) and the thickness T2 deposited on the sidewall of the sacrificial pattern 204A is shown. Therefore, the coverage of 90% or more means that T2 / T1 is 0.9 or more. In order to obtain such a coverage, it may be formed by an atomic layer deposition (ALD) process.

In the case where the insulating film 208 is formed of a nitride film, either a furnace type or a plasma type may be used, and the deposition temperature may be performed at 400 ° C to 1000 ° C.

Subsequently, as illustrated in FIG. 2D, an etching process using the sacrificial pattern 204A and the second hard mask 203 as an etching barrier layer is performed to form an upper surface of the sacrificial pattern 204A and the second hard mask 203. The spacer insulating film 208 (see FIG. 2C) is etched to expose it. In this case, the etching process may be performed by an anisotropic dry etching process, for example, an etch back process using a plasma etching equipment. For example, in the case where the spacer insulating film 208 is formed of a nitride film, it is etched under high power conditions so that a physical etch property is strongly applied, and CF ₄ Or use a mixed gas of CHF ₃ gas and O ₂ gas, or CH ₂ F ₂ Use gas. As a result, spacers 208A are formed on both sidewalls of the sacrificial pattern 204A.

Then, as shown in FIG. 2E, the sacrificial pattern 204A (see FIG. 2D) is selectively removed. In this case, the removing process may be performed by a wet etching process or a dry etching process using the spacer 208A and the second hard mask 203 as an etching barrier layer. For example, when the sacrificial pattern 204A is formed of an amorphous carbon film, an ashing process using an O ₂ plasma is performed.

Next, as shown in FIG. 2F, the second hard mask 203 (see FIG. 2E) is etched using the spacer 208A (see FIG. 2E) as an etching barrier layer. In this case, the etching process may be either a wet etching process or a dry etching process. For example, in the dry etching process, when the second hard mask 203 is made of a polysilicon film and the spacer 208A is made of a nitride film, Cl ₂ and BCl ₃ are used as the main etching gas in consideration of the high etching selectivity therebetween. In addition, CH ₄ , C ₂ H ₄ , SO ₂ , CO, Ar, or a mixture thereof may be further added as a passivation gas in order to prevent an asymmetric profile due to the spacer 208A.

Next, the spacer 208A is removed. For example, the spacer 208A may be removed by a wet etching process using phosphoric acid (H ₃ PO ₄ ) when the spacer 208A is formed of a nitride film. As a result, only the first hard mask pattern 203A remains on the first hard mask 202.

As such, the reason why the spacer 208A is removed is because the spacer 208A is asymmetrically formed, and when the lower layer is etched using the spacer 208A formed asymmetrically as an etch barrier layer, This is because the ion scattering angle appears asymmetrically and affects the profile of the underlying layer. In particular, when the thickness of the underlying layer to be etched is thick, the deformation of the profile of the underlying layer is further intensified. Therefore, in the exemplary embodiment of the present invention, the etching target layer 201 is not etched using the spacer 208A as the etching barrier layer, but only the second hard mask 203 formed relatively thinner than the etching target layer 201. The spacer 208A is used to be etched and then removed, and the etched layer 201 is etched using the first hard mask pattern 203A as an etch barrier layer.

Subsequently, as illustrated in FIG. 2G, the first hard mask 202 (see FIG. 2F) and the etched layer 201 (see FIG. 2F) are etched using the first hard mask pattern 203A (see FIG. 2F) as an etching mask. . In this case, the etching process may be performed in two steps by a dry etching process using the same plasma etching equipment. For example, in the first step, in order to etch the first hard mask 202 made of an oxide film, CF ₄ and CHF ₃ gas are used as the main etching gas. In the second step, O ₂ or H ₂ gas is used as the main etching gas in order to etch the etching target layer 201 made of the amorphous carbon film, and in addition, N ₂ , COS, SO ₂ , It is carried out by further adding CO, Ar or a mixed gas thereof.

Meanwhile, all of the first hard mask patterns 203A may be etched and removed during the dry etching process, but may remain at a predetermined thickness on the second hard mask patterns 202A.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, in the embodiment of the present invention, an etched layer made of an amorphous carbon film is applied, but this is for convenience of description and may be applied to all materials used in the semiconductor device, including the conductive layer. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1D are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200: semiconductor substrate 201, 201A: hard mask (etched layer)

202, 202A: First Hard Mask 203, 203A: Second Hard Mask

204: sacrificial film 204A: sacrificial pattern

205, 205A: CVD-DARC 206: BARC

207: antireflection layer 208: insulating film

208A: Spacer

Claims (19)

Forming a first hard mask using an oxide film on an etched layer made of an amorphous carbon film; Forming a second hard mask on the first hard mask by using a polysilicon film; Forming a sacrificial pattern on the second hard mask by using an amorphous carbon film; Forming a spacer on both sidewalls of the sacrificial pattern by using a nitride film; Removing the sacrificial pattern; Etching the second hard mask with the spacer as an etch barrier layer to form a first hard mask pattern; Removing the spacers; And Etching the first hard mask and the etched layer using the first hard mask pattern as an etch barrier layer; The forming of the sacrificial pattern, the forming of the first hard mask pattern, and the etching of the etched layer may be performed by adding a passivation gas to obtain a vertical profile. Method of forming a fine pattern of a semiconductor device. delete delete delete delete delete delete Claim 8 was abandoned when the registration fee was paid. The method of claim 1, Forming the spacers, Forming the nitride film along an upper surface of the second hard mask including the sacrificial pattern; And Etching back the nitride film Method of forming a fine pattern of a semiconductor device comprising a. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, The sacrificial pattern may be formed by using O ₂ or H ₂ as an etching gas, and further adding N ₂ , COS, SO ₂ , CO, Ar, or a mixed gas thereof as a passivation gas. A method of forming a fine pattern of a semiconductor device performed by the etching process. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The removing of the sacrificial pattern is a fine pattern forming method of a semiconductor device is carried out by an ashing process using an O ₂ plasma (plasma). Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, The forming of the first hard mask pattern may be performed by using Cl ₂ and BCl ₃ as an etching gas, and using a passivation gas as CH ₄ , C ₂ H ₄ , N ₂ , SO ₂ , CO, Ar, or these. A method of forming a fine pattern of a semiconductor device which is carried out by a dry etching process further adding a mixed gas mixture. Claim 12 was abandoned upon payment of a registration fee. The method of claim 1, Removing the spacer is a method of forming a fine pattern of a semiconductor device using a phosphoric acid (H ₃ PO ₄ ). Claim 13 was abandoned upon payment of a registration fee. The method of claim 1, The forming of the second hard mask pattern may be performed by a dry etching process using CF ₄ and CHF ₃ gas. Claim 14 was abandoned when the registration fee was paid. The method of claim 1, The etching of the etched layer may be performed using O ₂ or H ₂ as an etching gas, and further adding N ₂ , COS, SO ₂ , CO, Ar, or a mixed gas thereof as a passivation gas. A method of forming a fine pattern of a semiconductor device performed by the etching process. Claim 15 was abandoned upon payment of a registration fee. The method of claim 1, The etching of the second hard mask and the layer to be etched is performed in the same plasma etching apparatus. Claim 16 was abandoned upon payment of a setup registration fee. After forming the second hard mask, And forming an anti-reflection layer on the second hard mask. Claim 17 has been abandoned due to the setting registration fee. The method of claim 16, The anti-reflection layer is a fine pattern forming method of a semiconductor device formed by Bottom Anti-Reflective Coating (BARC). Claim 18 was abandoned upon payment of a set-up fee. The method of claim 16, The anti-reflection layer is a fine pattern forming method of a semiconductor device formed of a laminated structure of DARC (Dielectric Anti-Reflective Coating) and BARC (Bottom Anti-Reflective Coating). delete

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