KR101040137B1 - Thin film transistor using asymmetric electrode structure and manufacturing method thereof - Google Patents

Abstract

The thin film transistor may include a channel layer including a first surface and a second surface; A source electrode positioned at least partially at one end of the channel layer in contact with the first surface; A drain electrode positioned at least partially at the other end of the channel layer in contact with the second surface; A gate insulating layer in contact with the drain electrode; And a gate electrode in contact with the gate insulating layer. The thin film transistor may have an asymmetric staggered electrode structure having a source electrode and a drain electrode interposed between the channel layer, thereby improving electron mobility through the channel and turning off characteristics of the thin film transistor.

Description

Thin film transistor using asymmetric electrode structure and manufacturing method thereof {THIN FILM TRANSISTOR WITH ASYMMETRIC STAGGERED ELECTRODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME}

Embodiments relate to a thin film transistor having asymmetric electrode structures applied to a source electrode and a drain electrode, and a method of manufacturing the same.

A display device such as an organic light emitting diode (OLED) or a liquid crystal display (LCD) may include a thin film transistor (TFT) as a switching device. As described above, the thin film transistor is widely used as a switching device or a driving device in the electronic device field.

On the other hand, as the gate channel length of the thin film transistor is shortened, the depletion region generated in the drain electrode region and the source electrode region when the voltage is applied increases, thereby increasing the sub-threshold swing and turning off the threshold voltage. The deterioration of the turn-off characteristic due to the increase of off-current has emerged as a problem to be solved.

In addition, due to the dominant effect on the transistor performance according to the interfacial characteristics of the thin film, it appears as a factor of deterioration of reliability and driving characteristics.

In addition, since the performance of the display device using the thin film transistor varies according to the degree of switching performance of the thin film transistor, many studies have been made to improve the switching performance of the thin film transistor.

According to an aspect of the present invention, a thin film transistor having improved characteristics by applying an asymmetric staggered electrode structure, which has not been used in a conventional thin film transistor, to a source electrode and a drain electrode of the thin film transistor, and a method of manufacturing the same can be provided. have.

In one embodiment, a thin film transistor includes: a channel layer including a first surface and a second surface; A source electrode positioned at least partially at one end of the channel layer in contact with the first surface; A drain electrode positioned at least partially at the other end of the channel layer in contact with the second surface; A gate insulating layer in contact with the drain electrode; And a gate electrode in contact with the gate insulating layer.

According to one or more exemplary embodiments, a method of manufacturing a thin film transistor includes: forming a gate electrode; Forming a gate insulating film covering the gate electrode; Forming a drain electrode on the gate insulating film; Forming a channel layer on the gate insulating film and the drain electrode to partially cover the drain electrode; And forming a source electrode on the gate insulating layer and the channel layer to partially cover the channel layer.

In another embodiment, a method of manufacturing a thin film transistor includes forming a source electrode; Forming a channel layer to partially cover the source electrode; Forming a drain electrode to partially cover the channel layer; Forming a gate insulating film on the channel layer and the drain electrode to partially cover the drain electrode; And forming a gate electrode on the gate insulating layer.

In the above-described methods of manufacturing the thin film transistor, both ends of the channel layer may contact the source electrode and the drain electrode, respectively.

According to an aspect of the present invention, the source electrode and the drain electrode of the thin film transistor are formed in an asymmetric electrode structure with the channel layer interposed therebetween, thereby forming a channel between the surface of the channel and the channel and the gate insulating film when the channel is formed in the on-state. Not disturbed by the interfacial properties of the channel can be formed in a low resistance state.

In addition, the drain electrode may be disposed between the channel layer and the gate insulating layer to prevent the channel characteristic from being degraded due to the bulk effect, and the electron mobility through the channel may be improved.

In addition, a strong electric field is formed between the source electrode and the drain electrode under the influence of the interface and the surface of the channel, and the drain electrode from which the electrons escape from the channel can be formed on the same plane as the channel, thereby turning the thin film transistor. Turn-off characteristics can be improved.

According to the thin film transistor, it is possible to obtain a high efficiency compared to the prior art by using a device of the same area, and / or it is possible to manufacture a device having the same performance by miniaturization compared to the prior art.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A is a perspective view illustrating a thin film transistor according to an exemplary embodiment. FIG. 1A illustrates a thin film transistor of a bottom gate type in which the gate electrode 11 is located under the entire structure.

Referring to FIG. 1A, the thin film transistor may include a gate electrode 11, a gate insulating layer 12, a channel layer 13, a source electrode 14a, and a drain electrode 14b. The shape of each component shown in FIG. 1A is exemplary, and in other embodiments, each component of the thin film transistor may be a shape different from that shown in FIG. 1A.

The gate electrode 11 may be located on the substrate 100. The substrate 100 may comprise silicon (Si), glass, plastic or other suitable material. The gate electrode 11 may also be made of metal or other suitable conductive material. For example, the gate electrode 11 may be formed of indium tin oxide (ITO), gallium zinc oxide (GZO), indium gallium zinc oxide (IGZO), and indium gallium oxide (Indium Gallium). It may include any one selected from the group consisting of Oxide (IGO), Indium Zinc Oxide (IZO), and Indium Oxide (In ₂ O ₃ ), or a combination of two or more thereof.

In another embodiment, the substrate 100 may serve as a gate electrode as a back gate without using a separate gate electrode 11. In this case, the substrate 100 may be made of doped silicon (Si) or a silicon compound. For example, the substrate 100 may be made of a poly-silicon-based material.

The gate insulating layer 12 may be positioned on the gate electrode 11. The gate insulating layer 12 includes silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), and barium. Strontium-titanium-oxygen compound (Ba-Sr-Ti-O), bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) and any other selected from the group consisting of other suitable materials Combinations of two or more may be included.

The source electrode 14a, the channel layer 13, and the drain electrode 14b may be positioned on the gate insulating layer 12. The source electrode 14a and the drain electrode 14b may be formed in an asymmetric staggered electrode structure positioned opposite to each other with the channel layer 13 therebetween. This is described in detail with reference to FIG. 1B below.

FIG. 1B is a perspective view illustrating only the channel layer 13 in the thin film transistor of FIG. 1A. Referring to FIG. 1B, the channel layer 13 may include a first surface 131 and a second surface 132. In the present specification, the first surface 131 and the second surface 132 are intended to refer to surfaces that are opposite to each other among the surfaces of the channel layer 13, and do not necessarily mean flat surfaces, but partially recessed or Even when the protruding region or the step is formed, the entire surface in the corresponding direction, including the same, is referred to as the first surface 131 or the second surface 132.

1A and 1B, the first surface 131 may be an upper surface of the channel layer 13, and the second surface 132 may be a lower surface of the channel layer 13. The source electrode 14a may be at least partially in contact with the first surface 131, and the drain electrode 14b may be at least partially in contact with the second surface 132. In addition, the source electrode 14a may be positioned at one end of the channel layer 13 in contact with the first surface 131, and the drain electrode 14b may be in contact with the second surface 132. It can be located at the other end of 13). The source electrode 14a and the drain electrode 14b may be positioned not to contact each other.

In one embodiment, the first region 1000 in contact with the first surface 131 and the source electrode 14a and the second region 2000 in contact with the second surface 132 and the drain electrode 14b may be in contact with each other. It may be located so as not to face each other. That is, when the thin film transistor is viewed from a direction perpendicular to the surface of the channel layer 13, the source electrode 14a and the channel layer (not to overlap the first region 1000 and the second region 2000) do not overlap each other. 13) and the drain electrode 14b may be disposed.

The channel layer 13 may be positioned to partially cover the drain electrode 14b on the gate insulating layer 12 and the drain electrode 14b. At this time, a part of the drain electrode 14b should be exposed without being covered by the channel layer 13 for external connection when driving the thin film transistor later. The source electrode 14a may be positioned to partially cover the channel layer 13 on the gate insulating layer 12 and the channel layer 13. The drain electrode 14b may be at least partially positioned between the gate insulating layer 12 and the channel layer 13.

The channel layer 13 includes aluminum (Al), boron (B), gallium (Ga), indium (In), titanium (Ti), tin (Sn), zirconium (Zr), hafnium (Hf), and fluorine (F). It may comprise any one selected from the group consisting of or a combination of two or more thereof and zinc (Zn).

In addition, the channel layer 13 may be formed of an oxide including the materials listed above, or may be formed of an oxide semiconductor. The oxide semiconductor may have a relatively high electron mobility of about 10 cm ² / Vs or more even when amorphous. For example, channel layer 13 may include mixed oxides or other suitable oxides such as ZnO, IZO, IGO, GZO, IGZO, titanium zinc oxide (TiZnO), aluminum zinc oxide (AlZnO), or boron zinc oxide (BZnO), or the like. Can be done.

The source electrode 14a and the drain electrode 14b may comprise a metal or other suitable conductive material. The source electrode 14a and the drain electrode 14b may be made of the same material or may be made of different materials.

For example, the source electrode 14a and the drain electrode 14b may include one or a combination of two or more selected from the group consisting of ITO, GZO, IGZO, IGO, IZO, and In ₂ O ₃ . Alternatively, the source electrode 14a and the drain electrode 14b may include titanium (Ti), indium (In), aluminum (Al), gallium (Ga), gold (Au), tin oxide (SnO _x ), and silver (Ag). And a metal or an oxide containing zinc (Zn) and any one or a combination of two or more selected from the group consisting of platinum (Pt).

In the thin film transistor configured as described above, when a voltage is applied to the gate electrode 11 to form a channel in the channel layer 13, the drain electrode 14b is positioned between the channel layer 13 and the gate insulating layer 12, thereby bulking. The carrier path may be easily formed because it is not affected by the bulk effect, and electron mobility through the channel layer 13 may be improved.

In addition, a strong electric field may be formed between the source electrode 14a and the drain electrode 14b arranged in an asymmetric electrode structure, and the drain electrode 14b through which electrons escape and the channel are located on the same plane to form a thin film transistor. Turn-off characteristics can be improved.

Therefore, in the thin film transistor according to the above-described embodiment, the source electrode 14a and the drain electrode 14 are formed on the same plane as the channel layer 13, or the drain electrode 14b is a channel even in a multilayer structure. Compared with the conventional thin film transistor that is not disposed between the layer 13 and the gate insulating film 12, it has improved driving characteristics.

2A to 2E are perspective views illustrating each step of a method of manufacturing a thin film transistor, according to an exemplary embodiment.

Referring to FIG. 2A, a gate electrode 11 may be formed on the substrate 100. For example, the gate electrode 11 may be formed by depositing a thin film made of a conductive material on the substrate 100 and partially removing it using a photolithography process or a lift-off process. It may be. On the other hand, in another embodiment, the substrate 100 itself may operate as a back gate without a separate gate electrode 11.

Referring to FIG. 2B, a gate insulating film 12 may be formed on the substrate 100 on which the gate electrode 11 is formed. For example, the gate insulating film 12 may be formed by sputtering. The gate insulating layer 12 may be positioned to completely cover the gate electrode 11.

Referring to FIG. 2C, a drain electrode 14b may be formed on the gate insulating layer 12. The drain electrode 14b may be a chemical vapor deposition method such as physical vapor deposition such as RF sputter, E-beam evaporation, thermal chemical vapor deposition, or other. It can be formed by forming a thin film of conductive material by a suitable method and partially removing it by a photolithography process or a liftoff process.

Referring to FIG. 2D, the channel layer 13 may be formed on the gate insulating layer 12 and the drain electrode 14b. The channel layer 13 may be formed to partially cover the drain electrode 14b. A portion of the drain electrode 14b may be exposed without being covered by the channel layer 13 for external connection when driving the thin film transistor later. The channel layer 13 may be formed by various physical vapor deposition methods, chemical vapor deposition methods or other suitable methods.

Referring to FIG. 2E, the source electrode 14a may be formed on the gate insulating layer 12 and the channel layer 13. The source electrode 14a may be formed to partially cover the channel layer 13 and not to contact the drain electrode 14b. Since the formation process of the source electrode 14a may be the same as the formation process of the drain electrode 14b mentioned above, detailed description is abbreviate | omitted.

In this case, the source electrode 14a may be formed such that the source electrode 14a and the drain electrode 14b are positioned at both ends of the channel layer 13, respectively. As a result, the source electrode 14a and the drain electrode 14b may be formed in an asymmetrical structure which is located on the upper and lower portions of the channel layer 13, respectively, and located at opposite ends of the channel layer 13, respectively. .

In an exemplary embodiment, the first region 1000 in contact with the channel layer 13 and the source electrode 14a and the second region 2000 in contact with the drain electrode 14b of the channel layer 13 may not face each other. Can be located. That is, when viewed from a direction perpendicular to the surface of the channel layer 13, the drain electrode 14b, the channel layer 13, and the first region 1000 and the second region 2000 do not overlap each other. The source electrode 14a may be formed.

In the method of manufacturing the thin film transistor described above, at least one of the gate electrode 11, the gate insulating film 12, the channel layer 13, the source electrode 14a, and the drain electrode 14b may be formed by sputtering. have. However, this is merely an example, and the manufacturing process is not limited to sputtering, and other suitable physical vapor deposition or chemical vapor deposition may be used.

In the method of manufacturing the thin film transistor described above, the constituent materials constituting the gate electrode 11, the gate insulating film 12, the channel layer 13, the source electrode 14a, and the drain electrode 14b are illustrated in FIG. Since the thin film transistor according to the exemplary embodiment described above with reference to 1a and 1b may be the same as a material of a corresponding component, a detailed description thereof will be omitted.

3A is a perspective view illustrating a thin film transistor according to another exemplary embodiment. 3A illustrates a top gate thin film transistor in which a gate electrode 24 is disposed.

Referring to FIG. 3A, the thin film transistor may include a channel layer 21, a source electrode 22a, a drain electrode 22b, a gate insulating layer 23, and a gate electrode 24. The shape of each component illustrated in FIG. 3A is exemplary, and in another embodiment, each component of the thin film transistor may have a shape different from that illustrated in FIG. 3A.

The channel layer 21, the source electrode 22a, and the drain electrode 22b may be positioned on the substrate 200. In this case, the substrate 200 may include silicon (Si), glass, plastic, or another suitable material. The channel layer 21 is a layer for forming a channel through which electrons move between the source electrode 22a and the drain electrode 22b. The source electrode 22a and the drain electrode 22b may be formed in an asymmetric electrode structure positioned opposite to each other with the channel layer 21 therebetween. This will be described in detail with reference to FIG. 3B below.

3B is a perspective view illustrating only the channel layer 21 in the thin film transistor of FIG. 3A. 3A and 3B, the channel layer 21 may include a first surface 211 and a second surface 212 positioned opposite to each other. For example, the first surface 211 may be a lower surface of the channel layer 21, and the second surface 212 may be an upper surface of the channel layer 21.

The source electrode 22a may be at least partially in contact with the first surface 211, and the drain electrode 22b may be at least partially in contact with the second surface 212. In addition, the source electrode 22a may be positioned at one end of the channel layer 21 in contact with the first surface 211, and the drain electrode 22b may be in contact with the second surface 212. It may be located at the other end of (21). The source electrode 22a and the drain electrode 22b may be positioned not to contact each other.

In an embodiment, the first region 1000 in contact with the first surface 211 and the source electrode 22a and the second region 2000 in contact with the second surface 212 and the drain electrode 22b may be in contact with each other. It may be located so that it does not face each other. That is, when the above-described thin film transistor is viewed from above, the source electrode 22a, the drain electrode 22b, and the channel layer 21 may be disposed so that the first region 1000 and the second region 2000 do not overlap each other. have.

The channel layer 21 may be positioned on the substrate 200 to partially cover the source electrode 22a. At this time, a part of the source electrode 22a should be exposed without being covered by the channel layer 21 for external connection when the thin film transistor is driven later. Meanwhile, the drain electrode 22b may be positioned on the channel layer 21 and the substrate 200 to partially cover the channel layer 21.

The gate insulating layer 23 may be positioned to partially cover the drain electrode 22b on the channel layer 21 and the drain electrode 22b. In addition, the drain electrode 22b may be at least partially positioned between the channel layer 21 and the gate insulating layer 23. At this time, a part of the drain electrode 22b should be exposed without being covered by the gate insulating film 23 for external connection when the thin film transistor is driven later. The gate electrode 24 may be positioned on the gate insulating layer 23.

In the embodiment shown in FIGS. 3A and 3B, the constituent materials constituting each of the channel layer 21, the source electrode 22a, the drain electrode 22b, the gate insulating film 23, and the gate electrode 24 are shown in FIG. Since the thin film transistor according to the exemplary embodiment described above with reference to 1a and 1b may be the same as a material of a corresponding component, a detailed description thereof will be omitted.

The thin film transistor according to the exemplary embodiment described above represents a thin film transistor in which the asymmetric electrode structures of the source electrode 22a and the drain electrode 22b according to the present invention are applied to the upper gate method. Like the lower gate type thin film transistor described above with reference to FIGS. 1A and 1B, the thin film transistor prevents a decrease in channel characteristics due to a bulk effect, thereby increasing electron mobility through a channel, and a turn-off characteristic of the thin film transistor. There is an advantage that can be improved.

4A to 4E are perspective views illustrating respective steps of a method of manufacturing a thin film transistor according to another embodiment.

Referring to FIG. 4A, a source electrode 22a may be formed on the substrate 200. The source electrode 22a forms a thin film made of a conductive material by physical vapor deposition such as RF sputtering, pulse laser deposition, etc., chemical vapor deposition such as thermochemical vapor deposition, or other suitable method, and is used in a photolithography process or a lift-off process. By partially removing it.

Referring to FIG. 4B, the channel layer 21 may be formed on the substrate 200 on which the source electrode 22a is formed. The channel layer 21 may be formed to partially cover the source electrode 22a. In this case, a portion of the source electrode 22a may be exposed without being covered by the channel layer 21 for external connection when the thin film transistor is driven later. The channel layer 21 may be formed by physical vapor deposition, chemical vapor deposition, or other suitable method.

Referring to FIG. 4C, the drain electrode 22b may be formed on the substrate 200 on which the source electrode 22a and the channel layer 21 are formed. The drain electrode 22b may be formed to partially cover the channel layer 21 and not to contact the source electrode 22a. In this case, the drain electrode 22b may be formed at an end opposite to the end where the channel layer 21 contacts the source electrode 22a. As a result, the source electrode 22a and the drain electrode 22b may be formed in an asymmetric electrode structure, which is located at the lower and upper portions of the channel layer 21, respectively, and located at opposite ends of the channel layer 21, respectively. have.

Referring to FIG. 4D, the gate insulating layer 23 may be formed on the substrate 200 on which the source electrode 22a, the channel layer 21, and the drain electrode 22b are formed. The gate insulating layer 23 may be formed to partially cover the drain electrode 22b on the channel layer 21 and the drain electrode 22b. In this case, a part of the drain electrode 22b may be exposed without being covered by the gate insulating layer 23 so that external connection may be possible when the thin film transistor is driven later.

Referring to FIG. 4E, the gate electrode 24 may be formed on the gate insulating layer 23. For example, the gate electrode 24 may be formed by depositing a thin film of conductive material on the gate insulating film 23 and partially removing it by a photolithography process or a liftoff process.

In the above-described method of manufacturing a thin film transistor, at least one of the channel layer 21, the source electrode 22a, the drain electrode 22b, the gate insulating film 23, and the gate electrode 24 may be formed using sputtering. It may be. However, this is merely an example, and the manufacturing process is not limited to sputtering, and other suitable physical vapor deposition or chemical vapor deposition may be used.

In the method of manufacturing the thin film transistor described above, the material constituting each of the channel layer 21, the source electrode 22a, the drain electrode 22b, the gate insulating film 23, and the gate electrode 24 is illustrated in FIG. 1A. And since it may be the same as the constituent material of the corresponding component of the thin film transistor according to the above-described embodiment with reference to FIG. 1B a detailed description thereof will be omitted.

The embodiments described above have been described by the thin film transistor according to any one of the upper gate method and the lower gate method, but this is merely an example, and the thin film transistor and the method of manufacturing the same according to the embodiments are specific types and / or It is not limited in a way. In addition, the shape of the components of the thin film transistor and / or the relative sizes therebetween shown in the accompanying drawings of the present specification are shown by way of example only for understanding of the present invention, the configuration of the thin film transistor according to the embodiments The shape of the elements and / or the relative sizes between them may be different from that shown in the figures.

5 is a graph illustrating a current according to a gate voltage in a thin film transistor according to an exemplary embodiment in comparison with a thin film transistor according to the related art.

In FIG. 5, the graph 510 shows current characteristics of a thin film transistor having a channel structure including a top electrode of an amorphous IGZO according to the related art. Meanwhile, the graph 520 illustrates a current characteristic of the thin film transistor having a drain electrode disposed between the gate insulating layer and the channel layer, and the source electrode having an electrode structure formed at an asymmetrical position with the drain electrode on the opposite surface of the channel layer, according to an exemplary embodiment. Indicates.

As can be seen from FIG. 5, the thin film transistor according to the embodiment has excellent current-voltage characteristics compared to the thin film transistors according to the prior art. For example, when the gate voltage is negative in the graph 520, the current magnitude is smaller than that in the graph 510 corresponding to the conventional thin film transistor, which indicates that the thin film transistor has excellent turn-off characteristics. Indicates.

6 is a graph illustrating output curves according to drain voltages in a channel layer of a thin film transistor according to an exemplary embodiment.

Each of the graphs 610, 620, 630, and 640 of FIG. 6 shows currents of channels according to drain voltages when the gate voltages of the thin film transistors according to the exemplary embodiment are 16, 24, 32, and 40 V, respectively. As shown, it can be seen that as the drain voltage increases, the current is well saturated and the current magnitude is large, thereby improving driving characteristics of the thin film transistor.

Although the present invention described above has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and variations may be made therefrom. However, such modifications should be considered to be within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1A is a perspective view of a thin film transistor according to an exemplary embodiment.

FIG. 1B is a perspective view of a channel layer in the thin film transistor of FIG. 1A.

2A to 2E are perspective views illustrating each step of a method of manufacturing a thin film transistor, according to an exemplary embodiment.

3A is a perspective view of a thin film transistor according to another embodiment.

3B is a perspective view of a channel layer in the thin film transistor of FIG. 3A.

4A to 4E are perspective views illustrating respective steps of a method of manufacturing a thin film transistor according to another embodiment.

5 is a graph illustrating a current according to a gate voltage in a thin film transistor according to an exemplary embodiment in comparison with a thin film transistor according to the related art.

6 is a graph illustrating output characteristics according to drain voltages in a channel layer of a thin film transistor according to an exemplary embodiment.

Claims (4)

A channel layer comprising a first side and a second side; A source electrode positioned at least partially at one end of the channel layer in contact with the first surface; A drain electrode positioned at least partially at the other end of the channel layer in contact with the second surface; A gate insulating layer in contact with the drain electrode; And A gate electrode in contact with the gate insulating film, And the gate insulating layer is disposed under the channel layer and contacts the source electrode, the second surface of the channel layer, and the drain electrode. The method of claim 1, The first region in which the source electrode and the first surface contact each other, and the second region in which the drain electrode and the second surface contact each other do not face each other. delete Forming a source electrode; Forming a channel layer to partially cover the source electrode; Forming a drain electrode to partially cover the channel layer; Forming a gate insulating film on the channel layer and the drain electrode to partially cover the drain electrode; And Forming a gate electrode on the gate insulating film, Both end portions of the channel layer are in contact with the source electrode and the drain electrode, respectively.

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