KR101088062B1 - Stacked printed circuit board with bumps and manufacturing method - Google Patents

Abstract

The present invention, the step of forming at least one inner layer on both sides of the removable carrier; Removing the separated carrier to separate the inner layer into a separated inner layer group; And patterning a photosensitive material on the outer surface of the separated inner layer group to form an outermost base layer in which bumps are formed by a plating method. 2. do.

According to the present invention, a high reliability printed circuit board having low signal resistance between upper and lower layers can be manufactured by applying bumps and stacking insulating layers to the formation of inner layers and outermost layers in stacking multilayer substrates. have.

Printed Circuit Boards, Bumps, Plating

Description

Stacked printed circuit board with bumps and manufacturing method {A BUILD-UP PRINTED CIRCUIT BOARD OF STACK TYPE USING BUMP STRUCTURE AND MANUFACTURING METHOD OF THE SAME}

The present invention relates to a method for manufacturing a printed circuit board implemented in a multi-layer and a printed circuit board manufactured accordingly.

Printed CirCuit Board (PCB) is a printed circuit board pattern formed of a conductive material such as copper on an electrically insulating substrate, and refers to a board immediately before mounting an electronic component. That is, it means a circuit board in which a mounting position of each component is determined and a circuit pattern for connecting the components is printed and fixed on the surface of the flat plate in order to mount a large number of various electronic components on the flat plate. Such printed circuit boards generally include a single-layer PCB and a build-up board in which multilayers of PCBs are formed, that is, multilayer PCB substrates.

These build-up boards and multi-layer PCB boards can be manufactured one by one, and the quality of the multi-layer PCB boards can be increased, and the interlayer wiring can be precisely connected to produce high-density miniature PCBs. Let's do it.

This build-up process leads to the formation of interconnecting lines between the layers and via via holes between the layers. In order to form such a via hole, a very small diameter can be realized by using a laser rather than a conventional mechanical drill operation.

Specifically, the method of forming the via holes of the build-up substrate is implemented by a stack via method in which vias are stacked on the vias, and the formation of the stack vias facilitates a circuit design of a printed circuit board and a circuit. The length of wiring can be shortened to improve the electrical operation ability, and the circuit density can be increased, which is considered to be a very important core technology in multilayer PCB fabrication. In order to form the stack via, it is necessary to align the via holes very precisely, and also requires the circuit line width and the fine design standards of the via holes, which are required for the high density, thus causing difficulty in processing.

To form such stack vias, laser drilling techniques have been used to process via holes in insulating materials constituting each layer of a printed circuit board, and to fill the via holes with metallic paste. Thereafter, when the copper metal foil is laminated on the surface of the insulating material by a hot press method and a circuit is formed by a patterning method using a photoresist, one layer is completed. After forming each layer in this manner, finely aligning their positions, and again lamination using a hot press to form a build-up substrate.

1 is a cross-sectional view of a buildup substrate manufactured according to the prior art. Referring to FIG. 1, a circuit is generally formed by filling copper plating or conductive paste after mechanical hole processing in order to connect different interlayer circuits in multilayer PCB fabrication. In addition, in the case of hole processing, after the hole is formed using a mechanical drill or a laser drill method, the falling hole 20 is formed using a copper plating filling technique. In particular, when the via hole is large and it is difficult to fill with copper plating, a filling method using a conductive paste is used.

Here, in the case of the via hole formed by a mechanical drill, multiple layers may be stacked at the same time and a via hole may be formed. However, in the case of processing a fine via hole, a laser drill used for only one panel can be worked at a time, so the work time for forming the via hole is considerably longer. Takes

 In particular, the electrical transmission signal of the via hole by the conductive paste contains noise. In other words, it has a large electrical resistance and is not suitable for application in a high reliability product range.

The present invention has been made to solve the above-described problem, the object of the present invention in the manufacture of a build-up printed circuit board, by implementing the inner layer and the outermost layer through continuous lamination to shorten the manufacturing process and at the same time interlayer adhesion To provide a printed circuit board with a highly reliable stack via to improve the performance and minimize the resistance of the signal transmission.

The present invention is a means for solving the above problems, one step of forming at least one inner layer on both sides of the removable carrier; Removing the separated carrier to separate the inner layer into a separated inner layer group; To provide a stack-type printed circuit board manufacturing method having a bump, comprising the step of forming an outermost base layer with bumps formed by plating a photosensitive material on the outer shell of the separated inner layer group. It is possible to implement a high reliability product with low signal resistance between the upper and lower layers.

In particular, the specificity of the manufacturing process according to the detachable carrier used in the above-described manufacturing process will appear. As an example, the detachable carrier of the first step may use a structure in which a Cu layer is bonded to both sides of a copper foil composite by a bonding film. have. In this case, in constructing the first step, 1a) forming a base layer by forming a primary bump on the split carrier and stacking an insulating layer; 1b) forming a secondary bump pad and a secondary bump on the base layer. In addition, in step 1a), the photosensitive material may be patterned, and the first bump may be implemented by plating. In particular, step 1b) may include forming a secondary bump pad by forming and patterning one or more surface treatment layers on the insulating layer; 1b-2) It is preferable to form the inner layer forming step of forming a secondary bump on the secondary bump pad and stacking an insulating layer to include a step of repeating one or more times.

In particular, the step 1b-1) in the above-described manufacturing process of the present invention, the surface treatment layer may be formed of alloy deposition layer, Cu deposition layer, Cu plating layer, the alloy deposition layer, Ni, Cr, It can be formed as a single layer or multilayer structure layer made of a material selected from Au, Ag, Pb, and Pd.

In step 1b-2) of the above-described manufacturing process, the photosensitive material may be patterned, and the second bump may be embodied by a plating method. After the second bump is plated, mechanical or chemical polishing may be performed and the photosensitive material may be used. The process of peeling off may be further performed.

In any case, it is preferable that the manufacturing process according to the present invention as described above can perform simultaneous operation with two separate inner layer groups by removing the detachable carrier so as to enhance the efficiency of the process.

After the separation of the removable carrier, the third step may include: 3a) forming an outermost bump pad by forming and patterning at least one surface treatment layer on the removable inner layer group; 3b) forming an outermost bump on the outermost bump pad and laminating an insulating layer to form an outermost base layer; And 3c) forming a circuit pattern on the outermost base layer.

According to the manufacturing process according to the present invention described above, it is possible to manufacture a printed circuit board having the following structure.

Specifically, the printed circuit board manufactured by the present invention includes one or more inner layers having bumps inside the insulating clarification layer and connected to each layer; An outermost base layer formed on the inner shell and connected to the inner layer by bumps formed by plating a photosensitive material; And a circuit pattern formed on the outermost base layer.

Here, at least one of the connection portions of the bumps connecting the inside of the stacked printed circuit board may include a bump pad.

In addition, the inner layer is a base layer having a primary bump in the insulating layer; A one or more secondary inner layers formed on the base layer and having a secondary bump pad and a secondary bump connected to the primary bumps in an insulating layer, the bumps and the secondary inside the outermost base layer; The outermost bump pad is preferably formed between the bumps.

In addition, the bumps inside the primary, secondary, and outermost base layers may have a rectangular or square shape in cross section, and the secondary bump pads and the outermost bump pads may include:

It is preferable that it is formed in the laminated structure of an alloy deposition layer, a Cu deposition layer, and a Cu plating layer. In this case, the alloy deposition layer may be formed of a single layer or a multilayer structure consisting of a material selected from Ni, Cr, Au, Ag, Pb.

According to the present invention, a highly reliable printed circuit board having low signal resistance between upper and lower layers can be manufactured by applying bumps and stacking insulating layers to the formation of inner layers and outermost layers in stacking multilayer substrates. have.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation according to the present invention. In the description with reference to the accompanying drawings, the same components will be denoted by the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

According to the present invention, in manufacturing a stacked printed circuit board having bumps, two printed circuit boards can be simultaneously manufactured using a separate carrier, and in particular, the manufacturing of an inner layer and an outermost layer to be connected to a bump structure therein. Make a point.

2a to 2c schematically show a flowchart and a process diagram of the manufacturing process of the preferred embodiment according to the present invention.

Example

The present invention is largely the first step to form one or more inner layer on both sides of the removable carrier and the second step of separating the inner layer into a separate inner layer group by removing the removable carrier, and patterning the photosensitive material on the outer shell of the separated inner layer group It comprises three steps to form the outermost base layer in which bumps are formed by a plating method. In this case, the one or more inner layers and the outermost layers are connected between the layers via bumps.

(1) step 1-separate carrier + inner layer forming step;

In the first step, the first bump 120 is first formed through plating on the detachable carrier C1. (S1-S2). The detachable carrier (C1) has a structure in which the copper foil layer (Cu) is bonded to the copper foil composite body 110 (a structure in which the copper foil (a) is coated on both surfaces of the insulator (b)) via the double-sided bonding film 111. desirable. This serves to facilitate the fairness of the thin product in the future, and at the same time to be able to produce both sides of the product at the same time to achieve the effect of improving the productivity of the process. The double-sided bonding film 111 may be formed on the outer portion of the upper and lower surfaces of the copper foil composite 110, and then form a Cu layer through lamination. Subsequently, in the separation process of the second step, the double-sided bonding film 111 may be removed and separated. In addition, portions other than the portion on which the double-sided bonding film 111 is formed are preferably formed in a structure in which the space between the upper and lower surfaces of the copper foil composite 110 and the copper foil layer is finely spaced or adhered to each other.

The formation of the first bump 120 may be realized by implementing a pattern by exposure and development using a dry film resist (DFR) 122 and then filling a metal material into the pattern using electrolytic plating. (S3). Of course, before peeling the DFR 122 after plating, a process of chemical or mechanical polishing may be added for height control of the appropriate bumps.

Next, after forming the first bump 120, the insulating layer 121 is laminated (S4). An insulating layer having the primary bumps 120 is defined as a 'base layer'.

Specifically, when the primary bumps 120 are formed by plating, the DFR 122 is peeled off, the prepreg sheet and the copper thin film layer are laminated, and then pressed by heat and pressure, and then the copper thin film layer is pressed. It can be implemented by etching to remove. In this case, the copper thin film layer serves to facilitate the flow and spreadability of the resin during the pressing process due to heat and pressure. Of course, even in this case, after removing the copper thin film layer, it is possible to implement the appropriate bump height by performing mechanical or chemical polishing to make the height of the bumps constant.

After step S4, in step S5 to form an inner circuit layer (0.1 ~ 50㎛), that is, a surface treatment layer on the base layer to form a secondary bump pad. The surface treatment layer forms an alloy deposition layer 131, a Cu deposition layer 132, and a Cu plating layer 133 on the base layer. After lamination, the second bump pad 130 is patterned by applying a DFR and forming a pattern. The secondary bump pad forms a secondary bump 140 and at the same time implements an inner layer circuit. The alloy deposition layer 131 may be formed of an alloy of two or more metals selected from Ni, Cr, Au, Ag, Pb, and Pd. In one example, the alloy deposition layer 131 to deposit an alloy of Ni, Cr, thereby improving the adhesion between the Cu plating layer 133 and the epoxy layer laminated first. The alloy deposition layer 131 is preferably formed in 0.05 ~ 0.1㎛. In addition, the Cu deposition layer 132 serves to improve the adhesion between the alloy deposition layer 131 described above and the Cu plating layer 133 to be formed in the future.

In step S6, after applying and patterning the DFR on the Cu plating layer 133, which is the innermost circuit layer of the secondary bump pad 130, by the same method as the method of forming the first bump, the second bump 140 is plated. ), And then mechanical and chemical polishing can be performed before the DFR is peeled off.

Thereafter, an insulating layer 141 is stacked on the secondary bumps 140. Lamination of the insulating layer is the same as the method of step S4. In the present invention, the layer of the structure in which the secondary bump pad 130, the secondary bump 140, and the insulating layer 141 are formed is defined as a 'secondary inner layer'. In the present invention, the secondary inner layer structure may be formed at least one or more.

(2) forming a separate-separable inner layer group of a detachable carrier

Thereafter, as in step S8, the detachable carrier C1 is removed to separate the structures formed on the upper and lower surfaces of the detachable carrier (each separated structure is defined as a detachable inner layer group) and simultaneously work on two separate inner layer groups. The PCB manufacturing process is carried out at the same time. In the figure, the process will be described with only one separate inner layer group.

The above separation process is to cut the use section of the double-sided bonding film of the detachable carrier so that the product can be separated through the internal non-bonded portion.

(3) Formation of outermost base layer with bumps formed by plating method

The separate inner layer group is provided with the same structure, by preparing one of them (S9) will be described after the process. Surface treatment is performed on both surfaces of the separate inner layer group to form an outermost bump pad 150 (S10). The process of forming the outermost bump pad 150 is performed in the same process as the process of step S5. Similarly, the structure of the alloy deposition layer 151, the Cu deposition layer 152, and the Cu plating layer 153 is provided. As shown, the Cu 112 layer of the initial detachable carrier is also formed into a patterned structure while patterning the outermost bump pad 150 together.

In step S11, the outermost bump 170 is formed on the outermost bump pad 150 and the insulating layer 154 is stacked. This process is the same as the process of S6 and S7 mentioned above. Here, the layer including the outermost bump pad 150, the outermost bump 170, and the insulating layer 154 thereon is defined as an 'outermost base layer'.

Then, in step S12, the circuit pattern 155 is formed on the outermost base layer. Although the circuit pattern of a single layer is shown in the figure, a circuit pattern composed of multiple layers may be implemented using the same process as in the above-described steps S5 and S10. Thereafter, in step S13, the surface circuit protection layer 160 may be further formed on the circuit pattern 155. The surface circuit protection layer 160 may be formed of one or more layers using one or more of SR (Solder Resist), oxide, and Au.

Referring to Figure 3 will be described the structure of a printed circuit board manufactured by the manufacturing process according to the present invention.

The printed circuit board of the present invention includes one or more inner layers having bumps inside the insulating material layer and connected to each layer, and formed on the inner surface of the inner layer and connected to the inner layers by bumps formed by plating a photosensitive material. It may have a structure including an outermost base layer and a circuit pattern formed on the outermost base layer.

In particular, as shown, the printed circuit board manufactured by the manufacturing process according to an embodiment of the present invention, the secondary bumps on the top of the base layer including the primary bump 120 and the insulating layer 121 At least one or more secondary inner layers formed of the bump pads 130, the secondary bumps 140, and the insulating layer 141 may be formed and stacked. The bump pad 130 may be formed in a triple structure of the alloy deposition layer 131, the Cu deposition layer 132, and the Cu plating layer 133 as described above.

In addition, in the above-described structure, the outermost base layer formed of the outermost bump pad 150, the outermost bump 170, and the insulating layer 154 is formed on the outer shell of the laminated structure of the secondary inner layer and the outer shell of the base layer. Can be. In particular, a Cu layer may be further formed at an adjacent boundary between the outermost bump pad 150 and the primary bump 120 formed on the outer surface of the base layer. In addition, at least one of the bump pads 130 and 150 formed between the primary bumps 120 and the secondary bumps 140 and between the secondary bumps 140 and the outermost bumps 170 may be formed of an alloy deposition layer, Cu. It may be implemented in a triple structure of a deposition layer, a Cu plating layer. In particular, an alloy of at least two or more metals selected from Ni, Cr, Au, Ag, Pb, and Pd may be used as the material for forming the alloy deposition layer.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical spirit of the present invention should not be limited to the described embodiments of the present invention, but should be determined not only by the claims, but also by those equivalent to the claims.

1 is a cross-sectional view of a build-up substrate manufactured according to the prior art

2a to 2c is a flow chart and process diagram of the manufacturing process of the preferred embodiment according to the present invention

3 is a cross-sectional view showing the structure of a printed circuit board manufactured by the method of manufacturing a stacked printed circuit board of the present invention.

Description of the Related Art [0002]

110: copper foil composite 111: double-sided bonding film

120: primary bump 122: DFR

121, 141, 154: insulation layer 131, 151: alloy deposition layer

132, 152: Cu deposition layer 133, 153: Cu plating layer

130: 2nd bump pad 140: 2nd bump

150: outermost bump pad 170: outermost bump pad

160: surface circuit protection layer

Claims (17)

Forming at least one inner layer on both sides of the separate carrier having a structure in which a Cu layer is bonded to both sides of the copper foil composite by a bonding film; Separating the inner layer into a separated inner layer group by removing the bonding film constituting the separated carrier; And Patterning a photosensitive material on an outer surface of the separated inner layer group to form an outermost base layer having bumps formed by a plating method; Including, The third step, 3a) forming and patterning at least one surface treatment layer on the separate inner layer group to form an outermost bump pad; 3b) forming an outermost bump on the outermost bump pad and stacking an insulating layer to form an outermost base layer; 3c) forming a circuit pattern on the outermost base layer. delete The method of claim 1, wherein the first step is 1a) forming a primary bump on the split carrier and stacking an insulating layer to form a base layer; 1b) forming a secondary bump pad and a secondary bump on the base layer. The method of claim 3, The step 1a), the step of patterning the photosensitive material, a method of manufacturing a stacked printed circuit board having a bump, characterized in that to implement a primary bump by plating. The method of claim 3, Step 1b), 1b-1) forming a second bump pad by forming and patterning one or more surface treatment layers on the insulating layer; 1b-2) a stack-type printed circuit having bumps, wherein the inner layer forming step of forming a secondary bump on the secondary bump pad and stacking an insulating layer is repeated one or more times. Substrate manufacturing method. The method of claim 5, Step 1b-1), The method of manufacturing a stacked printed circuit board having bumps, wherein the surface treatment layer is formed of an alloy deposition layer, a Cu deposition layer, and a Cu plating layer. The method of claim 6, The alloy deposition layer, A method for manufacturing a stacked printed circuit board with bumps, characterized in that it is formed of a single layer or a multilayer structure of a layer consisting of a material selected from Ni, Cr, Au, Ag, Pb, and Pd. The method of claim 5, The step 1b-2), the step of patterning the photosensitive material, and the stack-type printed circuit board manufacturing method having a bump, characterized in that to implement a secondary bump by plating. The method of claim 8, Method of manufacturing a stacked printed circuit board with bumps after plating the secondary bumps, performing mechanical or chemical polishing, and peeling the photosensitive material. delete delete At least one inner layer including a base layer having a primary bump in an insulating layer, a secondary bump pad formed on the base layer and connected to the primary bump, and at least one secondary inner layer having a secondary bump; An outermost base layer formed on the inner shell and connected to the inner layer by bumps formed by plating a photosensitive material; An outermost bump pad formed between the bump inside the outermost base layer and the secondary bumps; A circuit pattern formed on the outermost base layer; Including, At least one of the secondary bump pad and the outermost bump pad may include: Stacked printed circuit board with bumps, characterized in that formed in a laminated structure of an alloy deposition layer, Cu deposition layer, Cu plating layer. delete delete The method of claim 12, And the bumps inside the first bump, the second bump, and the outermost base layer have a rectangular or square shape in cross section. delete The method of claim 12, The alloy deposition layer, Stacked printed circuit board with bumps, characterized in that formed in a single layer or a multilayer structure consisting of a material selected from Ni, Cr, Au, Ag, Pb.

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