KR101099560B1 - High voltage transistor manufacturing method - Google Patents

Abstract

The present invention discloses a method of manufacturing a high voltage transistor for improving breakdown voltage BVdss and off current Ioff characteristics. The disclosed method includes providing a semiconductor substrate equipped with a high voltage well; Selectively implanting impurities into the surface of the semiconductor substrate, and then performing a thermal diffusion process to form respective drift regions; Forming a field oxide film on the semiconductor substrate, the field oxide film defining a device region; Forming a gate electrode pattern on the substrate between the drift regions; Selectively forming an oxide film on drift regions under both sides of the gate electrode pattern; Forming spacers on both sidewalls of the gate electrode pattern; And selectively implanting high concentration impurities into the resulting substrate surface to form source / drain regions.

Description

High voltage transistor manufacturing method {METHOD FOR MANUFACTURING HIGH VOLTAGE TRANSISTOR}

1A to 1C are cross-sectional views illustrating processes for manufacturing a high voltage transistor according to the related art.

2A through 2D are cross-sectional views of processes for describing a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

30 semiconductor substrate 31 photosensitive film pattern

32: drift region 33: field oxide film

34: gate oxide film 35: gate polysilicon film

36: gate electrode pattern 37: oxide film

38: spacer 39, 40: source / drain region

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a high voltage transistor for improving breakdown voltage (BVdss) and off current (Ioff) characteristics.

Typical high voltage transistors are source / drain regions doped with high concentrations of impurities and drift doped with low concentrations of impurities to improve the avalanche junction breakdown voltage. A (Drift) region is formed to use a double diffused drain (DDD) junction structure.

On the other hand, the drift region increases the junction breakdown voltage due to electric field concentration by dispersing an electric field by forming a junction depth deep.

A conventional method of manufacturing a high voltage transistor using a double diffused drain (DDD) junction structure will be briefly described with reference to FIGS. 1A to 1C.

1A to 1C are cross-sectional views of processes for explaining a conventional method of manufacturing a high voltage transistor.

A conventional high voltage transistor manufacturing method, as shown in FIG. 1A, first provides a semiconductor substrate 10 provided with a high voltage well (not shown). Then, a photoresist pattern 11 defining a drift forming region (not shown) is formed on the semiconductor substrate 10. Subsequently, an ion is implanted into the entire surface of the semiconductor substrate 10 using the photoresist pattern 11 as an ion implantation mask, and then a thermal diffusion process is performed to diffuse the impurity into the surface of the semiconductor substrate 10. Each drift region 12 is formed.

Next, as shown in FIG. 1B, after removing the photoresist pattern, a field oxide film (not shown) defining a device region (not shown) is formed on the semiconductor substrate 10 by a LOCOS (Local Oxidation of Silicon) process. 13). Then, the gate oxide film 14 and the gate polysilicon film 15 are sequentially formed on the resultant.

Subsequently, as illustrated in FIG. 1C, the gate polysilicon layer 15 and the gate oxide layer 14 may be selectively etched to form a gate electrode pattern 16 on the substrate 10 between the drift regions 12. Form.

Next, spacers 17 are formed on both sidewalls of the gate electrode pattern 16. Thereafter, a high concentration of impurities are selectively implanted into the surface of the resulting semiconductor substrate 10 to form source / drain regions 18 and 19 in the drift region 12.

However, in the related art, since the drift region is formed directly on the substrates on both sides of the gate electrode pattern, the series resistance becomes small, resulting in a problem that the breakdown voltage BVdss and the off current Ioff characteristics are deteriorated.

Accordingly, the present invention has been made to solve the above problems, and the high voltage transistor can be prevented from deteriorating the breakdown voltage and off current characteristics due to the drift region is formed directly on the substrate on both sides of the gate electrode pattern. The purpose is to provide a method.

In the method of manufacturing a high voltage transistor according to an embodiment of the present invention for achieving the above object, the step of providing a semiconductor substrate provided with a high voltage well, after ion implantation selectively into the surface of the semiconductor substrate, a thermal diffusion process Forming respective drift regions, forming a field oxide film defining a device region on the semiconductor substrate, forming a gate electrode pattern on the substrate between the drift regions, and both sides of the gate electrode pattern. Selectively forming an oxide film by performing an O2 ion implantation process on a lower drift region, forming a spacer on both sidewalls of the gate electrode pattern, and selectively implanting a high concentration of impurities into the surface of the semiconductor substrate to To form source / drain regions spaced apart It includes the system.

Here, the oxide film is formed on one side of the drift region adjacent to the gate electrode pattern or on the middle side of the drift region.

According to the present invention, an oxide film is selectively formed in a predetermined portion of the drift region to increase the series resistance, thereby reducing the bias applied to the actual channel, thereby reducing the breakdown voltage BVdss and the off current ( Ioff) characteristics can be improved.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating processes of manufacturing a high voltage transistor according to an exemplary embodiment of the present invention.

In the method of manufacturing a high voltage transistor according to an exemplary embodiment of the present invention, as shown in FIG. 2A, first, a semiconductor substrate 30 having a high voltage well (not shown) is provided. Next, a photosensitive film pattern 31 defining a drift forming area (not shown) is formed on the semiconductor substrate 30.

Subsequently, an ion is implanted into the entire surface of the semiconductor substrate 30 using the photoresist pattern 31 as an ion implantation mask, and then a thermal diffusion process is performed to diffuse the impurities into the surface of the semiconductor substrate 30. The drift region 32 is formed.

Then, as shown in FIG. 2B, after removing the photoresist pattern, the field oxide layer 33 is subjected to a local oxide of silicon (LOCOS) process to isolate a device in a predetermined region of the semiconductor substrate 30. To form. Then, a gate oxide film 34 and a gate polysilicon film 35 are sequentially formed on the resultant.

Subsequently, as shown in FIG. 2C, the gate polysilicon layer 35 and the gate oxide layer 34 are selectively etched to form the gate electrode pattern 36 on the substrate 30 between the drift regions 32. Form.

Next, an oxide film 37 is formed by selectively performing an O 2 ion implantation process on the drift regions 32 below both sides of the gate electrode pattern 36. In this case, the oxide layer 37 is formed on one side of the drift region 32 adjacent to the gate electrode pattern 36 or on the middle side of the drift region 32.

Here, the oxide layer 37 increases the series resistance. When the bias voltage is applied to the drain, the oxide layer 37 is applied to the resistance increased by the oxide layer 37 in the actual channel. The breakdown voltage BVdss and the off current Ioff characteristics are improved because the bias is applied by decreasing the applied voltage. That is, the oxide layer 37 serves to improve the breakdown voltage BVdss and the off current Ioff by applying a relatively low bias to the actual channel.

Then, as illustrated in FIG. 2D, spacers 38 are formed on both sidewalls of the gate electrode pattern 36. Thereafter, a high concentration of impurities are selectively implanted into the surface of the resultant semiconductor substrate 30 to form source / drain regions 39 and 40 in the drift region 32.

As described above, in manufacturing the high voltage transistor, the series resistance is increased by selectively forming an oxide film through an O 2 ion implantation process in a predetermined portion in the drift region formed on both lower sides of the gate electrode pattern, As a result, the breakdown voltage BVdss and the off current Ioff may be improved by reducing the bias applied to the actual channel.

Claims (4)

Providing a semiconductor substrate with a high voltage well; Selectively implanting impurities into the surface of the semiconductor substrate, and then performing a thermal diffusion process to form respective drift regions; Forming a field oxide film on the semiconductor substrate, the field oxide film defining a device region; Forming a gate electrode pattern on the substrate between the drift regions; Selectively forming an oxide film by performing an O2 ion implantation process on drift regions under both sides of the gate electrode pattern; Forming spacers on both sidewalls of the gate electrode pattern; And And selectively implanting a high concentration of impurities into a surface of the semiconductor substrate to form a source / drain region spaced apart from the oxide film at a predetermined interval. delete The method of claim 1, wherein the oxide layer is formed on one side of the drift region adjacent to the gate electrode pattern. The method of claim 1, wherein the oxide film is formed at an intermediate side of the drift region.

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