KR101116729B1

KR101116729B1 - Semiconductor memory device

Info

Publication number: KR101116729B1
Application number: KR1020100017332A
Authority: KR
Inventors: 이종원; 추신호
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-02-25
Filing date: 2010-02-25
Publication date: 2012-02-22
Anticipated expiration: 2030-02-25
Also published as: KR20110097472A

Abstract

반도체 메모리 장치는 제1 어드레스신호그룹을 버퍼링하여 제1 내부어드레스신호그룹으로 출력하는 제1 입력부와 노멀모드신호에 따라 데이터마스크신호를 버퍼링하여 내부데이터마스크신호로 출력하고, 테스트모드신호에 따라 제2 어드레스신호그룹을 버퍼링하여 제2 내부어드레스신호그룹으로 출력하는 제2 입력부 및 상기 노멀모드신호에 따라 데이터스트로브신호를 버퍼링하여 내부데이터스트로브신호로 출력하고, 상기 테스트모드신호에 따라 제3 어드레스신호그룹을 버퍼링하여 제3 내부어드레스신호그룹으로 출력하는 제3 입력부를 포함한다.The semiconductor memory device buffers the first address signal group and outputs the data mask signal as an internal data mask signal according to the first mode and the normal mode signal to output the first internal address signal group. A second input unit for buffering an address signal group and outputting the second internal address signal group and a data strobe signal according to the normal mode signal and outputting the buffered data strobe signal as an internal data strobe signal, and a third address signal according to the test mode signal And a third input unit configured to buffer the group and output the buffered group to the third internal address signal group.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

본 발명은 반도체 메모리 장치에 관한 것이다. The present invention relates to a semiconductor memory device.

기존의 DRAM은 용량을 증가시키는 방향으로 개량되었으나, 현재의 DRAM은 저전력 동작 및 처리속도를 향상시키는 방향으로 개량되고 있다. 그 결과물로서 개발된 장치가 LP(Low Power)DDR2이다. 이름에서 알 수 있듯이, LPDDR2는 기존의 DRAM과 비교하여 저전력으로 동작하며, 처리속도 또한 매우 빠르다.Conventional DRAMs have been retrofitted to increase capacity, but current DRAMs have been retrofitted to improve low power operation and throughput. The resulting device was LP (Low Power) DDR2. As the name suggests, LPDDR2 operates at lower power than conventional DRAM, and the processing speed is very fast.

기존의 DRAM과 LPDDR2는 외부로부터 커맨드 및 어드레스신호를 입력받는 방식 또한 차이가 있다. 기존의 DRAM은 클록의 라이징시점(rising edge)에 동기하여 복수의 커맨드 및 어드레스를를 입력받는 반면, LPDDR2는 클록의 라이징시점에는 커맨드를 입력받고, 폴링시점(failing edge)에는 어드레스신호를 입력받는다. 따라서, LPDDR2는 하나의 패드를 통해 2개의 신호를 입력받을 수 있기 때문에, 기존의 DRAM보다 적은 패드 수로 설계된다.Conventional DRAM and LPDDR2 also have a different way of receiving command and address signals from the outside. Conventional DRAMs receive a plurality of commands and addresses in synchronization with a rising edge of the clock, while the LPDDR2 receives a command at the rising edge of the clock and an address signal at the falling edge. Therefore, since the LPDDR2 can receive two signals through one pad, the LPDDR2 is designed with a lower pad count than conventional DRAM.

한편, 기존의 DRAM 및 LPDDR2는 별도의 테스트 동작을 통해 데이터 처리능력이 테스트된다. 특히, LPDDR2는 저전력으로 동작하기 때문에 데이터가 손실되거나 오동작할 확률이 높기 때문에, LPDDR2의 테스트는 더욱 정밀하게 진행되어야 한다.
Meanwhile, conventional DRAM and LPDDR2 are tested for data throughput through separate test operations. In particular, since LPDDR2 operates at low power, there is a high probability of data loss or malfunction, so the LPDDR2 testing needs to be performed more precisely.

본 발명은 기존 DRAM용 테스트 장비에서 LPDDR2를 테스트하는 기술을 개시한다.The present invention discloses a technique for testing LPDDR2 in an existing DRAM test equipment.

이를 위해, 본 발명은 제1 어드레스신호그룹을 버퍼링하여 제1 내부어드레스신호그룹으로 출력하는 제1 입력부와 노멀모드신호에 따라 데이터마스크신호를 버퍼링하여 내부데이터마스크신호로 출력하고, 테스트모드신호에 따라 제2 어드레스신호그룹을 버퍼링하여 제2 내부어드레스신호그룹으로 출력하는 제2 입력부 및 상기 노멀모드신호에 따라 데이터스트로브신호를 버퍼링하여 내부데이터스트로브신호로 출력하고, 상기 테스트모드신호에 따라 제3 어드레스신호그룹을 버퍼링하여 제3 내부어드레스신호그룹으로 출력하는 제3 입력부를 포함하는 반도체 메모리 장치를 제공한다.To this end, the present invention buffers the data mask signal in accordance with the first input unit and the normal mode signal buffering the first address signal group and outputs the signal to the first internal address signal group, and outputs the internal data mask signal to the test mode signal. The second input unit buffers the second address signal group to output the second internal address signal group, and buffers the data strobe signal according to the normal mode signal and outputs the internal data strobe signal according to the test mode signal. A semiconductor memory device including a third input unit configured to buffer an address signal group and output the buffered address signal group as a third internal address signal group.

또한, 본 발명은 제1 어드레스신호그룹을 버퍼링하여 제1 내부어드레스신호그룹으로 출력하는 제1 입력부와 노멀모드신호에 따라 데이터마스크신호를 버퍼링하여 내부데이터마스크신호로 출력하고, 테스트모드신호에 따라 제2 어드레스신호그룹을 버퍼링하여 제2 내부어드레스신호그룹으로 출력하는 제2 입력부와 상기 노멀모드신호에 따라 데이터스트로브신호를 버퍼링하여 내부데이터스트로브신호로 출력하고, 상기 테스트모드신호에 따라 제3 어드레스신호그룹을 버퍼링하여 제3 내부어드레스신호그룹으로 출력하는 제3 입력부 및 상기 제1 내지 제3 어드레스신호그룹을 디코딩하여 내부커맨드 및 내부어드레스신호로 출력하는 디코딩부를 포함하는 반도체 메모리 장치를 제공한다.
In addition, the present invention buffers the data mask signal according to the first input unit and the normal mode signal buffering the first address signal group and outputs the first internal address signal group, and outputs the internal data mask signal according to the test mode signal. A second input unit buffering the second address signal group and outputting the second internal address signal group and the data strobe signal according to the normal mode signal and outputting the buffered data strobe signal as an internal data strobe signal, and a third address according to the test mode signal. A semiconductor memory device includes a third input unit buffering a signal group and outputting the signal to a third internal address signal group, and a decoding unit decoding the first to third address signal groups and outputting the internal command and the internal address signal.

도 1은 본 발명의 일 실시예에 따른 반도체 메모리 장치를 나타낸 블록도이다.
도 2는 도 1에 도시된 커맨드어드레스신호 입력부를 나타낸 블록도이다.
도 3은 도 2에 도시된 제1 버퍼부를 나타낸 회로도이다.
도 4는 도 1에 도시된 데이터마스크신호 입력부를 나타낸 블록도이다.
도 5는 도 4에 도시된 제11 버퍼부를 나타낸 블록도이다.
도 6은 도 5에 도시된 제2 버퍼를 나타낸 회로도이다.
도 7은 도 1에 도시된 데이터스트로브신호 입력부를 나타낸 블록도이다.
도 8은 도 7에 도시된 제15 버퍼부를 나타낸 블록도이다.
도 9는 도 8에 도시된 제22 버퍼부를 나타낸 회로도이다.
도 10은 도 1에 도시된 칩선택신호 입력부를 나타낸 회로도이다.
도 11은 도 1에 도시된 디코딩부를 나타낸 블록도이다.1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a command address signal input unit shown in FIG. 1.
3 is a circuit diagram illustrating the first buffer unit illustrated in FIG. 2.
FIG. 4 is a block diagram illustrating a data mask signal input unit shown in FIG. 1.
FIG. 5 is a block diagram illustrating an eleventh buffer unit illustrated in FIG. 4.
FIG. 6 is a circuit diagram illustrating a second buffer shown in FIG. 5.
FIG. 7 is a block diagram illustrating a data strobe signal input unit shown in FIG. 1.
FIG. 8 is a block diagram illustrating a fifteenth buffer unit illustrated in FIG. 7.
FIG. 9 is a circuit diagram illustrating a twenty-second buffer unit illustrated in FIG. 8.
FIG. 10 is a circuit diagram illustrating a chip select signal input unit illustrated in FIG. 1.
FIG. 11 is a block diagram illustrating a decoding unit illustrated in FIG. 1.

이하, 실시예를 통하여 본 발명을 더욱 상세히 설명하기로 한다. 이들 실시예는 단지 본 발명을 예시하기 위한 것이며, 본 발명의 권리 보호 범위가 이들 실시예에 의해 제한되는 것은 아니다.Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

도 1은 본 발명의 일 실시예에 따른 반도체 메모리 장치를 나타낸 블록도이다.1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

도 1에 도시된 바와 같이, 반도체 메모리 장치는 커맨드어드레스신호 입력부(1)와 데이터마스크신호 입력부(2)와 데이터스트로브신호 입력부(3)와 칩선택신호 입력부(4)와 클록인에이블신호 입력부(5)와 클록 입력부(6) 및 디코딩부(7)로 구성된다.As shown in FIG. 1, the semiconductor memory device includes a command address signal input unit 1, a data mask signal input unit 2, a data strobe signal input unit 3, a chip select signal input unit 4, and a clock enable signal input unit ( 5) and a clock input section 6 and a decoding section 7.

커맨드어드레스신호 입력부(1)는, 도 2에 도시된 바와 같이, 제1 내지 제10 버퍼부(11~20)로 구성된다.As shown in FIG. 2, the command address signal input unit 1 includes first to tenth buffer units 11 to 20.

제1 버퍼부(11)는, 도 3에 도시된 바와 같이, 테스트모드신호(TM) 및 노멀모드신호(NM)를 부정논리곱하여 제1 인에이블신호(EN1)로 출력하는 제1 인에이블신호 생성부(111)와 제1 인에이블신호(EN1)에 응답하여 제1 패드(PAD1)에 실린 제1 커맨드어드레스신호(CA<1>)를 제1 전치 내부커맨드어드레스신호(PRECA<1>)로 전달하기 위한 신호전달부로 동작하는 제1 전달게이트(T1)와 제1 전치 내부커맨드어드레스신호(PRECA<1>)를 버퍼링하여 제1 내부커맨드어드레스신호(ICA1<1>)로 출력하는 제1 버퍼(112)로 구성된다. 제1 인에이블신호 생성부(111)는 제1 낸드게이트(ND1)로 구현된다. 여기서, 테스트모드신호(TM)는 반도체 메모리 장치가 테스트모드에 진입하기 위해 인에이블되는 신호이고, 노멀모드신호(NM)는 반도체 메모리 장치가 정상동작모드에 진입하기 위해 인에이블되는 신호이다. 테스트모드신호(TM)와 노멀모드신호(NM)는 동일한 인에이블구간을 갖지 않는다.As shown in FIG. 3, the first buffer unit 11 negatively multiplies the test mode signal TM and the normal mode signal NM, and outputs the first enable signal EN1 as a first enable signal EN1. In response to the generation unit 111 and the first enable signal EN1, the first command address signal CA <1> loaded on the first pad PAD1 is transferred to the first pre-internal command address signal PRECA <1>. A first buffering signal of the first transfer gate T1 and the first pre-internal command address signal PRECA <1>, which operate as a signal transfer unit for transmitting the signal to a first internal command address signal ICA1 <1> It consists of a buffer 112. The first enable signal generator 111 is implemented as a first NAND gate ND1. Here, the test mode signal TM is a signal that enables the semiconductor memory device to enter the test mode, and the normal mode signal NM is a signal that enables the semiconductor memory device to enter the normal operation mode. The test mode signal TM and the normal mode signal NM do not have the same enable period.

이와 같은 구성의 제1 버퍼부(11)는 테스트모드신호(TM)가 인에이블되거나 노멀모드신호(NM)가 인에이블되면, 제1 커맨드어드레스신호(CA<1>)를 버퍼링하여 제1 내부커맨드어드레스신호(ICA<1>)로 출력한다. 나머지, 제2 내지 제10 버퍼부(12~20)도 제1 버퍼부(11)와 동일한 구성으로 설계되어, 테스트모드신호(TM)와 노멀모드신호(NM)에 따라 제2 내지 제10 패드(PAD2~PAD10)에 실린 제2 내지 제10 커맨드어드레스신호(CA<2:10>)를 제2 내지 제10 내부커맨드어드레스신호(ICA<2:10>)로 출력한다.When the test mode signal TM is enabled or the normal mode signal NM is enabled, the first buffer unit 11 having the above configuration buffers the first command address signal CA <1> to the first internal portion. Output as command address signal ICA <1>. The second to tenth buffer units 12 to 20 are also designed in the same configuration as the first buffer unit 11, and according to the test mode signal TM and the normal mode signal NM, the second to tenth pads may be used. The second to tenth command address signals CA <2:10> loaded on the PAD2 to PAD10 are output as the second to tenth internal command address signals ICA <2:10>.

데이터마스크신호 입력부(2)는, 도 4에 도시된 바와 같이, 제11 내지 제14 버퍼부(21~24)로 구성된다.As illustrated in FIG. 4, the data mask signal input unit 2 includes the eleventh to fourteenth buffer units 21 to 24.

제11 버퍼부(21)는, 도 5에 도시된 바와 같이, 제1 신호출력부(211) 및 제2 신호출력부(212)로 구성된다.As illustrated in FIG. 5, the eleventh buffer unit 21 includes a first signal output unit 211 and a second signal output unit 212.

제1 신호출력부(211)는 테스트모드신호(TM)가 인에이블되면 제11 패드(PAD11)에 실린 제11 커맨드어드레스신호(CA<11>)를 제11 전치 내부커맨드어드레스신호(PRECA<11>)로 전달하기 위한 신호전달부로 동작하는 제2 전달게이트(T2)와 테스트모드신호(TM)와 노멀모드신호(NM)를 입력받아 제2 인에이블신호(EN2)로 출력하는 제2 인에이블신호 생성부(213)와 제2 인에이블신호(EN2)에 따라 제11 전치 내부커맨드어드레스신호(PRECA<11>)를 버퍼링하여 제11 내부커맨드어드레스신호(ICA<11>)로 출력하는 제2 버퍼(214)로 구성된다. 제2 인에이블신호 생성부(213)는 노멀모드신호(NM)와 테스트모드신호(TM)를 입력받는 제2 낸드게이트(ND2)와 제2 낸드게이트(ND2)의 출력을 반전하여 제2 인에이블신호(EN2)로 출력하는 제1 인버터(IN1)로 구성된다. 제2 버퍼(214)는, 도 6에 도시된 바와 같이, 제2 인에이블신호(EN2)의 인에이블 구간 내에서 제11 전치 내부커맨드어드레스신호(PRECA<11>)의 레벨에 따라 제11 내부커맨드어드레스신호(ICA<11>)로 출력하는 차동증폭기로 구성된다.When the test mode signal TM is enabled, the first signal output unit 211 outputs the eleventh command address signal CA <11> loaded on the eleventh pad PAD11 to the eleventh pre-internal command address signal PRECA <11. A second enable that receives a second transfer gate T2, a test mode signal TM, and a normal mode signal NM, which operate as a signal transfer unit for transferring to >) and outputs the second enable signal EN2 as a second enable signal EN2. A second buffering of the eleventh pre-internal command address signal PRECA <11> according to the signal generator 213 and the second enable signal EN2 and outputting the eleventh internal command address signal ICA <11>. It consists of a buffer 214. The second enable signal generator 213 inverts the outputs of the second NAND gate ND2 and the second NAND gate ND2 that receive the normal mode signal NM and the test mode signal TM, thereby inducing the second enable signal. The first inverter IN1 outputs the enable signal EN2. As illustrated in FIG. 6, the second buffer 214 may include an eleventh internal portion according to the level of the eleventh pre-internal command address signal PRECA <11> within the enable period of the second enable signal EN2. A differential amplifier outputs the command address signal ICA <11>.

제2 신호출력부(212)는 노멀모드신호(NM)가 인에이블되면 제11 패드(PAD11)에 실린 제1 데이터마스크신호(미도시)를 제1 전치 내부데이터마스크신호(PREDM<1>)로 전달하기 위한 신호전달부로 동작하는 제3 전달게이트(T3)와 테스트모드신호(TM)와 노멀모드신호(NM)에 응답하여 제3 인에이블신호(EN3)로 출력하는 제3 인에이블신호 생성부(215)와 제3 인에이블신호(EN3)에 따라 제1 전치 내부데이터마스크신호(PREDM<1>)를 버퍼링하여 제1 내부데이터마스크신호(IDM<1>)로 출력하는 제3 버퍼(216)로 구성된다. 제3 인에이블신호 생성부(215)는 테스트모드신호(TM)를 반전하는 제2 인버터(IN2)와 노멀모드신호(NM)와 제2 인버터(IN2)의 출력을 입력받는 제3 낸드게이트(ND3)와 제3 낸드게이트(ND3)의 출력을 반전하여 제3 인에이블신호(EN3)로 출력하는 제3 인버터(IN3)로 구성된다. 제3 단위버퍼(216)는 제2 단위버퍼(214)와 동일한 구성으로 설계된다. 여기서, 제1 데이터마스크신호는 외부로부터 입력되는 복수의 데이터 중, 특정 데이터만 추출하기 위한 신호이다. 예를 들어, 4개의 데이터가 순차적으로 입력되는 상태에서 두 번째 입력되는 데이터를 추출하고자 한다면, 제1 데이터마스크신호는 두 번째 데이터가 입력되는 시점에 인에이블되어 두 번째 데이터를 추출한다.When the normal mode signal NM is enabled, the second signal output unit 212 may output the first data mask signal (not shown) carried on the eleventh pad PAD11 to the first pre-internal data mask signal PREDM <1>. Generation of the third enable signal outputting the third enable signal EN3 in response to the third transfer gate T3, the test mode signal TM, and the normal mode signal NM, which operate as a signal transfer unit for transmitting to A third buffer for buffering the first pre-internal data mask signal PREDM <1> and outputting it as a first internal data mask signal IDM <1> according to the unit 215 and the third enable signal EN3. 216). The third enable signal generator 215 may include a third NAND gate that receives an output of the second inverter IN2, the normal mode signal NM, and the second inverter IN2 that inverts the test mode signal TM. And a third inverter IN3 that inverts the outputs of the ND3 and the third NAND gate ND3 and outputs the third enable signal EN3. The third unit buffer 216 is designed in the same configuration as the second unit buffer 214. Here, the first data mask signal is a signal for extracting only specific data among a plurality of data input from the outside. For example, if the second data is to be extracted while four data are sequentially input, the first data mask signal is enabled at the time when the second data is input and the second data is extracted.

이와 같은 구성의 데이터마스크신호 입력부(2)는 테스트모드신호(TM)가 인에이블되면 제11 패드(PAD11)에 실린 제11 커맨드어드레스신호(CA<11>)를 버퍼링하여 제11 내부커맨드어드레스신호(ICA<11>)로 출력한다. 또한, 데이터마스크신호 입력부(2)는 노멀모드신호(NM)가 인에이블되면 제11 패드(PAD11)에 실린 제1 데이터마스크신호를 버퍼링하여 제1 내부데이터마스크신호로 출력한다.The data mask signal input unit 2 having the above configuration buffers the eleventh command address signal CA <11> loaded on the eleventh pad PAD11 when the test mode signal TM is enabled, and the eleventh internal command address signal. Output to (ICA <11>). In addition, when the normal mode signal NM is enabled, the data mask signal input unit 2 buffers the first data mask signal loaded on the eleventh pad PAD11 and outputs the first internal data mask signal.

데이터스트로브신호 입력부(3)는, 도 7에 도시된 바와 같이, 제15 내지 제21 버퍼부(31~38)로 구성된다.As illustrated in FIG. 7, the data strobe signal input unit 3 includes the fifteenth to twenty first buffer units 31 to 38.

제15 버퍼부(31)는, 도 8에 도시된 바와 같이, 제3 신호출력부(311) 및 제4 신호출력부(312)로 구성된다.As shown in FIG. 8, the fifteenth buffer unit 31 includes a third signal output unit 311 and a fourth signal output unit 312.

제3 신호출력부(311)는 테스트모드신호(TM)가 인에이블되면 제15 패드(PAD15)에 실린 제15 커맨드어드레스신호(CA<15>)를 제15 전치 내부커맨드어드레스신호(PRECA<15>)로 전달하기 위한 신호전달부로 동작하는 제4 전달게이트(T4)와 테스트모드신호(TM)와 노멀모드신호(NM)를 입력받아 제4 인에이블신호(EN4)로 출력하는 제4 인에이블신호 생성부(313)와 제4 인에이블신호(EN4)에 따라 제15 전치 내부커맨드어드레스신호(PRECA<15>)를 버퍼링하여 제15 내부커맨드어드레스신호(ICA<15>)로 출력하는 제4 단위버퍼(314)로 구성된다. 제4 인에이블신호 생성부(313)는 노멀모드신호(NM)와 테스트모드신호(TM)를 입력받는 제4 낸드게이트(ND4)와 제4 낸드게이트(ND4)의 출력을 반전하여 제4 인에이블신호(EN4)로 출력하는 제4 인버터(IN4)로 구성된다. 제4 단위버퍼(314)는 도 6에 도시된 제2 단위버퍼(214)와 동일한 구성으로 설계된다.The third signal output unit 311 transmits the fifteenth command address signal CA <15> carried on the fifteenth pad PAD15 when the test mode signal TM is enabled, and the fifteenth pre-internal command address signal PRECA <15. A fourth enable that receives the fourth transfer gate T4, the test mode signal TM, and the normal mode signal NM, which operate as a signal transfer unit for transferring the signal>) and outputs the fourth enable signal EN4 as a fourth enable signal EN4. A fourth buffering buffer for the fifteenth pre- internal command address signal PRECA <15> according to the signal generator 313 and the fourth enable signal EN4 and outputting the fifteenth internal command address signal ICA <15>. It is composed of a unit buffer 314. The fourth enable signal generator 313 inverts the outputs of the fourth NAND gate ND4 and the fourth NAND gate ND4, which receive the normal mode signal NM and the test mode signal TM, thereby inverting the outputs of the fourth NAND gate ND4. The fourth inverter IN4 outputs the enable signal EN4. The fourth unit buffer 314 is designed in the same configuration as the second unit buffer 214 shown in FIG. 6.

제4 신호출력부(312)는 노멀모드신호(NM)가 인에이블되면 제15 패드(PAD15)에 실린 제1 데이터스트로브신호(미도시)를 제1 전치 내부데이터스트로브신호(PREDQS<1>)로 전달하기 위한 신호전달부로 동작하는 제4 전달게이트(T4)와 테스트모드신호(TM)와 노멀모드신호(NM)에 응답하여 제4 인에이블신호(EN4)로 출력하는 제4 인에이블신호 생성부(315)와 제4 인에이블신호(EN4)에 따라 제1 전치 내부데이터스트로브신호(PREDQS<1>)를 버퍼링하여 제1 내부데이터스트로브신호(IDQS<1>)로 출력하는 제4 단위버퍼(316)로 구성된다. 제4 인에이블신호 생성부(315)는 테스트모드신호(TM)를 반전하는 제5 인버터(IN5)와 노멀모드신호(NM)와 제5 인버터(IN5)의 출력을 입력받는 제5 낸드게이트(ND5)와 제5 낸드게이트(ND5)의 출력을 반전하여 제4 인에이블신호(EN4)로 출력하는 제6 인버터(IN6)로 구성된다. 제4 단위버퍼(316)는 도 6에 도시된 제2 단위버퍼(214)와 동일한 구성으로 설계된다. 여기서, 제1 데이터스트로브신호는 외부에서 입력되는 데이터를 동기화시키기 위한 신호이다. When the normal mode signal NM is enabled, the fourth signal output unit 312 may output the first data strobe signal (not shown) carried on the fifteenth pad PAD15 to the first pre-internal data strobe signal PREDQS <1>. Generation of the fourth enable signal outputting the fourth enable signal EN4 in response to the fourth transfer gate T4 and the test mode signal TM and the normal mode signal NM, which operate as a signal transfer unit for transmitting to A fourth unit buffer for buffering the first pre-internal data strobe signal PREDQS <1> and outputting the first internal data strobe signal IDQS <1> according to the unit 315 and the fourth enable signal EN4. 316. The fourth enable signal generator 315 may include a fifth NAND gate that receives an output of the fifth inverter IN5, the normal mode signal NM, and the fifth inverter IN5 that inverts the test mode signal TM. And a sixth inverter IN6 that inverts the outputs of the ND5 and the fifth NAND gate ND5 and outputs the fourth enable signal EN4. The fourth unit buffer 316 is designed in the same configuration as the second unit buffer 214 shown in FIG. 6. Here, the first data strobe signal is a signal for synchronizing data input from the outside.

이와 같은 구성의 제15 버퍼부(31)는 테스트모드신호(TM)가 인에이블되면 제15 패드(PAD15)에 실린 제15 커맨드어드레스신호(CA<15>)를 버퍼링하여 제15 내부커맨드어드레스신호(ICA<15>)로 출력한다. 또한, 제15 버퍼부(3)는 노멀모드신호(NM)가 인에이블되면 제15 패드(PAD15)에 실린 제1 데이터스트로브신호를 버퍼링하여 제1 내부데이터스트로브신호(IDQS<8>)로 출력한다. 나머지 제16 내지 제21 버퍼부(32~37)도 제15 버퍼부(31)와 동일한 구성으로 설계되어, 테스트모드신호(TM)가 인에이블되면 제16~21 패드(PAD16~PAD21)에 실린 제15 내지 제21 커맨드어드레스신호(CA<15:21>)를 제16~21 내부커맨드어드레스신호(ICA<16:21>)로 출력한다. 또한, 제2 내지 제7 단위 데이터스트로브신호 입력부(32~37)는 노멀모드신호(NM)가 인에이블되면 제16~21 패드(PAD16~PAD21)에 실린 제2 내지 제7 데이터스트로브신호를 제2 내지 제7 내부데이터스트로브신호로 출력한다.When the test mode signal TM is enabled, the fifteenth buffer unit 31 having the above configuration buffers the fifteenth command address signal CA <15> carried on the fifteenth pad PAD15, and thus the fifteenth internal command address signal. Output to (ICA <15>). In addition, when the normal mode signal NM is enabled, the fifteenth buffer unit 3 buffers the first data strobe signal loaded on the fifteenth pad PAD15 and outputs the first internal data strobe signal IDQS <8>. do. The remaining sixteenth to twenty-first buffer units 32 to 37 are also designed in the same configuration as the fifteenth buffer unit 31, and when the test mode signal TM is enabled, the sixteenth to twenty-first pads PAD16 to PAD21 are loaded. The 15th to 21st command address signals CA <15:21> are output as the 16th to 21st internal command address signals ICA <16:21>. Also, when the normal mode signal NM is enabled, the second to seventh unit data strobe signal input units 32 to 37 may output the second to seventh data strobe signals loaded on the 16 th to 21 th pads PAD16 to PAD21. Outputs the second to seventh internal data strobe signals.

제22 버퍼부(38)는, 도 9에 도시된 바와 같이, 제6 인에이블신호 생성부(381) 및 제5 버퍼(382)로 구성된다.As illustrated in FIG. 9, the twenty-second buffer unit 38 includes a sixth enable signal generator 381 and a fifth buffer 382.

제6 인에이블신호 생성부(381)는 테스트모드신호(TM)와 노멀모드신호(NM)를 입력받아 제6 인에이블신호(EN6)로 출력하는 제6 낸드게이트(ND6)로 구성된다. 제5 단위버퍼(382)는 제6 인에이블신호(EN6)에 따라 제8 데이터스트로브신호(DQS<8>)를 버퍼링하여 제8 내부데이터스트로브신호(IDQS<8>)로 출력하는 차동증폭기로 구성된다.The sixth enable signal generator 381 includes a sixth NAND gate ND6 that receives the test mode signal TM and the normal mode signal NM and outputs the sixth enable signal EN6. The fifth unit buffer 382 is a differential amplifier that buffers the eighth data strobe signal DQS <8> and outputs the eighth internal data strobe signal IDQS <8> according to the sixth enable signal EN6. It is composed.

이와 같은 구성의 제22 버퍼부(38)는 테스트모신호(TM)가 인에이블되거나 노멀모드신호(NM)가 인에이블되면, 제8 데이터스트로브신호(DQS<8>)를 버퍼링하여 제8 내부데이터스트로브신호(IDQS<8>)로 출력한다.The twenty-second buffer unit 38 having the above configuration buffers the eighth data strobe signal DQS <8> when the test mother signal TM is enabled or the normal mode signal NM is enabled. Output as data strobe signal IDQS <8>.

칩선택신호 입력부(4)는, 도 10에 도시된 바와 같이, 제7 인에이블신호 생성부(41) 및 제6 버퍼(42)로 구성된다. As illustrated in FIG. 10, the chip select signal input unit 4 includes a seventh enable signal generator 41 and a sixth buffer 42.

제7 인에이블신호 생성부(42)는 테스트모드신호(TM)와 노멀모드신호(NM)를 입력받아 제7 인에이블신호(EN7)로 출력하는 제7 낸드게이트(ND7)로 구성된다. 제6 버퍼(42)는 제7 인에이블신호(EN7)에 따라 제23 패드(PAD23)에 실린 칩선택신호(CSB)를 버퍼링하여 내부칩선택신호(ICSB)로 출력하는 차동증폭기로 구성된다.The seventh enable signal generator 42 includes a seventh NAND gate ND7 that receives the test mode signal TM and the normal mode signal NM and outputs the seventh enable signal EN7. The sixth buffer 42 includes a differential amplifier configured to buffer the chip select signal CSB carried on the twenty-third pad PAD23 according to the seventh enable signal EN7 and output the buffered chip select signal ISCB.

클록인에이블신호 입력부(5)와 클록 입력부(6)도 칩선택신호 입력부(4)와 동일한 구조로 설계되어, 클록인에이블신호 입력부(5)는 내부클록인에이블신호(ICKE)를 생성하고, 클록 입력부(6)는 내부클록(ICLK)을 생성한다.The clock enable signal input unit 5 and the clock input unit 6 are also designed in the same structure as the chip select signal input unit 4, so that the clock enable signal input unit 5 generates an internal clock enable signal ICKE, The clock input unit 6 generates an internal clock ICLK.

디코딩부(7)는, 도 11에 도시된 바와 같이, 커맨드 디코더(71)와 어드레스 디코더(72)로 구성된다.The decoding unit 7 is composed of a command decoder 71 and an address decoder 72 as shown in FIG.

커맨드 디코더(71)는 내부클록신호(ICLK)와 내부클록인에이블신호(ICKE)와 내부칩선택신호(ICSB) 및 제1 내지 제4 내부커맨드어드레스신호(ICA<1:4>)를 디코딩하여, 액티브커맨드(ACT)와 프리차지커맨드(PREC)와 리드커맨드(RD)와 라이트커맨드(WT)와 오토리프레쉬커맨드(AREF)와 셀프리프레쉬커맨드(SREF)와 버스트커맨드(BST) 및 비구동커맨드(NOP)를 생성한다.The command decoder 71 decodes the internal clock signal ICLK, the internal clock enable signal ICKE, the internal chip select signal ISCB, and the first to fourth internal command address signals ICA <1: 4>. Active Command (ACT), Precharge Command (PREC), Lead Command (RD), Light Command (WT), Auto Refresh Command (AREF), Self-Fresh Command (SREF), Burst Command (BST) and Non-Drive Command ( NOP).

어드레스 디코더(72)는 제1 내지 제21 내부커맨드어드레스신호(ICA<1:21>)를 디코딩하여 로우어드레스신호(RADD<1:15>)와 컬럼어드레스신호(CADD<1:15>) 및 뱅크어드레스신호(BADD<1:4>)를 생성한다.The address decoder 72 decodes the first through twenty-first internal command address signals ICA <1:21> to display the low address signals RADD <1:15> and the column address signals CADD <1:15>, and The bank address signals BADD <1: 4> are generated.

이상과 같은 반도체 메모리 장치의 동작을 설명하기에 앞서, LPDDR2의 데이터 처리능력을 테스트하는데는 총 8가지의 상태를 규정짓는 커맨드가 필요하다. 즉, LPDDR2의 데이터 처리능력을 테스트하는데는 액티브커맨드(ACT)와 프리차지커맨드(PREC)와 리드커맨드(RD)와 라이트커맨드(WT)와 오토리프레쉬커맨드(AREF)와 셀프리프레쉬커맨드(SREF)와 버스트커맨드(BST) 및 비구동커맨드(NOP)가 필요하다. 위와 같이 8개의 상태를 구별하기 위해서는 3개의 커맨드어드레스신호가 필요하고, 뱅크를 선택하기 위해서는 3개의 커맨드어드레스신호가 필요하며, 컬럼 및 로우어드레스를 선택하기 위해서는 15개의 커맨드어드레스신호가 필요하다. 즉, 상술한 8개의 상태를 구별하기 위해서는 총 21개의 커맨드어드레스신호가 필요하다. 그래서, 본 실시예에서는 제1 내지 제10 커맨드어드레스신호(CA<1:10>)를 입력받는 커맨드어드레스신호 입력부(1) 뿐만 아니라, 테스트모드에서는 규정짓지 않아도 되는 커맨드에 대응하는 입력부(2, 3)를 통해 나머지 제11 내지 제21 커맨드어드레스신호를 입력받는 방식을 제안한다.Before explaining the operation of the semiconductor memory device as described above, a command for defining a total of eight states is required to test the data processing capability of the LPDDR2. In other words, to test the data processing capability of LPDDR2, active command (ACT), precharge command (PREC), lead command (RD), light command (WT), auto refresh command (AREF), self-fresh command (SREF), Burst commands (BST) and non-driven commands (NOP) are required. As described above, three command address signals are required to distinguish eight states, three command address signals are required to select a bank, and 15 command address signals are required to select a column and a low address. That is, a total of 21 command address signals are required to distinguish the above eight states. Therefore, in the present embodiment, not only the command address signal input unit 1 which receives the first to tenth command address signals CA <1:10>, but also the input unit 2 corresponding to a command that does not need to be specified in the test mode. A method of receiving the remaining eleventh to 21st command address signals through 3) is proposed.

LPDDR2의 스펙에 의하면, LPDDR2의 패드 수는 클록 및 클록바 입력 패드, 클록인에이블신호 입력 패드, 칩선택신호 입력 패드, 제1 내지 제10 커맨드어드레스신호 입력 패드, 제1 내지 제8 데이터스트로브신호 입력 패드, 제1 내지 제4 데이터마스크신호 입력 패드, 제1 내지 제32 데이터입/출력 패드를 포함하여 총 58개로 규정되어 있다. 이 중, 제1 내지 제32 데이터입/출력 패드는 데이터를 입력받는 패드로서 테스트모드에서 제1 내지 제32 데이터입/출력 패드를 통해 커맨드어드레스를 수신할 수 없다. 하지만, 제1 내지 제4 데이터마스크신호는 특정 데이터를 추출하는 동작이기 때문에 데이터의 처리능력을 테스트하는 동작에서는 필요치 않은 신호이고, 제1 내지 제8 데이터스트로브신호도 하나의 데이터스트로브신호만으로도 데이터의 입/출력이 가능하기 때문에 테스트 동작에서 제1 내지 제7 데이터스트로브신호는 필요치 않은 신호이다.According to the specification of the LPDDR2, the number of pads of the LPDDR2 includes a clock and a clock bar input pad, a clock enable signal input pad, a chip select signal input pad, first to tenth command address signal input pads, and first to eighth data strobe signals. A total of 58 items are defined, including an input pad, first to fourth data mask signal input pads, and first to thirty-second data input / output pads. Among the first to thirty-second data input / output pads, the first to thirty-second data input / output pads may receive a command address through the first to thirty-second data input / output pads in a test mode. However, since the first to fourth data mask signals are an operation of extracting specific data, the first to fourth data mask signals are not necessary for the operation of testing the processing capability of the data, and the first to eighth data strobe signals may be used only with one data strobe signal. Since input / output is possible, the first to seventh data strobe signals are unnecessary signals in the test operation.

결과적으로, 제1 내지 제10 커맨드어드레스신호 입력 패드, 제1 내지 제4 데이터마스크신호 입력 패드, 제1 내지 제7 데이터스트로브신호 입력 패드를 통해 커맨드어드레스를 입력받을 수 있다. As a result, the command addresses may be received through the first to tenth command address signal input pads, the first to fourth data mask signal input pads, and the first to seventh data strobe signal input pads.

본 실시예에서는 위와 같이 테스트 동작에서 용도를 전환할 수 있는 패드들을 이용하여 커맨드어드레스신호를 입력받아 기존 DRAM용 테스트 장비로도 LPDDR2를 테스트할 수 있다.In the present exemplary embodiment, the LPDDR2 can be tested with the existing DRAM test equipment by receiving a command address signal using the pads that can be used in the test operation as described above.

이하, 본 실시예에 따른 반도체 메모리 장치의 동작을 설명하면 다음과 같다.Hereinafter, the operation of the semiconductor memory device according to the present embodiment will be described.

테스트모드신호(TM)가 인에이블되면, 기존 DRAM용 테스트 장비로부터 제1 내지 제21 커맨드어드레스신호(CA<1:21>)가 출력된다. When the test mode signal TM is enabled, the first to twenty first command address signals CA <1:21> are output from the existing DRAM test equipment.

커맨드어드레스신호 입력부(1)와 데이터마스크신호 입력부(2) 및 데이터스트로브신호 입력부(3)는 각각 제1 내지 제10 패드(PAD1~PAD10)에 실린 제1 내지 제10 커맨드어드레스신호(CA<1:10>)와 제11 내지 제14 패드(PAD11~PAD14)에 실린 제11 내지 제14 커맨드어드레스신호(CA<11:14>) 및 제15 내지 제21 패드(PAD15~PAD21)에 실린 제15 내지 제21 커맨드어드레스신호(CA<15:21>)를 입력받아 버퍼링한 후, 제1 내지 제10 내부커맨드어드레스신호(ICA<1:10>)와 제11 내지 제14 내부커맨드어드레스신호(ICA<11:14>) 및 제15 내지 제21 내부커맨드어드레스신호(ICA<15:21>)로 출력한다. 그리고, 데이터스트로브신호 입력부(3) 내 제8 버퍼부(38)는 제22 패드(PAD22)에 실린 데이터스트로브신호(DQS<8>)를 버퍼링하여 테스트모드에서 데이터를 전달받기 위한 내부데이터스트로브신호(IDQS<8>)로 출력한다.The command address signal input unit 1, the data mask signal input unit 2, and the data strobe signal input unit 3 are each of the first to tenth command address signals CA <1 loaded on the first to tenth pads PAD1 to PAD10. 10), the eleventh to fourteenth command address signals CA <11:14> on the eleventh to fourteenth pads PAD11 to PAD14, and the fifteenth to twenty-first pads PAD15 to PAD21. To buffer the first to tenth command address signals CA <15:21> to the first to tenth internal command address signals ICA <1:10> and the eleventh to fourteenth internal command address signals ICA. <11:14>) and the fifteenth to twenty-first internal command address signals ICA <15:21>. The eighth buffer unit 38 in the data strobe signal input unit 3 buffers the data strobe signal DQS <8> mounted on the twenty-second pad PAD22 to receive data in the test mode. Output to (IDQS <8>).

칩선택신호 입력부(4)와 클록인에이블신호 입력부(5) 및 클록 입력부(6)는 각각 제23 패드(PAD23)에 실린 칩선택신호(CSB)와 제24 패드(PAD24)에 실린 클록인에이블신호(CKE) 및 제25 패드(PAD25)에 실린 클록(CLK)을 입력받아 버퍼링한 후, 내부칩선택신호(ICSB)와 내부클록인에이블신호(ICKE) 및 내부클록(ICLK)로 출력한다.The chip select signal input unit 4, the clock enable signal input unit 5, and the clock input unit 6 are clock enable loaded on the chip select signal CSB and the twenty-fourth pad PAD24 respectively mounted on the twenty-third pad PAD23. The signal CKE and the clock CLK loaded on the twenty-fifth pad PAD25 are received and buffered, and then output as an internal chip select signal ISCB, an internal clock enable signal ICKE, and an internal clock ICLK.

제1 내지 제21 내부커맨드어드레스신호(ICA<1:21)와 내부칩선택신호(ICSB)와 내부클록인에이블신호(ICKE) 및 내부클록(ICLK)가 생성되면, 디코딩부(7) 내 커맨드 디코더(71)는 각 신호들을 디코딩하여 액티브커맨드(ACT)와 프리차지커맨드(PREC)와 리드커맨드(RD)와 라이트커맨드(WT)와 오토리프레쉬커맨드(AREF)와 셀프리프레쉬커맨드(SREF)와 버스트커맨드(BST)를 생성하고, 어드레스 디코더(72)는 로우어드레스신호(RADD<1:15>)와 컬럼어드레스신호(CADD<1:15>) 및 뱅크어드레스신호(BADD<1:4>)를 생성한다.When the first to 21st internal command address signals ICA <1:21, the internal chip selection signal ISCB, the internal clock enable signal ICKE, and the internal clock ICLK are generated, the command in the decoding unit 7 is generated. The decoder 71 decodes the signals and bursts the active command (ACT), the precharge command (PREC), the lead command (RD), the light command (WT), the auto refresh command (AREF), the cell refresh command (SREF), and the burst. A command BST is generated, and the address decoder 72 generates the low address signal RADD <1:15>, the column address signal CADD <1:15>, and the bank address signal BADD <1: 4>. Create

전술한 본 실시예를 정리해 보면, 기존의 DRAM용 테스트 장비에서 LPDDR2를 테스트하기 위해 반도체 메모리 장치는 테스트모드에서 규정되지 않는 커맨드에 대응하는 패드들을 통해 커맨드어드레스신호를 수신한다. 이는, 기존의 DRAM보다 LPDDR2가 커맨드어드레스신호를 전달받는 패드의 수가 더 적기 때문에, 기존의 DRAM용 테스트 장비에서 LPDDR2가 테스트되지 못하는 점을 개선하기 위한 것이다.In summary, the semiconductor memory device receives a command address signal through pads corresponding to a command not defined in the test mode in order to test the LPDDR2 in the existing DRAM test equipment. This is because the LPDDR2 receives fewer command address signals than the conventional DRAM, so that the LPDDR2 cannot be tested in the conventional DRAM test equipment.

따라서, 본 실시예에 따른 반도체 메모리 장치는 클록의 라이징시점에만 커맨드어드레스신호를 전달하는 기존 DRAM용 테스트 장비에서도 테스트를 진행할 수 있어서, 새로운 테스트 장비의 구입비용을 절감할 수 있는 효과가 있다.
Therefore, the semiconductor memory device according to the present exemplary embodiment can test the existing DRAM test equipment that delivers the command address signal only at the time of rising of the clock, thereby reducing the cost of purchasing new test equipment.

1 : 커맨드어드레스신호 입력부 2 : 데이터마스크신호 입력부
3 : 데이터스트로브신호 입력부 4 : 칩선택신호 입력부
5 : 클록인에이블신호 입력부 6 : 클록 입력부
7 : 디코딩부1: Command address signal input unit 2: Data mask signal input unit
3: Data strobe signal input unit 4: Chip select signal input unit
5: Clock enable signal input part 6: Clock input part
7: decoding unit

Claims

A first input unit for buffering the first address signal group and outputting the first address group;
When the test mode signal is enabled and the test mode signal is enabled, the second address signal group inputted to the pad is buffered and output to the second internal address signal group, the test mode ends, and the normal operation mode is entered to enter the test. A second input unit for buffering the data mask signal input to the pad and outputting the internal data mask signal when the mode signal is disabled and the normal mode signal is enabled; And
When the test mode signal is enabled and the test mode signal is enabled, the third address signal group inputted to the pad is buffered and output to the third internal address signal group, the test mode ends, and the normal operation mode is entered. And a third input unit configured to buffer the data strobe signal input to the pad and to output the internal data strobe signal when the test mode signal is disabled and the normal mode signal is enabled.

Claim 2 has been abandoned due to the setting registration fee.

The semiconductor memory device of claim 1, wherein the first input unit buffers the first address signal group and outputs the buffered first address signal group to the first internal address signal group when the test mode signal or the normal mode signal is enabled.

Claim 3 was abandoned when the setup registration fee was paid.

The method of claim 1, wherein the first input unit buffers each of the first to tenth command address signals of the first address signal group according to the test mode signal and the normal mode signal to generate a first one of the first internal address signal group. A first to tenth buffer unit for outputting the first to tenth internal command address signal.

Claim 4 was abandoned when the registration fee was paid.

The method of claim 3, wherein the first buffer unit
A first enable signal generator configured to negatively multiply the test mode signal and the normal mode signal to output a first enable signal;
A first signal transfer unit configured to transfer the first command address signal as a first pre-internal command address signal in response to the first enable signal; And
And a first buffer which buffers the first pre-internal command address signal and outputs the first internal command address signal as the first internal command address signal.

Claim 5 was abandoned upon payment of a set-up fee.

The semiconductor memory device of claim 3, wherein each of the first to tenth command address signals is input from the outside through the first to tenth pads.

Claim 6 was abandoned when the registration fee was paid.

The method of claim 1, wherein the second input unit buffers each of the first to fourth data mask signals according to the normal mode signal and outputs the first to fourth internal data mask signals, and the second to the second mode according to the test mode signal. And an eleventh through fourteenth buffer units for buffering each of the eleventh through fourteenth command address signals in the address signal group and outputting the eleventh through fourteenth internal command address signals.

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 6, wherein the eleventh buffer unit
A first signal output unit which buffers the eleventh command address signal and outputs the eleventh internal command address signal according to the test mode signal; And
And a second signal output unit configured to buffer the first data mask signal and output the buffered first data mask signal as the first internal data mask signal according to the enable of the normal mode signal.

Claim 8 was abandoned when the registration fee was paid.

The method of claim 7, wherein the first signal output unit
A second signal transfer unit configured to output the eleventh command address signal as an eleventh pre-internal command address signal according to the enable of the test mode signal;
A second enable signal generation unit for performing an AND operation on the normal mode signal and the test mode signal to output a second enable signal; And
And a second buffer configured to buffer the eleventh pre-internal command address signal according to the second enable signal and output the buffered signal as the eleventh internal command address signal.

Claim 9 was abandoned upon payment of a set-up fee.

The method of claim 7, wherein the second signal output unit
A third signal transfer unit configured to output the first data mask signal as a first pre-internal data mask signal according to the enable of the normal mode signal;
A first logic circuit for inverting the test mode signal;
A third enable signal generation unit for performing an AND operation on the normal mode signal and the output of the first logic circuit to output a third enable signal; And
And a third buffer configured to buffer the first pre-internal data mask signal according to the third enable signal and output the buffered first internal data mask signal as the first internal data mask signal.

Claim 10 was abandoned upon payment of a setup registration fee.

The method of claim 6, wherein each of the first to fourth data mask signals is input from the outside through the eleventh to fourteenth pads, and each of the eleventh to fourteenth command address signals is also through the eleventh to fourteenth pads. A semiconductor memory device input from the outside.

Claim 11 was abandoned upon payment of a setup registration fee.

The method of claim 1, wherein the third input unit buffers each of the first to seventh data strobe signals according to the normal mode signal, and outputs the first to seventh internal data strobe signals, and outputs the first to seventh internal data strobe signals according to the test mode signal. And a fifteenth to twenty-first buffer unit for buffering the fifteenth to twenty first command address signals among the address signal groups and outputting the fifteenth to twenty first internal command address signals, respectively.

Claim 12 was abandoned upon payment of a registration fee.

The method of claim 11, wherein the fifteenth buffer unit
A third signal output unit which buffers the fifteenth command address signal and outputs the fifteenth internal command address signal according to the enable of the test mode signal; And
And a fourth signal output unit configured to buffer the first data strobe signal and output the buffered first data strobe signal as the first internal data strobe signal according to the enable of the normal mode signal.

Claim 13 was abandoned upon payment of a registration fee.

The method of claim 12, wherein the third signal output unit
A third signal transfer unit configured to output the fifteenth command address signal as a fifteenth pre-internal command address signal according to the enable of the test mode signal;
A third enable signal generator for performing an AND operation on the normal mode signal and the test mode signal to output a third enable signal; And
And a third buffer buffering the fifteenth pre-internal command address signal according to the third enable signal and outputting the fifteenth internal command address signal.

Claim 14 was abandoned when the registration fee was paid.

The method of claim 12, wherein the fourth signal output unit
A fourth signal transfer unit configured to output the first data strobe signal as a first pre-internal data strobe signal according to the enable of the normal mode signal;
A second logic circuit for inverting the test mode signal;
A fourth enable signal generation unit for performing an AND operation on the normal mode signal and the output of the second logic circuit to output a fourth enable signal; And
And a fourth buffer configured to buffer the first pre-internal data strobe signal and output the buffered first internal data strobe signal according to the fourth enable signal.

Claim 15 was abandoned upon payment of a registration fee.

12. The apparatus of claim 11, wherein each of the first to seventh data strobe signals is input from the outside through the fifteenth to twenty-first pads, and each of the fifteenth to twenty-first command address signals is provided through the fifteenth to twenty-first pads. A semiconductor memory device input from the outside.

Claim 16 was abandoned upon payment of a setup registration fee.

The semiconductor memory device of claim 11, wherein the third input unit further comprises a twenty-second buffer unit configured to buffer an eighth data strobe signal according to the test mode signal and the normal mode signal and output the eighth data strobe signal as an eighth internal data strobe signal.

A first input unit for buffering the first address signal group and outputting the first address group;
When the test mode signal is enabled and the test mode signal is enabled, the second address signal group inputted to the pad is buffered and output to the second internal address signal group, the test mode ends, and the normal operation mode is entered to enter the test. A second input unit for buffering the data mask signal input to the pad and outputting the internal data mask signal when the mode signal is disabled and the normal mode signal is enabled;
When the test mode signal is enabled and the test mode signal is enabled, the third address signal group inputted to the pad is buffered and output to the third internal address signal group, the test mode ends, and the normal operation mode is entered. A third input unit configured to buffer the data strobe signal input to the pad and to output the internal data strobe signal when the test mode signal is disabled and the normal mode signal is enabled; And
And a decoding unit to decode the first to third address signal groups and output the internal command and the internal address signal.

Claim 18 was abandoned upon payment of a set-up fee.

The semiconductor memory device of claim 17, wherein the first input unit buffers the first address signal group and outputs the buffered first address signal group to the first internal address signal group when the test mode signal or the normal mode signal is enabled.

Claim 19 was abandoned upon payment of a registration fee.

18. The method of claim 17, wherein the first input unit buffers each of the first to tenth command address signals of the first address signal group according to the test mode signal and the normal mode signal to generate a first one of the first internal address signal group. A first to tenth buffer unit for outputting the first to tenth internal command address signal.

Claim 20 was abandoned upon payment of a registration fee.

20. The method of claim 19, wherein the first buffer unit
A first enable signal generator configured to negatively multiply the test mode signal and the normal mode signal to output a first enable signal;
A first signal transfer unit configured to transfer the first command address signal as a first pre-internal command address signal in response to the first enable signal; And
And a first buffer which buffers the first pre-internal command address signal and outputs the first internal command address signal as the first internal command address signal.

Claim 21 has been abandoned due to the setting registration fee.

The semiconductor memory device of claim 19, wherein each of the first to tenth command address signals is input from the outside through the first to tenth pads.

Claim 22 is abandoned in setting registration fee.

18. The method of claim 17, wherein the second input unit buffers each of the first to fourth data mask signals according to the normal mode signal, and outputs the first to fourth internal data mask signals, and the second to the second mode according to the test mode signal. And an eleventh through fourteenth buffer units for buffering each of the eleventh through fourteenth command address signals in the address signal group and outputting the eleventh through fourteenth internal command address signals.

Claim 23 was abandoned upon payment of a set-up fee.

The method of claim 22, wherein the eleventh buffer unit
A first signal output unit which buffers the eleventh command address signal and outputs the eleventh internal command address signal according to the test mode signal; And
And a second signal output unit configured to buffer the first data mask signal and output the buffered first data mask signal as the first internal data mask signal according to the enable of the normal mode signal.

Claim 24 is abandoned in setting registration fee.

The method of claim 23, wherein the first signal output unit
A second signal transfer unit configured to output the eleventh command address signal as an eleventh pre-internal command address signal according to the enable of the test mode signal;
A second enable signal generation unit for performing an AND operation on the normal mode signal and the test mode signal to output a second enable signal; And
And a second buffer configured to buffer the eleventh pre-internal command address signal according to the second enable signal and output the buffered signal as the eleventh internal command address signal.

Claim 25 is abandoned in setting registration fee.

The method of claim 23, wherein the second signal output unit
A third signal transfer unit configured to output the first data mask signal as a first pre-internal data mask signal according to the enable of the normal mode signal;
A first logic circuit for inverting the test mode signal;
A third enable signal generation unit for performing an AND operation on the normal mode signal and the output of the first logic circuit to output a third enable signal; And
And a third buffer configured to buffer the first pre-internal data mask signal according to the third enable signal and output the buffered first internal data mask signal as the first internal data mask signal.

Claim 26 is abandoned in setting registration fee.

23. The apparatus of claim 22, wherein each of the first to fourth data mask signals is input from the outside through the eleventh to fourteenth pads, and each of the eleventh to fourteenth command address signals is connected to the eleventh to fourteenth pads. A semiconductor memory device input from the outside.

Claim 27 was abandoned upon payment of a registration fee.

18. The method of claim 17, wherein the third input unit buffers each of the first to seventh data strobe signals according to the normal mode signal, and outputs the first to seventh internal data strobe signals, and the first to seventh internal data strobe signals. And a fifteenth to twenty-first buffer unit for buffering the fifteenth to twenty first command address signals among the address signal groups and outputting the fifteenth to twenty first internal command address signals, respectively.

Claim 28 has been abandoned due to the set registration fee.

The method of claim 27, wherein the fifteenth buffer unit
A third signal output unit which buffers the fifteenth command address signal and outputs the fifteenth internal command address signal according to the enable of the test mode signal; And
And a fourth signal output unit configured to buffer the first data strobe signal and output the buffered first data strobe signal as the first internal data strobe signal according to the enable of the normal mode signal.

Claim 29 has been abandoned due to the setting registration fee.

The method of claim 28, wherein the third signal output unit
A third signal transfer unit configured to output the fifteenth command address signal as a fifteenth pre-internal command address signal according to the enable of the test mode signal;
A third enable signal generator for performing an AND operation on the normal mode signal and the test mode signal to output a third enable signal; And
And a third buffer buffering the fifteenth pre-internal command address signal according to the third enable signal and outputting the fifteenth internal command address signal.

Claim 30 has been abandoned due to the set registration fee.

The method of claim 28, wherein the fourth signal output unit
A fourth signal transfer unit configured to output the first data strobe signal as a first pre-internal data strobe signal according to the enable of the normal mode signal;
A second logic circuit for inverting the test mode signal;
A fourth enable signal generation unit for performing an AND operation on the normal mode signal and the output of the second logic circuit to output a fourth enable signal; And
And a fourth buffer configured to buffer the first pre-internal data strobe signal and output the buffered first internal data strobe signal according to the fourth enable signal.

Claim 31 has been abandoned due to the setting registration fee.

28. The apparatus of claim 27, wherein each of the first to seventh data strobe signals is input from the outside through the fifteenth to twenty-first pads, and each of the fifteenth to twenty-first command address signals is also through the fifteenth to twenty-first pads. A semiconductor memory device input from the outside.

Claim 32 is abandoned due to the set registration fee.

28. The semiconductor memory device of claim 27, wherein the third input unit further comprises a twenty-second buffer unit configured to buffer an eighth data strobe signal according to the test mode signal and the normal mode signal and output the eighth data strobe signal as an eighth internal data strobe signal.

Claim 33 was abandoned upon payment of a registration fee.

The method of claim 17,
A fourth input unit which buffers the chip select signal and outputs the internal chip select signal;
A fifth input unit which buffers the clock enable signal and outputs the internal clock enable signal; And
And a sixth input unit buffering a clock and outputting the clock to an internal clock.

Claim 34 was abandoned upon payment of a registration fee.

The method of claim 33, wherein the decoding unit
The first to fourth internal command address signals of the internal clock, the internal clock enable signal, the internal chip selection signal, and the first address signal group are decoded to generate active commands, precharge commands, lead commands, write commands, and the like. A command decoder for generating auto refresh commands, self-fresh commands, burst commands, and non-driven commands; And
Decode the first to third address signal groups A semiconductor memory device comprising an address decoder for generating a low address signal, a column address signal, and a bank address signal.