KR101145347B1 - Low noise amplifier and gain control circuit for amplifier - Google Patents

Abstract

A technique related to a low noise amplifier in which gain is adjusted and a gain control circuit of the amplifier is disclosed. According to this technique, an amplifying unit for amplifying the input signal with a gain adjusted according to the first or second gain control signal to output an amplified signal; A controller configured to generate a selection signal according to a result of comparing the magnitude of the amplified signal with a reference voltage; And a gain adjuster configured to output the first gain control signal according to the amplitude of the amplified signal or the second gain control signal according to the magnitude of the reference voltage in response to the selection signal.

Amplifier, gain, power

Description

LOW NOISE AMPLIFIER AND GAIN CONTROL CIRCUIT FOR AMPLIFIER}

The present invention relates to a low noise amplifier and a gain control circuit of an amplifier, and more particularly, to a low noise amplifier and a gain control circuit of an amplifier whose gain is adjusted.

Recently, in order to meet the demands of consumers for the explosive increase in portable terminals, the technology has been developed for miniaturizing the size of the portable terminal and minimizing the power consumption of the portable terminal. In response to these demands, research is being conducted on how to increase the efficiency of the entire system as well as the efficiency of individual components of the receiver. In addition, a technique for effectively controlling the communication failure due to a channel failure such as fading, which is a signal damage caused by an irregular transmission characteristic of a transmission medium, has been developed.

In general, a plurality of amplifiers are used to amplify an input signal in a wireless communication system. The use of a plurality of amplifiers is because the dynamic range of each amplifier capable of linearly amplifying the input signal is limited, and in this case, the problem can be solved by connecting several amplifiers.

In particular, the low noise amplifier operates in a low gain mode when the magnitude of the input signal is large, and operates in a high gain mode when the magnitude of the input signal is small, thereby controlling the magnitude of the output signal, when the gain is excessively increased. In addition to unnecessary power consumption, there is a problem that the output signal can be distorted.

The present invention has been proposed to solve the above problems, and an object thereof is to provide an amplifier which can prevent the gain from being unnecessarily increased according to the magnitude of an input signal.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention, which are not mentioned above, can be understood by the following description, and more clearly by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

The present invention for achieving the above object is an amplifier for amplifying an input signal with a gain adjusted according to the first or second gain control signal to output an amplified signal; A controller configured to generate a selection signal according to a result of comparing the magnitude of the amplified signal with a reference voltage; And a gain adjuster configured to output the first gain control signal according to the amplitude of the amplified signal or the second gain control signal according to the magnitude of the reference voltage in response to the selection signal.

In addition, the present invention for achieving the above object is a control unit for generating a selection signal according to the result of the comparison of the magnitude and the reference voltage of the amplified signal; And a gain adjuster configured to output the first gain control signal according to the amplitude of the amplified signal or the second gain control signal according to the magnitude of the reference voltage in response to the selection signal. A gain control circuit of an amplifier, which is an amplified signal generated by a first amplifier or a second amplifier, is provided.

According to the present invention, the power consumption of the low noise amplifier can be reduced and the distortion of the amplified signal output by being amplified can be prevented by preventing the gain of the input signal from being unnecessarily increased.

In addition, according to the present invention, by adjusting the gain of the low noise amplifier within the input allowable range of the device, such as a mixer, which receives the output signal of the low noise amplifier, the non-linear characteristic that the output signal is out of the input allowable range is adjusted. Can be reduced.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, and in describing the present invention, a detailed description of well-known technology related to the present invention may unnecessarily obscure the subject matter of the present invention. If it is determined that the detailed description is omitted.

1 is a view showing a low noise amplifier according to an embodiment of the present invention.

As shown in FIG. 1, the low noise amplifier according to the present invention includes an amplifier 101, a controller 103, and a gain adjuster 105.

The amplifier 101 according to the present invention outputs an amplified signal by amplifying an input signal with a gain adjusted according to a gain control signal output from the gain adjuster 105. At this time, the gain adjusting unit 105 outputs a gain control signal according to the control of the control unit 103. The controller 103 compares the amplitude of the amplified signal fed back from the amplifier and the reference voltage, generates a selection signal according to the comparison result, and the gain adjusting unit 105 outputs a gain control signal in response to the selection signal. That is, the gain control unit 105 outputs a gain control signal according to the case where the amplified signal is larger or smaller than the reference voltage, and the amplifier 101 adjusts the gain according to the gain control signal.

Therefore, according to the present invention, when the amplitude of the amplified signal is greater than or equal to the reference voltage, an amplified signal that is no longer increased by the adjusted gain may be generated. Hereinafter, the amplifier 101, the control unit 103 and the gain control unit 105 will be described in more detail.

The amplifier 101 amplifies the input signal with a gain adjusted according to the first or second gain control signal and outputs an amplified signal. That is, the amplifier 101 may actually perform amplification in the low noise amplifier, and may include all amplification circuits that perform amplification. The first and second gain control signals are described below in detail as control signals output from the gain adjusting unit 105.

The controller 103 generates a selection signal according to a result of comparing the magnitude of the amplified signal and the reference voltage. The controller 103 generates a selection signal according to a result of comparing the amplitude of the amplified signal fed back from the amplifier 101 with the reference voltage, so that the amplitude of the amplified signal is further increased when the amplitude of the amplified signal is greater than or equal to the reference voltage. Can be prevented. That is, the controller 103 may generate a selection signal so that the amplitude of the amplified signal no longer increases, and control the gain adjusting unit 105 that receives the selection signal.

The gain adjusting unit 105 outputs a first gain control signal according to the amplitude of the amplified signal or a second gain control signal according to the magnitude of the reference voltage in response to the selection signal. The first and second gain control signals may be constituted by binary codes, and more specifically, the first gain control signal may be constituted by binary codes having variable code values according to the amplitude of the amplified signals. As the code value is changed, the gain may be adjusted in the amplifier 101.

The second gain control signal is output from the gain adjusting unit 105 when the amplitude of the amplified signal is greater than the reference voltage, and the binary code value of the first gain control signal generated in a state where the amplitude of the amplified signal is greater than the reference voltage. It may be a gain control signal having one of the values. For example, as the amplitude of the amplified signal increases, the first gain control signal varies in the order of '00', '01', '10', and '11', the gain increases, and the amplitude of the amplified signal is a reference voltage. When the binary code values of the first gain control signal generated in the larger size state are '00', '01', or '10', the binary code value of the second gain control signal may be '10'.

Therefore, according to the present invention, even when the amplitude of the amplified signal is greater than the reference voltage, since the first gain control signal generated before the amplitude of the amplified signal is greater than the reference voltage is input to the amplifier 101, the amplified signal. The size of may no longer be increased. In this case, the gain adjusting unit 105 stores the first gain control signal that increases or decreases according to the magnitude of the amplified signal fed back, and in response to the selection signal, the first gain stored instead of the first gain control signal that increases or decreases. One of the control signals may be output as the second gain control signal.

In addition, according to the present invention, by adjusting the magnitude of the reference voltage, it is possible to adjust the maximum magnitude of the amplified signal. That is, in the above-described example, when the reference voltage is decreased so that the second gain control signal becomes '01', the maximum amplitude of the amplified signal may be smaller than when the second gain control signal is '10'.

As a result, according to the present invention, the gain according to the magnitude of the amplified signal is prevented from being unnecessarily increased, thereby reducing power consumption of the amplifier and preventing distortion of the amplified signal that is amplified and output. In addition, the linear characteristics of the mixer can be ensured by allowing the amplified signal to swing within an input tolerance range of a device such as a mixer using the amplified signal of the amplifier.

FIG. 2 is a diagram for describing the control unit 103 and the gain control unit 105 of FIG. 1 in more detail.

As shown in FIG. 2, the gain adjuster 105 may more specifically include a peak detector 201, an AD converter 203, a signal selector 205, and a signal storage 207. The controller 103 may be a comparator.

The peak detector 201 generates a detection signal charged and discharged according to the peak value of the amplified signal. That is, the peak detector 201 may generate a detection signal that increases in proportion to the peak of the amplified signal that is a sinusoidal voltage. For example, the voltage of the detection signal may increase as the peak value of the amplified signal increases, and the voltage of the detection signal may decrease as the peak value of the amplified signal decreases.

The AD converter 203 generates a first gain control signal PRE_SEL <0: 1> composed of a binary code according to the detection signal. As described above, the detection signal is an analog signal charged and discharged according to the peak value of the amplified signal, and the AD converter 203 converts the detection signal into a digital signal composed of a binary code. The AD converter 203 divides the predetermined reference voltage into a plurality of voltages, and compares the magnitude of the divided voltage with the detection signal voltage to obtain a first gain control signal PRE_SEL <0: 1>). At this time, the comparator constituting the AD converter 203 may have hysteresis characteristics in order to avoid bang-bang operation.

The signal selector 205 outputs the first gain control signal PRE_SEL <0: 1> in response to the selection signal or the first gain control signal PRE_SEL <0: 1> stored in the signal storage unit 207. ) Is output as the second gain control signal. The signal storage unit 207 stores the first gain control signal PRE_SEL <0: 1>, and the signal selector 205 generates the first gain control signal PRE_SEL generated from the AD converter 203 according to the selection signal. <0: 1> is output directly or the first gain control signal PRE_SEL <0: 1> stored in the signal storage unit 207 is output as the second gain control signal. Here, SEL <0: 1> is a signal representing both the first and second gain control signals.

In more detail, the signal selector 205 may include a switch that is turned on / off in response to the selection signal, and a signal storage unit 207 configured as a latch may be connected to an output terminal of the switch. Accordingly, the first gain control signal PRE_SEL <0: 1> generated from the AD converter 203 is transmitted to the amplifier 101 in the switched-on state, but the signal storage unit 207 is switched in the switched-off state. The first gain control signal PRE_SEL <0: 1> stored therein is transmitted to the amplifier 101. As described above, the selection signal is a signal according to a result of comparing the amplitude of the amplification signal with the reference voltage, and the first gain control signal stored in the signal storage unit 207 in the switched off state becomes the second gain control signal. Can be.

Since the latch constituting the signal storage unit 207 generally stores one bit, the latch used according to the bit of the binary code constituting the gain control signal can be varied. In addition, since the signal storage unit 207 is connected to the output terminal of the switch, the first gain control signal and the signal stored in the signal storage unit 207 may collide with each other in connection with the switching operation. Therefore, the size of the transistor constituting the latch is preferably designed in consideration of the collision.

Meanwhile, as shown in FIG. 1, the low noise amplifier according to the present invention may further include an initial voltage removing unit 209 for setting an initial value of the first gain control signal PRE_SEL <0: 1>. Since the AD converter 203 may operate abnormally when the amplifier starts to operate, the initial voltage removing unit 209 is connected to the output terminal of the AD converter 203 so that the first gain control signal PRE_SEL <0: 1 Set the initial value of>).

In more detail, the initial voltage removing unit 209 may include a comparator and a delay circuit. The comparator compares the lowest voltage among the voltages divided by the AD converter 203 with the detection signal of the peak detector 201 so that the AD converter 203 outputs a first value to a predetermined value until the AD converter 203 outputs a normal first gain control signal. An initial value of the gain control signal PRE_SEL <0: 1> may be set.

3 is a view for explaining the peak detector 201 in more detail.

As shown in FIG. 3, the peak detector 201 includes a termination unit 301, a capacitor 303, and a discharge unit 305.

The termination unit 301 generates the detection signal VPEAK terminated with the preset voltage VDD according to the comparison result of the amplitude of the amplified signal and the magnitude of the detection signal VPEAK.

The amplified signal V _in is a sinusoidal signal having a V _peak as a peak value, as shown in [Equation 1]. In order to detect the magnitude of the sinusoidal voltage having fast response performance, the termination unit 301 has a wide linear operating range. It is preferable to have.

The comparator of the termination unit 301 compares the amplified signal and the detection signal VPEAK, outputs a low level signal when the amplified signal is larger than the detection signal VPEAK, and the amplified signal is smaller than the detection signal VPEAK. In this case, a high level signal is output. Therefore, when the amplification signal is larger than the detection signal VPEAK, the PMOS transistor is turned on so that the voltage of the detection signal VPEAK is increased. When the amplification signal is smaller than the detection signal VPEAK, the PMOS transistor is turned off. The voltage of the detection signal VPEAK drops.

At this time, since the capacitor 303 charges the charge according to the detection signal VPEAK, and the discharge unit 305 discharges the charge charged in the capacitor 303, the voltage of the detection signal VPEAK gradually increases or decreases. Can descend.

In this case, the discharge unit 305 may be a diode connected transistor. The peak detection unit 201 according to the present invention can reduce the size of the peak detection unit 201 while maintaining the discharge effect by using the diode-connected transistor as the discharge unit 305, which is advantageous in circuit integration. .

4 is a diagram for describing a first gain control signal output from the AD converter 203. In FIG. 4, the first gain control signal for increasing the gain in proportion to the amplitude of the amplified signal is described as an embodiment.

In FIG. 4, DM stands for Detection Mode and indicates the voltage to be divided in the AD converter 203. Higher voltage from DM1 to DM3. In the table of FIG. 4, DV represents an amplified signal input to the AD converter 203. That is, according to the table of FIG. 4, the AD converter 203 generates a thermometer code in accordance with DV and DM1 to DM3, and decodes the first gain control signal composed of a binary code. Create

5 is a view for explaining the amplifier 101 in more detail.

In FIG. 5, the amplifying unit of the two-stage cascode structure is described as an embodiment. As shown in FIG. 5, the amplifier 101 according to the present invention includes first and second amplifier circuits 501 and 503 as two stages. The input signal is input to the first port PORT1 of the first amplifier circuit 501 and amplified, and output to the second port PORT2 of the second amplifier circuit 503.

First, the characteristics and design of the low noise amplifier, which is located in front of the receiver and serves to suppress noise components and amplify only a desired signal, will be briefly described.

The input impedance Z _in of the basic cascode structure is shown _in Equation 2 below.

를 이용하면 입력 임피던스에서 요구하는 실수부를 만들 수 있다. 그리고 게이트인덕터

를 이용하여 입력 임피던스(Z_in)의 허수부를 제거할 수 있다. 기본적인 캐스코드 구조에 게이트와 소스 사이에 추가적인 캐패시터를 연결하게 되면, 최적의 잡음 반사계수

과

(입력 반사계수)가 스미스 차트 상에서 한 곳에 모이는 현상이 나타나기 때문에 이득과 잡음 정합을 동시에 달성할 수 있다Equation 2 is derived by ignoring the feedback capacitor to theoretically simplify the basic structure of the common ground transistor. In Equation 2, the source inductor with the transconductance (g _m ) of the transistor fixed

Use to create the real part required by the input impedance. And gate inductor

The imaginary part of the input impedance Z _in can be removed using. Optimal noise reflection coefficient by connecting additional capacitors between the gate and source to the basic cascode structure

and

Gain and noise matching can be achieved simultaneously because (input reflection coefficient) converges on the Smith chart.

In general, the main noise power source of the MOSFET is composed of the drain current noise (channel current noise) and the gate noise (induced gate noise), the power density of each of the equation (3) and (4).

는 트랜지스터의 영바이어스 드레인 컨덕턴스(zero-bias drain conductance)로

V일 때 드레인과 소스사이의 컨덕턴스를 나타낸다.

는 드레인 전류의 잡음 계수로 long channel의 경우

값은 2/3이고,

는 게이트 잡음계수이며 long channel의 경우 4/3이고 게이트 잡음과 관련된 파라미터

이다. Where k is Boltzmann's constant and T is the absolute temperature.

Is the zero-bias drain conductance of the transistor

When V is the conductance between the drain and the source.

Is the noise factor of the drain current for long channels

The value is 2/3,

Is the gate noise coefficient, 4/3 for the long channel, and the parameters related to the gate noise

to be.

Considering the two noise sources described above, that is, drain current noise and gate noise, a noise factor can be obtained and a point having the best noise figure can be found. Thus, there is an optimal size of transistor to minimize the amplifier's noise figure for a given power dissipation and input impedance.

The two-stage amplifying unit 101 secures sufficient gain to exhibit stable reception characteristics and appropriate noise figure characteristics. The first amplifier circuit 501 prevents the deterioration of the reflection coefficient and the noise figure that appear as the gain changes. The second amplifier 503 serves to adjust the gain.

According to the Friis formula, the noise figure of the low noise amplifier follows the noise figure of the first amplifier circuit 501. Equation 5 below is a Friis formula for the two stage amplifier.

은 제1증폭회로(501)의 이득이고

는 제2증폭회로(503)의 이득이며,

과

는 제1 및 제2증폭회로(501, 503) 각각의 잡음지수를 나타낸다. here,

Is the gain of the first amplifier circuit 501

Is the gain of the second amplifier circuit 503,

and

Denotes a noise figure of each of the first and second amplifier circuits 501 and 503.

As described above, since the noise characteristics of the receiver generally have an absolute effect on the noise characteristics of the first stage of the low noise amplifier, a certain gain or more must be secured to minimize the noise characteristics in the circuit after the first stage. To this end, in consideration of Equation 5, a power-constrained noise optimization technique may be used under the power condition proposed in the first stage of the low noise amplifier, that is, the first amplifier circuit 501.

According to the present invention, the amplifier 101 adjusts the gain by adjusting the amount of current flowing through the amplifier 101 by using a transistor turned on / off according to the first or second gain control signal. In FIG. 5, the transistors M7, M8, and M9 are turned on / off and gain is adjusted according to the first or second gain control signal.

The decoder 505 decodes the first or second gain control signal according to the number of binary code bits of the first or second gain control signal and the number of transistors turned on / off to adjust the gain. For example, as shown in FIG. 5, when the first or second gain control signal is a control signal composed of two bits of SEL <0: 1>, the decoder 505 may determine the first or second gain control signal. By decoding the 3bit signal (SW <1: 3>) can be generated. Here, SELB <0: 1> represents an inverted signal of SEL <0: 1>. Each of the transistors M7, M8, and M9 is turned on and off in accordance with a 3-bit signal SW <1: 3> to adjust the gain.

The relationship between the currents I ₁ , I ₂ , I ₃ , I ₄ and the corresponding gains flowing through the transistors M5, M7, M8, and M9, respectively, is shown in Equations 6 to 9. Here, the gain mode represents different gains according to the gain control signal.

As shown in FIG. 5, transistor M5 is always turned on, thus providing one of the higher gains when one of M7, M8 and M9 is on than when only M5 is on. As shown in Equations 6 to 8, the gain may be adjusted according to the sizes of M7, M8 and M9.

On the other hand, the transistor M4 of the second amplifier 503 serves to increase the isolation between the input and the output.

6 to 8 are diagrams showing simulation results of a low noise amplifier according to the present invention. 6 to 8, a low noise amplifier operating efficiently according to the magnitude of the input signal in the 5.2 GHz band and designed through a 0.18um CMOS process was used as an embodiment. 6 to 8, the HSPICE simulator was used for the simulation of the gain control unit 105, and the Cadence specter simulator was used for the simulation of the amplifier 101.

6 is a diagram illustrating a gain control signal according to a detection signal in the gain adjusting unit 105. As the magnitude of the detection signal increases, the bit value of the gain control signal also increases, and it can be seen that the binary code value of the first gain control signal coincides with the code value shown in FIG. 4. FIG. 7 is a diagram illustrating a gain according to a gain mode of the low noise amplifier illustrated in FIG. 5. Here, the power supplied to the low noise amplifier, that is, the amplifier 101 is 1.8V, and as shown in FIG. 6, the gain increases as the bit value of the first gain control signal increases. 8 is a diagram illustrating input reflection loss, and S ₁₁ represents an input reflection coefficient. That is, the lower the S ₁₁ value, the better the characteristic that the input signal is output without being reflected. As shown in FIG. 8, it can be seen that the low noise amplifier operates efficiently in the 5.2 GHz frequency band.

9 is a diagram illustrating a gain control circuit of an amplifier according to an embodiment of the present invention. In FIG. 9, the gain control circuit 901, the low noise amplifiers 903 and LNA, and the mixer 905 and MIXER according to the present invention. And a receiver including a variable gain amplifier 907 (VGA) are described as an embodiment. The gain control circuit 901 according to the present invention corresponds to the control unit 103 and the gain control unit 105 of FIG. 1, and the low noise amplifier 903 corresponds to the amplifying unit 101 of FIG. 1.

The low noise amplifier 903 amplifies an input signal under the control of the gain control circuit 901 and outputs an amplified signal. The mixer 905 mixes the preset signal and the amplified signal and outputs the mixed signal to the variable gain amplifier 907, and the variable gain amplifier 907 amplifies the mixed signal again. The gain control circuit 901 generates a gain control signal according to the output signal of the variable gain amplifier 907, and the low noise amplifier 903 adjusts the gain according to the gain control signal.

The gain control circuit 901 according to the present invention is a control unit for generating a selection signal according to a result of comparing the amplitude of the amplified signal and the reference voltage and the first gain control signal or reference voltage according to the amplitude of the amplified signal. A gain control unit for outputting a second gain control signal according to the size of the, amplified signal may be an amplified signal generated by the first amplifier or the second amplifier. Here, the first amplifier may be a low noise amplifier 903 and the second amplifier may be a variable gain amplifier 907.

That is, the gain control circuit 901 according to the present invention may be included in the amplifier as described in FIG. 1 and may be included as a separate communication chip in the receiver.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a view showing a low noise amplifier according to an embodiment of the present invention,

2 is a view for explaining in detail the control unit 103 and the gain control unit 105 of FIG.

3 is a view for explaining the peak detector 201 in more detail,

4 is a view for explaining a first gain control signal output from the AD converter 203,

5 is a view for explaining the amplifier 101 in more detail,

6 to 8 show simulation results of the low noise amplifier according to the present invention;

9 is a diagram for describing a gain control circuit of an amplifier according to an exemplary embodiment of the present invention.

Claims (8)

An amplifier for amplifying the input signal with a gain adjusted according to the first or second gain control signal and outputting an amplified signal; A controller configured to generate a selection signal according to a result of comparing the magnitude of the amplified signal with a reference voltage; And A gain adjusting unit outputting the first gain control signal or the second gain control signal according to the magnitude of the reference voltage in response to the selection signal; Including, The second gain control signal is A gain control output when the magnitude of the amplified signal is greater than the reference voltage and having one of binary code values of the first gain control signal generated in a state in which the magnitude of the amplified signal is greater than the reference voltage Low noise amplifier that is a signal. delete The method of claim 1, The gain control unit A peak detector for generating a detection signal charged and discharged according to the peak value of the amplified signal; An AD converter for generating the first gain control signal composed of a binary code according to the detection signal; A signal storage unit for storing the first gain control signal; And A signal selector configured to output the first gain control signal or output the first gain control signal stored in the signal storage as the second gain control signal in response to the selection signal; Low noise amplifier comprising a. The method of claim 3, The peak detection unit A termination unit configured to generate the detection signal terminated at a predetermined voltage according to a comparison result of the amplitude of the amplified signal and the detection signal; A capacitor charging the charge according to the detection signal; And Discharge part for discharging the electric charge charged in the capacitor Low noise amplifier comprising a. The method of claim 3, The gain control unit An initial voltage removing unit configured to set an initial value of the first gain control signal Low noise amplifier comprising more. The method of claim 1, The amplification unit Adjusting the amount of current flowing through the amplifying unit by using a transistor that is turned on / off according to the first or second gain control signal Low noise amplifier comprising a. A controller configured to generate a selection signal according to a result of comparing the amplitude of the amplified signal with a reference voltage; And A gain adjuster configured to output a first gain control signal composed of a binary code whose code value varies according to the amplitude of the amplified signal or a second gain control signal according to the magnitude of the reference voltage in response to the selection signal; , The second gain control signal is A gain control output when the magnitude of the amplified signal is greater than the reference voltage and having one of binary code values of the first gain control signal generated in a state in which the magnitude of the amplified signal is greater than the reference voltage Signal, The amplified signal is Amplified signal generated by the first amplifier or the second amplifier Gain control circuit of amplifier. The method of claim 7, wherein A peak detector for generating a detection signal charged and discharged according to the peak value of the amplified signal; An AD converter for generating the first gain control signal composed of a binary code according to the detection signal; A signal storage unit for storing the first gain control signal; And A signal selector configured to output the first gain control signal in response to the selection signal, or to output the first gain control signal stored in the signal storage as the second gain control signal Gain control circuit of the amplifier comprising a.

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