KR101147366B1 - Ldmosfet for rf power amplifiers and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a horizontal diffusion MOS transistor having a high efficiency and a high output voltage and a method of manufacturing the same. The horizontal diffusion MOS transistor of the present invention includes a first conductive substrate having a first conductive epitaxial layer; A polygate formed on an upper surface of the first conductive epitaxial layer; A high concentration second conductive source region aligned with one side of the polygate; A highly concentrated second conductive drain region formed in the first conductive epitaxial layer at a predetermined distance from the other side of the polygate; A low concentration second conductive offset region formed in the first conductive epitaxial layer between the other side of the polygate and the second conductive drain region; A field oxide film formed on a surface of the low concentration second conductive offset region at a predetermined distance from the poly gate; A polyfield plate formed on the field oxide film; And a metal field plate connected to the polyfield plate while being connected to the source region, the present invention has the effect of minimizing the capacitance component between the drain region and the poly gate by forming a field oxide film in the offset region. In addition, the present invention has the effect of increasing the breakdown voltage by forming a polyfield plate connected to the source region on the field oxide film.

LDMOSFET, field plate, field oxide film, offset area

Description

Horizontal diffusion MOS transistor for high frequency power amplifier and its manufacturing method {LDMOSFET FOR RF POWER AMPLIFIERS AND METHOD FOR MANUFACTURING THE SAME}

1 is a view showing the structure of a horizontal diffusion MOS transistor according to the prior art,

2 is a view showing the structure of a horizontal diffusion MOS transistor according to an embodiment of the present invention;

3A to 3F illustrate a method of manufacturing a horizontal diffusion MOS transistor according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

21: p-type substrate 22: p-type epi layer

23: p-type sink 25: first offset region

26: field oxide film 27: gate oxide film

28: polygate 29: polyfield plate

30: secondary offset area 31: source area

32 drain region 33 source electrode

34: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to high performance silicon horizontal diffusion MOS transistors (LDMOSFETs) for high frequency power amplifiers.

In general, when an external system using a high voltage is controlled by an integrated circuit, an integrated circuit needs an element for high voltage control therein, and such a device requires a structure having a high breakdown voltage. That is, in the drain or the source of the transistor to which the high voltage is applied, the punch-through voltage between the drain and the source and the semiconductor substrate and the breakdown voltage between the drain and the source and the well or the substrate are It must be greater than the high voltage. In order to secure a breakdown voltage higher than the high voltage, a high voltage device having a modified latent MOSFET (LDMOSFET) structure, which is a modified MOSFET, is used, and the high diffusion device is used as a source. Since the drain and the drain are separated into a channel region and a drift region (or offset region), high breakdown voltage characteristics are exhibited.

1 is a view showing the structure of a horizontal diffusion MOS transistor according to the prior art.

Referring to FIG. 1, a p-type epitaxial layer 12 is grown on a p-type substrate 11, and a gate oxide film 13 and a gate electrode 14 are stacked on a surface of the p-type epitaxial layer 12. The source region 15 is formed in the p-type epitaxial layer 12 aligned with one side of the gate electrode 14. The drain region 16 is formed in the p-type epitaxial layer 12 at a predetermined distance from the other side of the gate electrode 14, and the p-type epitaxial layer 12 aligned with the other side of the gate electrode 14. An offset region 17 is formed inside. Here, the drain region 16 is formed in the offset region 17. In addition, a p-type sink (p ⁺ -sink) 18 for grounding is formed at one side of the source region 15.

Therefore, in the prior art, there is a channel region (region under the gate electrode) and an offset region 17 between the source region 15 and the drain region 16.

The horizontal diffusion MOS transistor is also referred to as a silicon power horizontal diffusion MOS transistor, and is applied to a power amplifier of a cellular base station.

However, the prior art has a problem that efficiency is not high by reducing the cutoff frequency and the maximum frequency fmax due to the gate-drain capacitance 19 which reduces the frequency characteristic. In addition, a small amount of current cannot obtain a high output voltage.

The present invention has been proposed to solve the above problems of the prior art, and relates to a horizontal diffusion morph transistor having a high efficiency and a high output voltage and a method of manufacturing the same.

Horizontal diffusion morph transistor of the present invention for achieving the above object is a first conductive type substrate on which the first conductive epitaxial layer is grown; A polygate formed on an upper surface of the first conductive epitaxial layer; A high concentration second conductive source region aligned with one side of the polygate; A highly concentrated second conductive drain region formed in the first conductive epitaxial layer at a predetermined distance from the other side of the polygate; A low concentration second conductive offset region formed in the first conductive epitaxial layer between the other side of the polygate and the second conductive drain region; A field oxide film formed on a surface of the low concentration second conductive offset region at a predetermined distance from the poly gate; A polyfield plate formed on the field oxide film; And a metal field plate connected to the source region and connected to the polyfield plate.

In addition, the method of manufacturing a horizontal diffusion morph transistor according to the present invention comprises the steps of: forming a primary offset region in a predetermined region of the first conductive epitaxial layer; Forming a field oxide film locally on the surface of the first offset region; Forming a polyfield plate on the field oxide layer while forming a polygate on a surface of the first conductive epitaxial layer at a predetermined distance from the first offset region; Forming a second offset region on the first conductive epitaxial layer between the other side of the polygate and one side of the field oxide film; Forming a drain region in the first conductive epitaxial layer on the other side of the field oxide layer while forming a source region aligned with one side of the polygate; Forming a metal field plate on the source region, the metal field plate overlapping the poly gate and electrically connected to the poly field plate; And forming a drain electrode connected to the drain region.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a diagram illustrating a structure of a horizontal diffusion MOS transistor according to an embodiment of the present invention.

Referring to FIG. 2, a predetermined region of a p-type substrate (p-sub) 21, a p-type epi layer (p-epi) 22, and a p-type epi layer 22 grown on the p-type substrate 21 is provided. A p-type sink (p ⁺ -sink) 23 having a depth in contact with the p-type substrate 21, a polygate 28, and a polygate 28 formed on a predetermined surface of the p-type epi layer 22. Source region 31 aligned with one side of and adjacent to p-type sink 23, drain region 32 and poly formed in p-type epi layer 22 at a predetermined distance from the other side of polygate 28. The offset regions 25 and 30 formed in the p-type epi layer 22 between the other side of the gate 28 and the drain region 32 and the offset regions 25 and 30 at a predetermined distance from the polygate 28. It includes a field oxide film 26 formed on the surface, a polyfield plate 29 formed on the field oxide film 26 and smaller in width than the field oxide film 26.

The gate oxide layer 27 is positioned below the poly gate 28, the source electrode 33 is connected to the source region 31, and the drain electrode 34 is connected to the drain region 32. Here, the source electrode 33 is also referred to as a metal field plate, and the length of the source electrode 33 is extended to cover the upper portion of the poly gate 28 and to approach one side of the field oxide layer 26. The source electrode 33 and the polyfield plate 29 are connected to each other.

In addition, the offset regions 25 and 30 are composed of a primary offset region 25 and a secondary offset region 30, and the impurity concentrations thereof include a source region 31 and a drain region doped with a high concentration of N-type impurities. Lower than (32). For example, an N-type impurity (N ⁻ ) of 1 × 10 ¹² atoms / cm ² level is doped. The primary offset region 25 is formed to have a wider width than the field oxide layer 26 under the field oxide layer 26, and the secondary offset region 30 is aligned with the other side of the polygate 28. Is formed.

According to FIG. 2, the first and second offset regions 25 and 30 are formed as a lightly doped N ⁻ region, thereby reducing the electric field concentrated on the drain region 32.

The source electrode 33 (ie, a metal field plate) overlapping the poly gate 28 and connected to the source region 31, and the field oxide layer 26 and the source electrode 33 grown in the offset region are electrically connected to the source region 31. The structure of the polyfield plate 29 is connected, in particular, the polyfield plate 29 increases the breakdown voltage by reducing the electric field concentrated at the edge of the polygate 26 toward the drain region 32, and the field oxide film 25 is drained. It serves to reduce the capacitance component between the region 32 and the polygate 28.

3A to 3F illustrate a method of manufacturing a horizontal diffusion MOS transistor according to an embodiment of the present invention.

As shown in FIG. 3A, the p-type epitaxial layer (epitaxial growth) is used on the p-type substrate 21 doped with p-type impurities having a concentration of 1x10 ¹⁹ atoms / cm ² . 22) grow. At this time, the p-type epi layer 22 is doped with boron having a concentration of 1 × 10 ¹⁶ atoms / cm ² , and the thickness thereof is 10 μm.

Subsequently, a p-type sink (p ⁺ -sink) 23 for RF ground with the p-type substrate 21 is formed in a predetermined region of the p-type epitaxial layer 22. At this time, the p-type sink 23 implants ions at a high concentration (1 × 10 ¹⁹ atoms / cm ² or more of boron) in order to have a low inductance component and a low resistance value, and high until it comes into contact with the p-type substrate 21. Drive in at temperature.

Subsequently, in order to adjust the threshold voltage of the horizontal diffusion MOS transistor, a threshold voltage adjustment ion implantation (Vt adjust implantation) 24 is performed in the channel region.

As shown in FIG. 3B, in order to reduce the electric field concentrated in the drain region, a 1st offset implantation is carried out at a low concentration (N ⁻ ) with n-type impurities in a region designated as an offset region, and then, as an offset region. The primary offset region 25 is formed in the predetermined p-type epi layer 22. At this time, the dose and length of the primary offset region 25 are set by optimizing the on-resistance value and the breakdown voltage of the horizontal diffusion MOS transistor. Therefore, the primary offset region 25 becomes an N ⁻ region into which a low concentration of N-type impurities are implanted.

As shown in FIG. 3C, a field oxide layer 26 is locally grown on the surface of the primary offset region 25. At this time, the field oxide film 26 is formed by a well-known LOCOS method.

The field oxide film 26 described above is a region that does not exist in the prior art and is intended to minimize the capacitance component between the drain region and the poly gate.

As shown in FIG. 3D, after the gate oxide film 27 is formed on the p-type epitaxial layer 22, polysilicon is deposited on the gate oxide film 27 to a thickness of 600 Å. Subsequently, gate patterning is performed to form a poly-si gate 28 made of polysilicon on the gate oxide layer 27. At this time, when the poly gate 28 is formed, a poly-si field plate 29 made of polysilicon is formed on the field oxide layer 26. Here, the polyfield gate 28 is smaller in width than the field oxide film 26.

As shown in FIG. 3E, the secondary offset region 30, the source region 31, and the drain region 32 are formed by a self-aligning process using the polygate 28 and the polyfield plate 29. As such, when the ion implantation is performed by the self-aligning process, the error generated when the mask is aligned can be minimized.

That is, ion implantation of low concentration N-type impurities using the polygate 28 and the polyfield plate 29 as the ion implantation barrier is performed to align the other side of the polygate 28 with one side of the field oxide film 26. The secondary offset region 30 is formed. Here, the primary offset region 25 and the secondary offset region 30 are lower than the impurity concentrations of the subsequent source region and the drain region. For example, it has a level of 1 × 10 ¹² atoms / cm ² .

Subsequently, a mask (not shown) covering the offset region, and ion implantation of a high concentration of N-type impurities using the polygate 28 and the polyfield plate 29 as ion implantation barriers are carried out to form one side of the polygate 28. While forming a source region 31 in contact with the P-type sink 23 and forming a drain region 32 aligned with the other side of the polyfield plate 29 (region outside the offset region).

As shown in FIG. 3F, the interlayer insulating film (not shown) is deposited, contacted, and metallized to form a source electrode 33 and a drain electrode 34 connected to the source region 31 and the drain region 32. Form. In this case, the source electrode 33 is connected to the source region 31 and overlaps with the upper portion of the poly gate 28 to extend to a side of the field oxide layer 26. The source electrode 33 is called a metal-field plate, and the source electrode 33 and the polyfield plate 29 are connected to each other through the metal line 35.

Therefore, the source electrode 33 is pulled out as a source S, a gate G for the polygate 26, and a drain D for the drain electrode 34.

According to the above-described embodiment, the first and second offset regions 25 and 30 are formed as a lightly doped N ⁻ region, thereby reducing the electric field concentrated on the drain region 32.

The source electrode 33 (ie, the metal field plate) connected to the source region 31 and overlapped with the poly gate 28 is electrically connected to the field oxide layer 26 and the source electrode 33 grown in the offset region. The structure of the polyfield plate 29 is connected, in particular, the polyfield plate 29 increases the breakdown voltage by reducing the electric field concentrated at the edge of the polygate 26 toward the drain region 32, and the field oxide film 25 is drained. It serves to reduce the capacitance component between the region 32 and the polygate 28.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The present invention described above has the effect of minimizing the capacitance component between the drain region and the poly gate by forming a field oxide film in the offset region.

In addition, the present invention has the effect of increasing the breakdown voltage by forming a polyfield plate connected to the source region on the field oxide film.

Claims (14)

A first conductive substrate on which the first conductive epitaxial layer is grown; A polygate formed on an upper surface of the first conductive epitaxial layer; A high concentration second conductive source region aligned with one side of the polygate; A highly concentrated second conductive drain region formed in the first conductive epitaxial layer at a predetermined distance from the other side of the polygate; A low concentration second conductive offset region formed in the first conductive epitaxial layer between the other side of the polygate and the second conductive drain region; A field oxide film formed on a surface of the low concentration second conductive offset region at a predetermined distance from the poly gate; A polyfield plate formed on the field oxide film; And A metal field plate connected to the source region and connected to the polyfield plate Horizontal diffusion MOS transistor comprising a. The method of claim 1, The offset region is, A first offset region formed below the field oxide film and having a wider width than the field oxide film; And Secondary offset region aligned with the other side of the polygate Horizontal diffusion MOS transistor comprising a. 3. The method of claim 2, And the offset region has a lower impurity concentration than the source and drain regions. The method of claim 1, The metal field plate may be connected to the source region and overlap the upper portion of the poly gate and have a length close to one side of the field oxide layer. The method of claim 1, And a first conductive sink adjacent to the source region and having a depth in contact with the first conductive substrate. 6. The method according to any one of claims 1 to 5, The first conductive type is doped with p-type impurities, the second conductive type is a horizontal diffusion MOS transistor, characterized in that doped with n-type impurities. Growing a first conductive epitaxial layer on the first conductive substrate; Forming a primary offset region in a predetermined region of the first conductive epitaxial layer; Forming a field oxide film locally on the surface of the first offset region; Forming a polyfield plate on the field oxide layer while forming a polygate on a surface of the first conductive epitaxial layer at a predetermined distance from the first offset region; Forming a second offset region on the first conductive epitaxial layer between the other side of the polygate and one side of the field oxide film; Forming a drain region in the first conductive epitaxial layer on the other side of the field oxide layer while forming a source region aligned with one side of the polygate; Forming a metal field plate on the source region, the metal field plate overlapping the poly gate and electrically connected to the poly field plate; And Forming a drain electrode connected to the drain region Method of manufacturing a horizontal diffusion MOS transistor comprising a. The method of claim 7, wherein And the first offset region and the second offset region have a lower impurity concentration than the source region and the drain region. The method of claim 7, wherein Forming the polygate and the polyfield plate, Forming a gate oxide film on the entire surface including the field oxide film; Depositing polysilicon on the gate oxide film; And Forming the polygate through gate patterning and simultaneously forming the polyfield plate on the field oxide layer Method of manufacturing a horizontal diffusion MOS transistor comprising a. 10. The method of claim 9, The polyfield plate is formed in a width smaller than the field oxide film manufacturing method of a horizontal diffusion MOS transistor. The method of claim 7, wherein The metal field plate is connected to the source region, overlapping the upper portion of the polygate, and a method of manufacturing a horizontal diffusion MOS transistor characterized in that it has a length close to one side of the field oxide film. The method of claim 7, wherein After growing the first conductive type epi layer, And forming a first conductive sink for ground on a portion of the first conductive epitaxial layer. The method of claim 12, The first conductive sink is formed in a depth in contact with the first conductive substrate, the manufacturing method of a horizontal diffusion MOS transistor. The method according to any one of claims 7 to 13, Wherein the first conductive type is doped with p-type impurities, and the second conductive type is doped with n-type impurities.

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