KR101147831B1 - Liquid crystal display of line on glass type - Google Patents

Abstract

The present invention provides a line on glass type liquid crystal display device capable of minimizing image degradation due to signal distortion.

The line-on-glass liquid crystal display according to the present invention comprises a liquid crystal panel having a liquid crystal cell matrix, at least two integrated circuits for driving the liquid crystal panel, and the liquid crystal panel for supplying an input driving signal to the integrated circuits. Signal lines directly formed on a substrate of the panel; And a current amplifier formed at an input end of each integrated circuit to amplify a current component of the input driving signal.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPLAY OF LINE ON GLASS TYPE}             

1 is a plan view illustrating a line-on glass liquid crystal display device.

FIG. 2 is a diagram for describing a horizontal stripe phenomenon in the liquid crystal display illustrated in FIG. 1.

3 is a diagram illustrating a LOG type liquid crystal display device according to a first embodiment of the present invention.

4 is a diagram illustrating the gate drive IC illustrated in FIG. 3 in detail.

FIG. 5 is a diagram illustrating the stage illustrated in FIG. 4 in detail.

FIG. 6 is a diagram for describing a voltage deviation between respective gate drive ICs reduced by the current amplifier shown in FIG. 4.

FIG. 7 is a diagram illustrating in detail a gate drive IC of a LOG type liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of main parts of drawing>

2,102: thin film transistor array substrate 4,104: color filter array substrate                 

6,106: liquid crystal panel 8,108: gate TCP

10,110: gate drive IC 12,112: data TCP

14,114: Data Drive IC 16,116: Data PCB

18,118: FPC 20,120: Main PCB

22,122: timing controller 24,124: power supply

26,126: LOG signal line group 32: horizontal line

150: stage 152: shift register

154: level shifter 156: buffer

158,164: current amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a line on glass type liquid crystal display capable of minimizing image degradation due to signal distortion.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the liquid crystal cells display an image by adjusting the light transmittance according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal display panel and the driving. And a power supply unit supplying power signals necessary for driving the circuits.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP in a chip on film (COF) method, and a liquid crystal display panel and a tape automated bonding (TAB) method. Electrically connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal display panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

Drive ICs mounted on a liquid crystal display panel in a COG method control signals from a timing controller mounted on a main PCB through line on glass (LOG) type signal lines formed on the FPC and the liquid crystal display panel. And power signals from the pixel data and the power supply unit.

Recently, even when the drive ICs are connected to the liquid crystal display panel via TCP, the LOG type signal lines are adopted to eliminate the PCB, thereby making the liquid crystal display device even thinner. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed in a LOG type on the liquid crystal display panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied. In this case, the gate control signals and the gate power signals supplied to the gate drive IC are distorted by the line resistance of the LOG signal lines, thereby causing a problem in that the quality of the image displayed on the liquid crystal display panel is degraded.

In detail, the LOG type liquid crystal display device in which the gate PCB is removed includes the main PCB 20 including the timing controller 22 and the power supply unit 24 and the main PCB (FPC 18) as shown in FIG. 1. A data PCB 16 connected to the 20, a data driver IC 14 mounted thereon, a data TCP 12 connected between the data PCB 16 and the liquid crystal display panel 6, and a gate driver IC 10; And a gate TCP 8 connected to the liquid crystal display panel 6.                         

The liquid crystal display panel 6 is formed by bonding the thin film transistor array substrate 2 and the color filter array substrate 4 to each other with a liquid crystal interposed therebetween. The liquid crystal display panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal display panel 6. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 18. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal display panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 are supplied to the data TCP 12 via the FPC 18 and the data PCB 16. . Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via the LOG signal line group 26 formed in the edge region of the thin film transistor array substrate 2. Gate control signals and power signals supplied to the gate TCP 8 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10, and the gate drive mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26. It is supplied to the IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 such as the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. DC drive voltages; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The LOG signal line group 26 is formed in a fine pattern by using the same gate metal layer as the gate lines in a limited pad region of the thin film transistor array substrate 2. Further, as the LOG signal line group 26 is contacted with the gate TCP 8 through ACF bonding, the contact portion A with the gate TCP 8 increases, resulting in a large contact resistance. Accordingly, the LOG signal line group 26 has a larger line resistance than the signal lines of the conventional gate PCB. Due to this line resistance, the gate control signals GSP, GSC, and GOE transmitted through the LOG signal line group 26 and the power signals VGH, VGL, VCC, GND, and VCOM are distorted, thereby causing horizontal stripes, spots, and the like. The deterioration of image quality such as crosstalk of the dot pattern, greenish, etc. becomes worse.

For example, the LOG signal line groups 26 that supply the gate control signals GSP, GSC, and GOE and the power signals VGH, VGL, VCC, GND, and VCOM may include the gate TCP as shown in FIG. And first to third LOG signal line groups LOG1 to LOG3 connected to each of them. Each of the first to third LOG signal line groups LOG1 to LOG3 has a line resistance (lΩ, mΩ, nΩ) proportional to the line length thereof, and is in series via the gate TCP 8 and the gate drive IC 10. Connected. Due to the first to third LOG signal line groups LOG1 to LOG3, gate control signals GSP, GSC, and GOE input to each gate drive IC 10 and power signals VGH, VGL, VCC, GND, VCOM) will cause a level difference. As a result, a luminance difference is generated between the horizontal line blocks A to C driven by the different gate drive ICs 10, resulting in horizontal stripes 32.

Specifically, the first gate drive IC 10 is provided with the first line resistance lΩ of the first LOG signal line group LOG1, and the second gate drive IC 10 is provided with the first and second LOG signal line groups. Due to the first and second line resistances (lΩ + mΩ) of LOG1 and LOG2, the third gate drive IC 10 includes the first to third of the first to third LOG signal line groups LOG1 to LOG3. Gate control signals GSP, GSC, GOE and voltage supply voltages VGH, VGL, VCC, GND, and VCOM that are voltage-dropped by the line resistance lΩ + mΩ + nΩ are supplied. Accordingly, as the difference between the gate signals VG1 to VG4 supplied to the gate lines of the first to third horizontal blocks A to C driven by the different gate drive ICs 10 occurs, the horizontal The horizontal stripes 32 are generated between the line blocks A to C. FIG.

The gate voltage difference in the unit of the gate drive IC 10 may be compensated using a method of increasing the cross sectional area of the LOG signal line group 26 in inverse proportion to the line length. However, since the outer region of the liquid crystal panel 6 in which the LOG signal line group 26 is formed is limited, there is a limit to increasing the cross-sectional area.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display device capable of minimizing image quality degradation due to signal distortion.

In order to achieve the above object, the line on glass type liquid crystal display device according to the present invention comprises a liquid crystal panel having a liquid crystal cell matrix, at least two integrated circuits for driving the liquid crystal panel, and input driving to the integrated circuits. Signal lines directly formed on a substrate of the liquid crystal panel to supply a signal; And a current amplifier formed at an input end of each integrated circuit to amplify a current component of the input driving signal.

The line on glass liquid crystal display may further include a second current amplifier formed at a first output line of each integrated circuit.                     

The integrated circuit may be a gate integrated circuit supplying a gate signal to a gate line formed on an excitation panel.

A singer line-on-glass liquid crystal display further includes an input line resistance that increases at a constant rate for each stage to at least one input line connected to input terminals of a plurality of stages that sequentially drive the gate lines in the gate integrated circuit. It is characterized by including.

The input line may be at least one of the gate high voltage input line and the gate low voltage input line.

The input line may be at least one of a plurality of gate control signal input lines.

The line on glass liquid crystal display may further include a data integrated circuit configured to supply a data signal to a data line formed to cross the gate line.

The input driving signal may be at least one of a high logic voltage of a gate signal, a low logic voltage of a gate signal, a base common voltage, a ground voltage, and a common voltage.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 7.                     

3 is a view showing a LOG type liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 3, the LOG type liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 106 having a liquid crystal cell matrix and a gate for driving gate lines GL of the liquid crystal panel 106. The timing controller for controlling the drive IC 110, the data drive IC 114 for driving the data lines DL of the liquid crystal panel 106, and the gate drive IC 110 and the data drive IC 114. And a power supply unit 124 for generating a driving voltage required for driving the liquid crystal display device.

The power supply unit 124 uses driving voltages (gate high voltage VGH, gate low voltage signal VGL, reference gamma voltage, and common voltage) required for driving the liquid crystal display using a voltage input from a system power supply (not shown). Voltage VCOM, etc.) are supplied to the timing controller 122, the data drive IC 114, the gate drive IC 110, and the like.

The timing controller 122 relays the video data R, G, and B from the graphics card and supplies the data drive IC 114. In addition, the timing controller 122 generates timing signals and control signals for controlling the timing of the data and gate drive ICs 114 and 110 in response to a control signal from the graphics card.

The liquid crystal panel 106 is formed by bonding the thin film transistor array substrate 102 and the color filter array substrate 104 to each other with a liquid crystal interposed therebetween. The liquid crystal panel 106 is provided with liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies a pixel signal from the data line DL to the liquid crystal cell in response to a scan signal from the gate line GL.

The data drive ICs 114 are connected to the data lines DL via the data TCP 112 and the data pad portion of the liquid crystal panel 106. The data drive ICs 114 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 114 transmit data control signals, pixel data, and power signals from the timing controller 122 and the power supply 124 on the main PCB 120 via the data PCB 116 and the FPC 118. Will be supplied.

The gate drive ICs 110 are connected to the gate lines GL via the gate TCP 108 and the gate pad portion of the liquid crystal panel 106. The gate drive ICs 110 sequentially supply a scan signal of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 110 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate gate control signals and power signals from the timing controller 122 and the power supply unit 124 are supplied to the data TCP 112 via the data PCB 116. Gate control signals and power signals supplied through the data TCP 112 are supplied to the gate TCP 108 via the LOG signal line group 126 formed in the edge region of the thin film transistor array substrate 102. Gate control signals and power signals supplied to the gate TCP 108 are input into the gate drive IC 110 through the input terminals of the gate drive IC 110 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 110 to be mounted on the next gate TCP 108 via the gate TCP 108 and the LOG signal line group 126. Supplied to the IC 110.

The LOG signal line group 126 is normally provided from a power supply unit (not shown) such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND, and a base driving voltage VCC. Gate power signals supplied; A signal line is provided to supply each of the gate control signals supplied from a timing controller (not shown), such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate enable signal GOE.

On the other hand, as the LOG signal line group 126 has a line resistance value in proportion to its line length, the gate driving signal decreases in proportion to the line length. The current amplifier 158 is provided at the input terminal of each gate drive IC 110 to compensate the voltage difference of the gate driving signal supplied to the gate drive IC 110 by the line resistance of the LOG signal line group 126. Is formed.

A current amplifier 158 is formed at the input of each gate drive IC 110 to increase the signal level of the first input line of each gate drive IC 110 so that the last output line of the previous gate drive IC 110 is increased by line resistance. Reduce the output stage of the

For example, the gate driving signal outputted through the last output terminals of the i th gate drive IC is mounted on the i + 1 th gate TCP 108 via the gate TCP 108 and the LOG signal line group 126. To the gate drive IC 110. At this time, the gate driving signal is reduced by the line resistance included in the LOG signal line group 126. The reduced gate drive signal compensates for the current component lowered by the line resistance through the current amplifier 158. The compensated gate driving signal is supplied to the first input terminal of the i + 1 th gate drive IC 110. Accordingly, the step difference between the gate driving voltage supplied to the last gate line of the i th gate drive IC 110 and the gate driving voltage supplied to the first gate line of the i + 1 th gate drive IC 110 is reduced. .

Meanwhile, the gate drive IC 110 includes first to kth stages 150 that sequentially drive k gate lines GL1 to GLk.

As shown in FIG. 4, the first to k-th stages 150 include a shift resist 152, a level shifter 154, and an output buffer 156 to sequentially drive the gate lines GL. do.

The shift register 152 shifts the gate start pulse signal GSP in response to the shift clock signal GSC to sequentially enable the gate line GL. In addition, when the enable operation of the gate lines GL of one frame is completed, a carry value is sent and the enable operation of the gate lines GL of the next frame is repeated. The current amplifier 158 described above is formed at an input terminal of the first shift register of each gate drive IC 110 among the shift registers 152.

The level shifter 154 sequentially shifts the scan pulse to be applied to the gate line GL and outputs the result to the buffer 156. That is, when the gate shift clock signal GSC is high logic, the scan logic VGH having a high logic is supplied to the buffer 156 in response to the gate enable signal GOE, and the gate shift clock signal GSC is In the low logic case, a low logic scan pulse VGL is supplied to the buffer 156 in response to the gate enable signal GOE.

The buffer 156 generates an output voltage having the same voltage level and polarity as the scan pulse input from the level shifter 154, suppresses the fluctuation of the output voltage, and supplies it to the gate line GL. Scan pulses output through the buffer 156 are sequentially supplied to the corresponding gate lines GL1 to GLk.

Compensation resistors R1 to Rk are formed between the first to k th stages so that the input line resistance increases at a constant rate in proportion to the lengths of the input lines 160 and 162 supplying the gate control signal and the gate power signal. In particular, a compensation resistor is formed in the input line 162 supplying the gate high voltage VGH and the gate low voltage VGL, which are directly supplied to each of the gate lines GL and directly affect the image quality. Accordingly, the gate control signal and the gate power signal, which are lowered in proportion to the first compensation resistor R1 than the first gate line GL1, are supplied to the second gate line GL2 through the second stage 150. The gate control signal and the gate power signal, which are voltage-dropped in proportion to the first and second compensation resistors R1 + R2, are supplied to the third gate line GL3 through the third stage 150. In this manner, the gate control signal and the gate power signal having the voltage drop in proportion to the line resistance of the input lines 160 and 162 connected to the input terminals of the fourth to kth stages are supplied to the fourth to kth gate lines GL4 to GLk. do. As a result, the input line resistance of the gate lines increases linearly in the gate drive IC, thereby not affecting the image quality. An attenuation resistor having a relatively larger resistance value than the sum of the LOG type line resistance may be formed at an input terminal of the first gate drive IC 110.

As described above, the liquid crystal display according to the first exemplary embodiment of the present invention includes the gate signal supplied to the last gate line GL of the i th gate drive IC 110 and the i + 1 th gate drive IC 110. The deviation ΔV of the gate signal supplied to the first gate line GL is reduced as shown in FIG. 6. Therefore, the luminance difference between the gate drive ICs 110 can be prevented, thereby preventing the occurrence of horizontal streaks between horizontal line blocks.

7 is a diagram illustrating a LOG type liquid crystal display device according to a second embodiment of the present invention.

The LOG type liquid crystal display shown in FIG. 7 has the same configuration except that a second current amplifier 164 is further provided at the first output terminal of each gate drive IC 110 as compared to the liquid crystal display shown in FIG. 3. With elements. Accordingly, detailed description of the same components will be omitted.

The second current amplifier 164 is positioned at an output terminal of the first stage of each gate drive IC 110. That is, the second current amplifier 164 is positioned after the buffer of the first stage. The second current amplifier 164 increases the signal level of the first output line of each gate drive IC 110 to reduce the output step with the last output line of the previous gate drive IC 110 by line resistance.                     

An operation process of the gate drive IC 110 having the second current amplifier 164 is as follows. The gate driving signal output through the last output terminals of the i th gate drive IC 110 is mounted on the i + 1 th gate TCP 108 via the gate TCP 108 and the LOG signal line group 126. Supplied to the gate drive IC 110. At this time, the gate driving signal is reduced by the line resistance included in the LOG signal line group 126. The reduced gate driving signal compensates for the current component lowered by the line resistance through the first current amplifier 158. The compensated gate driving signal is supplied to the first input terminal of the i + 1 th gate drive IC 110. The i + 1 th gate drive IC 110, to which the compensated gate driving signal is input, supplies the gate high voltage VGH and the gate low voltage VGL to the gate line GL. In particular, the gate low voltage VGL and the gate high voltage VGH of which the current is amplified by using the second current amplifier 164 are supplied to the first gate line of each gate drive IC 110. Accordingly, the gate driving voltage supplied to the last gate line GL of the i th gate drive IC 110 and the gate driving supplied to the first gate line GL of the i + 1 th gate drive IC 110 are defined. The step with voltage is reduced.

As described above, the LOG type liquid crystal display according to the present invention forms a current amplifier at an input terminal of each gate drive IC. Accordingly, the liquid crystal display according to the first exemplary embodiment of the present invention provides a gate signal supplied to the last gate line of the i-th gate drive IC and a gate signal supplied to the first gate line of the i + 1 th gate drive IC. The deviation of is reduced. Therefore, the luminance difference between the gate drive ICs can be prevented, thereby preventing the occurrence of horizontal streaks between horizontal line blocks.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A liquid crystal panel having a liquid crystal cell matrix, At least one gate integrated circuit and data integrated circuit for driving the liquid crystal panel; Signal lines directly formed on a substrate of the liquid crystal panel to supply an input driving signal to the gate integrated circuits; A current amplifier formed at an input terminal of each gate integrated circuit to amplify a current component of the input driving signal, The gate integrated circuit includes a plurality of stages, each of the plurality of stages having a shift resist, a level shifter and an output buffer, And the current amplifier is provided at an input terminal of a first shift resist of each gate integrated circuit. The method of claim 1, And a second current amplifier formed at a first output line of each integrated circuit. The method of claim 1, And the gate integrated circuit supplies a gate signal to a gate line formed on the liquid crystal panel. The method of claim 3, wherein And at least one input line connected to an input terminal of a plurality of stages sequentially driving the gate lines in the gate integrated circuit, further comprising an input line resistance increasing at a constant rate for each stage. Glass type liquid crystal display device. The method of claim 4, wherein And the input line is at least one of the gate high voltage input line and the gate low voltage input line. The method of claim 5, And the input line is at least one of a plurality of gate control signal input lines. The method of claim 3, wherein And the data integrated circuit supplies a data signal to a data line formed to intersect the gate line. The method of claim 1, And the input driving signal is at least one of a high logic voltage of a gate signal, a low logic voltage of a gate signal, a base common voltage, a ground voltage, and a common voltage.

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