KR101149572B1 - Nonvolatile memory device with staggered tunnel barrier - Google Patents

Abstract

A nonvolatile memory device having a staggered tunnel barrier insulating film having high speed characteristics and long data retention characteristics is provided. The device includes a semiconductor substrate, a source and drain region formed on the substrate, and a gate structure formed on the semiconductor substrate in contact with the source and drain region, the gate structure using a silicon nitride film (Si ₃ N ₄ ), A first tunneling insulating film having a thickness of 4 nm or less and a second tunneling insulating film having a thickness of 5 nm or less of hafnium oxide (HfO ₂ ) are stacked on the first tunneling insulating film to form a staggered tunnel barrier insulating film. A charge accumulation layer formed on the tagger tunnel barrier insulating film, a blocking insulating film formed on the charge accumulation layer, and a gate electrode layer formed of the metal material while being formed on the blocking insulating film.

Nonvolatile Memory, Stagger Tunnel Barrier, Silicon Nitride, Blocking Insulation

Description

Nonvolatile memory device with staggered tunnel barrier

The present invention relates to a nonvolatile memory device having an ultra-thin staggered tunnel barrier insulating film and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor fabrication capable of reading, writing, and storing electrical information, and having high-capacity and high-density features, and capable of high-speed write / erase operations, and having a high dielectric constant having a high dielectric constant on a semiconductor substrate. The present invention relates to a memory device having a tunneling insulating film employing a laminated structure of dielectric films.

The present invention is derived from a study performed by the Kwangwoon University Industry-Academic Cooperation Group with the support of the Ministry of Knowledge Economy. [Task unique number: 10029946, Title: Development of high reliability TBE-NFGM device]

Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices according to data storage methods. Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory includes dynamic random access memory (DRAM) or static random access memory (SRAM). On the other hand, the nonvolatile memory device retains data even when power is not supplied. Representative examples of the nonvolatile memory device include flash memory devices.

Such flash memory is widely used as a personal communication device such as a mobile phone that requires mobility to be portable, various small electronic devices such as USB memory, MP3, and PMP, and a data storage device such as a digital voice recorder or a memory card. have.

In particular, NAND (NOT-AND) flash memory, which is used in mobile phones, MP3s, digital cameras, and USB memories, is a representative nonvolatile memory device that solves a disadvantage of volatile operation of a DRAM (Dynamic Random Access Memory) device.

As such, flash memory has started to be used as a main memory device for portable devices due to its nonvolatile and low power consumption. In particular, the demand for flash memory is rapidly increasing as a mass storage medium such as digital home appliances due to its higher density than DRAM.

Flash memory technology, on the other hand, is not only a technical advantage of EPROM (Erasable-Programmable Read-Only Memory) and EEPROM (Electrically Erasable-Programmable Read-Only Memory), but also a memory with both DRAM and Read-Only Memory (ROM). to be. In particular, it has a higher density than the density of DRAM and ROM, and can rewrite the storage contents as necessary, such as EPROM or DRAM, and has both non-volatile ROM and EEPROM. NAND-type flash memory, which is currently commercialized, is 2 gigabytes in density, has a slow storage and erase time of several tens of us, and operates at a high supply voltage of 10V to 20V.

Current flash memories have a structure in which an oxide film, a floating gate, and an oxide film are inserted between a gate electrode and a channel based on a metal-oxide semiconductor field effect transistor (MOSFET) structure. The operation principle of such a flash memory device is to use a change in the threshold voltage of a transistor depending on whether or not charge is injected into a floating gate made of polysilicon.

Typically, once data has been written to a nonvolatile memory, the time to retain that data is more than 10 years. In order to store electrons in the floating gate during this period, there is a limit to thinning the thickness of the tunneling oxide film. The thickness of the current tunneling oxide layer of the flash memory device is 7 nm to 8 nm, which is a thickness that cannot inject or remove electrons by tunneling directly to the floating gate. Therefore, other methods are used to inject or remove electrons into the floating gate for speed improvement and low power operation.

Typically, channel hot-electron (CHE) injection or Fowler-Nordheim (F-N) tunneling is used instead of direct tunneling to store or remove electrons in nonvolatile memory. For this reason, high operating voltages are required for the storage and removal of electrons.

Current flash memories have a storage and erase voltage of more than 10V, which is very large compared to complementary metal-oxide-semiconductor (CMOS) driving voltages. This causes defects in the tunneling oxide film due to the high voltage and causes the performance of the memory device to deteriorate. Therefore, it is expected that more serious problems will occur when the cell size of the flash memory becomes smaller.

In addition, since the conventional flash memory uses a floating gate made of polysilicon as a storage electrode, interference occurs between adjacent gates when high integration, and stored charge can move freely through polysilicon, so that if there is a defect in the oxide film, The disadvantage is that all stored charges leak out.

1 illustrates a cross-sectional structure of a charge trapping nonvolatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) type, which is a charge trapping nonvolatile memory manufactured to solve such a problem.

Referring to FIG. 1, a tunneling insulating film made of a silicon oxide film, a charge trap layer made of a silicon nitride film, a blocking insulating film made of a silicon oxide film, and a gate electrode layer of polysilicon are sequentially stacked on a semiconductor channel. SONOS-type charge trap type nonvolatile memory eliminates interference problems caused by floating gate memory below 40 nm and has discrete traps to improve the reliability of memory devices. Has its drawbacks.

First, the tunneling insulating layer composed of a single layer of silicon oxide has a non-volatile property due to an increase in direct tunneling and stress induced leakage current when the thickness is reduced to improve the operation speed. It is not possible to secure the data retention characteristics of more than 10 years that memory should have. When the thickness of the tunneling insulating film composed of a single layer of silicon oxide film is increased to achieve data retention characteristics, there is a disadvantage in that deterioration of data recording / erasing characteristics occurs.

Second, since the charge trap layer made of a silicon nitride film has a high process temperature, the application of the tunneling insulating film of the high dielectric film having a low allowable process temperature is limited.

Third, since the blocking insulating layer made of the silicon oxide film has a low dielectric constant, the voltage for forming charge in the channel is high, which hinders the low voltage and high speed of the memory device.

Fourthly, the gate electrode using polycrystalline silicon has a low work function, and thus, since the holes injected from the silicon substrate side to cancel data are canceled by the electrons injected from the control gate, the erase speed may not be slowed or completely erased. have.

2 is a cross-sectional view showing the structure of a conventional SONOS type charge trapping nonvolatile memory device having a single layer of tunneling insulating film.

FIG. 3A shows an energy band diagram in thermal equilibrium with respect to the cross-sectional structure in the A-A 'direction of the SONOS memory element of FIG. 2.

Referring to FIG. 3A, since the Fermi level is constant in the entire system, the energy bands of the semiconductor substrate doped with the P-type and the control gate electrode doped with the N-type are bent in the thermal equilibrium state as shown in FIG. .

Referring to FIG. 3B, a high voltage is applied to the semiconductor substrate as compared to the control gate electrode of the SONOS memory device in the erase mode. As shown in FIG. 3B, the thermal equilibrium state is broken by an external applied voltage so that the Fermi level E _fn of the electrode rises higher than the Fermi level of the semiconductor substrate, and the tunneling insulating layer 22 and the charge trap layer 23 are formed. ), The conduction band of the blocking insulating film 24 is deformed.

In this erase operation, electrons stored in the charge trap layer 23 are tunneled through the tunneling insulating layer 22 and injected into the semiconductor substrate, thereby performing data erasing. However, since the hole injection is not easy and the work function of the polysilicon is low, the electron is injected into the charge trapping layer by tunneling the blocking insulating film from the electrode, so that it takes a long time to lower the threshold voltage, which results in a long data erasing time. Is generated.

As these problems are solved, and as the memory devices are highly integrated, new device structures and manufacturing process technologies are required to simultaneously secure fast write / erase operations and data retention characteristics of 10 years or more.

In current nonvolatile memory, the voltage stored and erased is very large. This causes defects in the tunneling oxide film due to the high voltage and causes the performance of the memory device to deteriorate. Therefore, it is expected that more serious problems will occur when the cell size of the flash memory becomes smaller.

In order to solve the above problems, by improving the material and structure of the tunneling insulating film of the conventional nonvolatile memory, a nonvolatile memory device having a high speed at a low voltage at the time of writing / erasing and simultaneously improving data retention characteristics and a manufacturing method thereof of

To provide.

In order to solve the above problems, a semiconductor memory device comprising a semiconductor substrate, a source and drain region formed on the substrate and a gate structure formed on the semiconductor substrate in contact with the source and drain regions, the gate structure is silicon nitride film (Si ₃ N ₄₎ to use, and by laminating a first tunnel insulating film, the first second tunnel insulating film of hafnium oxide (HfO ₂₎ in the tunnel insulating film as 5nm or less thick than the thickness 4nm staggered tunnel barrier (staggered tunnel barrier) insulating film, the charge accumulation layer formed on the staggered tunnel barrier insulating film, a blocking insulating film formed on the charge accumulation layer, and a gate electrode layer formed on the blocking insulating film using a metal material Non-volatile with a staggered tunnel barrier characterized in that The memory device is provided.

Forming a source and a drain on the semiconductor substrate to solve the above another problem; Forming a first tunneling insulating film made of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 4 nm or less while contacting a source and a drain on the substrate; Stacking a second tunneling insulating film including a hafnium oxide film (HfO ₂ ) having a thickness of 5 nm or less on the first tunneling insulating film to form a staggered tunnel barrier insulating film including the first tunneling insulating film and the second tunneling insulating film; Forming a charge accumulation layer on the staggered tunnel barrier insulating film; Forming a blocking insulating layer on the charge accumulation layer; A method of manufacturing a nonvolatile memory device having a staggered tunnel barrier is provided, including forming a gate electrode layer on the blocking insulating layer using a metal material.

The nonvolatile memory employing the staggered tunnel barrier structure according to the present invention can be expected to simultaneously improve the write / erase characteristics and the data retention characteristics.

Hereinafter, a nonvolatile memory device employing a staggered tunnel barrier structure and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that detailed descriptions of related well-known technologies or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to a client's or operator's intention or custom. Therefore, the definition should be based on the contents throughout this specification.

4 is a cross-sectional view illustrating a structure of a nonvolatile memory device having an ultra-thin staggered tunner barrier using Si ₃ N ₄ and HfO ₂ according to the present invention.

In the state where the source and drain 21 are provided on the substrate 20, the first tunneling insulating film 22 and the second tunneling insulating film 23 are sequentially formed thereon. Two thin films of the first tunneling insulating film 22 and the second tunneling insulating film 23 form a staggered tunnel barrier insulating film 27.

The charge accumulation layer 24 is formed on the staggered tunnel barrier insulating film 27, and the blocking insulating film 25 is formed thereon. A metal gate electrode layer 26 using a metal material is formed on the blocking insulating film 25. Throughout this specification, metal gates will be used interchangeably with control gates.

Sources and drains formed by thin silicon films doped on silicon substrates facilitate the formation of the very shallow junctions required in microdevices.

A device in which a staggered tunnel barrier insulating film 27 as shown in FIG. 4 is formed on the semiconductor substrate 20 by stacking a first tunneling insulating film and a second tunneling insulating film having different permittivity and conduction band energy levels, and having different dielectric constants. Improves the sensitivity of the electric field and reduces the effective tunneling thickness of electrons and holes. Therefore, a fast write / erase speed can be obtained even at a low gate voltage, and the reliability of the device can be improved due to the reduction of stress applied to the tunneling insulating layer even during frequent write / erase operations.

Although the ultra thin staggered tunnel barrier insulating film 27 and the conventional single layer tunneling insulating film are the same electrical thickness, the physical thickness of the ultra thin staggered tunnel barrier insulating film 27 is increased. Increasing the physical thickness of the tunneling insulating layer means a reduction of the leakage current, thereby improving data retention characteristics. Throughout this specification, ultra-thin staggered tunnel barrier insulating film and tunneling insulating film are used to refer to the same film.

The charge accumulation layer 24 is formed on the ultra-thin staggered tunnel barrier insulating layer 27. The charge accumulation layer 24 may include at least one of a floating gate using polysilicon, a nano floating gate having a metal, semiconductor, or oxide nanocrystal, or at least one of HfO ₂ , ZrO _2, and Si ₃ N ₄ . It can be formed including one.

The nanocrystalline floating gate or charge trap layer has a function of data writing and data erasing by hole traps by trapping electrons passing through the tunneling insulating layer 27, and enables the electric field of the control gate to be effectively applied to the channel and the tunneling insulating layer. .

The blocking dielectric layer 25 having a high dielectric constant and a large band gap formed on the nanocrystalline floating gate or the charge trap layer prevents electrons trapped in the charge accumulation layer from escaping to the control gate, and the nanocrystalline floating gate or By forming the electric field well so as to be trapped in the charge or charge trap layer, it functions to improve data retention characteristics. In addition, the electric field of the control gate is effectively applied to the channel and the tunneling insulating film.

The gate electrode layer 26 formed on the blocking insulating layer 25 applies a voltage to operate the device.

The staggered tunnel barrier according to an embodiment of the present invention may be applied to various nonvolatile memory devices.

In the case of the charge trap type nonvolatile memory device, the tunneling insulating film 27 may be applied instead of the conventional single layer insulating film. In addition, the non-volatile memory device structure of the conventional floating gate using polysilicon or the floating gate using nanocrystals may be applied as a tunneling insulating layer.

In the nonvolatile memory device, the tunneling insulating layer must satisfy two conditions. Firstly, the recording / erasing characteristics should be improved because they are more sensitive to electric fields than conventional SiO ₂ single layer tunneling insulating films. Second, the memory effect by the tunneling insulating film should be minimized by suppressing trapping of electrons or holes in the tunneling insulating film.

When the tunneling insulating layer 27 was formed, the trap characteristic according to the thickness was confirmed through experiments, and the energy band diagram and the current-voltage (I-V) characteristic during the write / erase operation of the device were confirmed through the simulation.

5 is a cross-sectional view of a device for experiment and simulation of a nonvolatile semiconductor device employing a staggled tunnel barrier insulating film according to the present invention.

After the first tunneling insulating layer 31 and the second tunneling insulating layer 32 were sequentially formed on the silicon semiconductor substrate 30, the gate electrode 33 was formed on the second tunneling insulating layer 30.

6A illustrates a CV hysteresis curve according to the thickness of Si ₃ N ₄ experimentally obtained in the device structure of FIG. 5 according to the present invention.

Referring to FIG. 6A, when the voltage applied to the electrode is changed from -1.2 V to +1.2 V, the change amount of the flat band voltage can be seen. The first tunneling insulating layer 31 was formed of SiO ₂ to a thickness of 2 nm by a thermal oxide film method, and Si ₃ N ₄ was deposited by a low pressure chemical vapor deposition (LPCVD) method.

The Si ₃ N ₄ thickness is 6.7 nm, 6 nm, 5 nm, and 4 nm, and the Si ₃ N ₄ thickness decreases from 5 nm to 4 nm, and the flat band voltage spacing is greatly reduced. Through this, it can be seen that the trap amount of charge decreases rapidly as the thickness of Si ₃ N ₄ decreases from 5 nm to 4 nm, and below 3 nm, there is no influence of the charge trap due to the tunnel barrier. .

Figure 6b shows the CV hysteresis curve according to the thickness of HfO ₂ experimentally obtained in the device structure of Figure 5 according to the present invention.

Referring to FIG. 6B, when the voltage applied to the electrode is changed from -5 V to +5 V and +5 V to -5 V, the variation in the flat band voltage can be seen. The first tunneling insulating layer 31 was formed by SiO ₂ to a thickness of 2 nm by a thermal oxide film method, HfO ₂ thickness was deposited by ALD (atomic layer deposition) method of 17.9 nm, 11.6 nm, 4.3 nm. Similar to Si ₃ N ₄ , as the thickness decreases, the flat band voltage interval decreases. In particular, when the thickness of HfO ₂ is 5 nm or less, it can be seen that the amount of change in the flat band voltage is greatly reduced. Therefore, in the case of the HfO ₂ film, as in Si ₃ N ₄ , it can be seen that the trap amount decreases rapidly as the thickness decreases.

FIG. 7A shows an energy band diagram in a write operation through simulation in the device structure of FIG. 5 according to the present invention. Referring to FIG. 7A, a dotted line represents an SiO ₂ single layer tunneling insulating film and a solid line is an ultra-thin staggered tunnel barrier insulating film according to the present invention in which Si ₃ N ₄ and HfO ₂ are stacked.

In this case, the energy band diagram in the write operation when the same voltage is applied to the electrode is shown. The thinner staggered tunnel barrier insulating film than the SiO ₂ single layer tunneling insulating film has a thinner effective thickness at which electrons are tunneled, so that a larger current flow can be expected.

FIG. 7B illustrates an energy band diagram of an erase operation by simulating the device structure of FIG. 5 according to the present invention.

Referring to FIG. 7B, the dotted line as in FIG. 7A is a SiO ₂ single layer tunneling insulating layer.

The solid line is an ultra-thin staggered tunnel barrier insulating film in which Si ₃ N ₄ and HfO ₂ are stacked.

In this case, the energy band diagram in the erase operation when the same voltage is applied to the gate is shown. In the ultra-thin staggered tunnel barrier insulating film than the SiO ₂ single-layer tunneling insulating film, the effective thickness of the holes (tuned) is thinner can be expected to flow a larger current.

7A and 7B, it can be seen that the ultra-thin staggered tunnel barrier insulating film has an increased sensitivity of the tunneling current at the same voltage than the SiO ₂ single-layer tunneling insulating film at the same thickness.

FIG. 8 illustrates simulation results of IV characteristics by setting a physical oxide thickness (POT) of the tunneling insulating layer 40 to 5 nm in the device structure of FIG. 5 according to the present invention. The thickness of the insulating film used in the calculation was Si ₃ N ₄ / HfO ₂ = 1 nm / 4 nm, Si ₃ N ₄ / HfO ₂ = 2 nm / 3 nm, and Si ₃ N ₄ / HfO ₂ = 3 nm / 2 nm It was set as. In addition, IV characteristics were simulated for 5 nm single layer SiO ₂ for comparison with the ultra-thin staggered tunnel barrier insulating film 40.

In the above simulation, the program operation indicates the amount of change in electron current when a voltage from 0 V to +10 V is applied, and the erase operation when a voltage from 0 V to -10 V is applied. The amount of change in hole current is shown.

Simulation results show that the ultra-thin staggered tunnel barrier insulating film 40 at the same physical thickness has a much larger current flow at the same voltage than the single-layer SiO ₂ tunneling insulating film. It can be seen that is larger.

In addition, when the thickness of Si ₃ N ₄ (31) decreases and the thickness of HfO ₂ (32) increases, a larger amount of current can be confirmed at high voltage. As a result, when the ultra-thin staggered tunnel barrier insulating film is formed than the single layer SiO ₂ tunneling insulating film, it can be seen that the write / erase voltage can be lowered and the operation speed can be further improved.

FIG. 9 is a graph illustrating simulated I-V characteristics of a case where an equivalent oxide thickness (EOT) of the tunneling insulating layer 40 is 1.5 nm in the device structure of FIG. 5 according to the present invention.

The thickness of each insulating film used for the calculation was set to Si ₃ N ₄ / HfO ₂ = 2 nm / 4 nm and Si ₃ N ₄ / HfO ₂ = 3 nm / 1 nm. In addition, IV characteristics were simulated for a single layer SiO ₂ having a thickness of 1.5 nm for comparison with the ultra-thin staggered tunnel barrier insulating film 40.

Simulation results show that similar currents can be seen at high voltages during program operation, but at higher voltages, higher currents can be seen in single-layer SiO ₂ tunneling insulating films. In the erase operation, it can be seen that the ultra-thin staggered tunnel barrier insulating film 40 shows a large amount of current at a high voltage and a small amount of current at a low voltage.

In the physical thickness (POT) is thickest Si ₃ N ₄ deposited by the device 31 to _{2 nm, HfO 2 (32)} 4 nm This small amount of current low voltage, the high voltage showed a large amount of current. This result indicates that a small amount of current at a low voltage means a decrease in leakage current, and a large amount of a current at a high voltage means an improvement in write / erase characteristics.

FIG. 10 illustrates IV characteristics by fixing the thickness of HfO ₂ (32) to 3 nm and depositing Si ₃ N ₄ (31) to 1 nm, 2 nm, and 3 nm in the device structure of FIG. 5 according to the present invention. A graph showing one result.

Simulation results showed that as the thickness of Si ₃ N ₄ (31) decreased, a large amount of current was shown at a high voltage and a similar amount of current was shown at a low voltage.

FIG. 11 illustrates IV characteristics by fixing the thickness of Si ₃ N ₄ (31) to 2 nm and depositing HfO ₂ (1), 1 nm, 3 nm, and 5 nm in the device structure of FIG. 5 according to the present invention. A graph showing the results.

Simulation results showed that as the thickness of HfO ₂ (32) was increased, the current was lower at low voltage and similarly at high voltage.

As a result of the simulation results, as in the present invention, the tunneling insulating film is formed of a laminated high-k dielectric film instead of a single layer of SiO ₂ , thereby confirming that a small amount of current flows at a low voltage and a large amount of current flows at a high voltage. It was. This reduces leakage current and improves data retention while simultaneously improving write / erase characteristics. In addition, the characteristics of the nonvolatile memory device may be optimized according to the thickness of the tunneling insulating layer.

12 is a flowchart illustrating a method of manufacturing a nonvolatile memory device employing a staggered tunnel barrier insulating film according to the present invention in detail. Referring to FIG. 4, the device manufacturing method according to FIG. 12 will be described with reference to FIG. 4.

First, a source and a drain 21 are formed on the semiconductor substrate 20 (1210).

The first tunneling insulating layer 22 made of a silicon nitride film Si ₃ N ₄ is formed on the semiconductor substrate while being in contact with the source and drain 21 (1220).

A staggered tunnel barrier insulating film including the first tunneling insulating film and the second tunneling insulating film by stacking a second tunneling insulating film 23 including a hafnium oxide film HfO ₂ having a thickness of 5 nm or less on the first tunneling insulating film 22. (27) is formed (1230).

The second tunneling insulating layer may include at least one of materials consisting of ZrO ₂ , HfSiOx, ZrSiOx, and La ₂ O ₃ instead of the hafnium oxide layer HfO ₂ .

The charge accumulation layer 24 is formed on the staggered tunnel barrier insulating layer 27 (1240). The charge accumulation layer may include at least one of a floating gate using polysilicon, a nano floating gate having a metal, semiconductor, or oxide nanocrystal, or at least one of HfO ₂ , ZrO _2, and Si ₃ N ₄ . It is characterized by including the.

When the charge accumulation layer is formed, the charge accumulation layer may be formed through an atomic layer deposition (ALD) method.

Next, a blocking insulating layer 25 is formed on the charge accumulation layer 24 (1250).

Finally, forming a gate electrode layer 26 made of a metal material on the blocking insulating layer 25 may include manufacturing a nonvolatile memory device having a staggered tunnel barrier.

In addition, the nonvolatile memory device may further include a step (not shown) of performing heat treatment at a temperature of 300 ° C. to 500 ° C. in the presence of hydrogen.

The nonvolatile memory device employing the ultra-thin staggered tunnel barrier insulating film has been described above. In the nonvolatile memory device employing the ultra-thin staggered tunnel barrier insulating film according to the present invention, the materials and structures of the tunneling insulating film, the charge storage layer and the blocking insulating film have been improved, and thus the write / erase characteristics and the data retention characteristics can be simultaneously improved. have. According to the present invention, it is possible to fabricate a high-density memory having a high performance and very small channel that requires low power and high speed operation.

As described above, the present invention has been described based on the preferred embodiments, but these embodiments are intended to illustrate the present invention, not to limit the present invention, so that those skilled in the art to which the present invention pertains can practice the above without departing from the technical spirit of the present invention. Various changes, modifications or adjustments to the example will be possible. Therefore, the protection scope of this invention will be limited only by the appended claims, and should be construed as including all changes, modifications or adjustments.

1 is a cross-sectional view of a structure of a charge trapping nonvolatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) type according to the prior art.

2 is a cross-sectional view showing the structure of a conventional SONOS type charge trapping nonvolatile memory device having a single layer of tunneling insulating film.

3 is an energy band diagram in thermal equilibrium with respect to the cross-sectional structure in the A-A 'direction of the SONOS memory device of FIG.

4 is a cross-sectional view illustrating a structure of a nonvolatile memory device having an ultra-thin staggered tunner barrier using Si 3 N 4 and HfO 2 according to the present invention.

FIG. 5 is a cross-sectional view of a device structure for experiment and simulation of a nonvolatile semiconductor device employing a staggered tunnel barrier insulating film according to the present invention.

FIG. 6A is a graph of a CV hysteresis curve according to the thickness of Si ₃ N ₄ experimentally obtained in the device structure of FIG. 5 according to the present invention. FIG.

FIG. 6B is a graph showing a CV hysteresis curve according to the thickness of HfO ₂ experimentally obtained in the device structure of FIG. 5 according to the present invention. FIG.

FIG. 7A shows an energy band diagram in a write operation through simulation in the device structure of FIG. 5 in accordance with the present invention. FIG.

FIG. 7B is an energy band diagram of an erase operation by simulating the device structure of FIG. 5 according to the present invention.

FIG. 8 illustrates simulation results of I-V characteristics using a physical oxide thickness (POT) of the tunneling insulating film 40 as 5 nm in the device structure of FIG. 5 according to the present invention.

FIG. 9 is a graph illustrating simulated I-V characteristics of a case where an equivalent oxide thickness (EOT) of the tunneling insulating layer 40 is 1.5 nm in the device structure of FIG. 5 according to the present invention.

FIG. 10 illustrates IV characteristics by fixing the thickness of HfO ₂ (32) to 3 nm and depositing Si ₃ N ₄ (31) to 1 nm, 2 nm, and 3 nm in the device structure of FIG. 5 according to the present invention. A graph showing one result.

FIG. 11 illustrates IV characteristics by fixing the thickness of Si ₃ N ₄ (31) to 2 nm and depositing HfO ₂ (1), 1 nm, 3 nm, and 5 nm in the device structure of FIG. 5 according to the present invention. A graph showing the results.

12 is a detailed flowchart illustrating a method of fabricating a nonvolatile memory device employing a staggered tunnel barrier insulating film according to the present invention.

Claims (8)

A semiconductor memory device comprising a semiconductor substrate, a source and drain region formed on the substrate, and a gate structure formed on the semiconductor substrate in contact with the source and drain region, wherein the gate structure includes: The first tunneling insulating film and the second tunneling insulating film having different dielectric constants are formed by laminating, and the conduction band energy level and valence band energy level of the second tunneling insulation film are respectively higher than the conduction band energy level and valence band energy level of the first tunneling insulation film. Low staggered tunnel barrier insulation film, A charge accumulation layer formed on the staggered tunnel barrier insulating film, A blocking insulating film formed on said charge storage layer, and And a gate electrode layer formed on the blocking insulating layer and using a metal material. The method of claim 1, wherein the charge accumulation layer Floating gate using polysilicon, Nano floating gates having metal, semiconductor or oxide nanocrystals, or A nonvolatile memory device having a staggered tunnel barrier, characterized in that it comprises at least one of a charge trap layer comprising at least one of HfO ₂ , ZrO _2, and Si ₃ N ₄ . The method of claim 1, The first tunneling insulating film is formed of a silicon nitride film, The second tunneling insulating layer is formed of at least one of a material consisting of a hafnium oxide (HfO ₂ ), ZrO ₂ , HfSiOx, ZrSiOx, La ₂ O ₃ Non-volatile memory device having a staggered tunnel barrier . Forming a source and a drain on the semiconductor substrate; Forming a first tunneling insulating film on the substrate; A second tunneling insulating layer having a dielectric constant different from that of the first tunneling insulating layer is formed by stacking on the first tunneling insulating layer, wherein the conduction band energy of the second tunneling insulating layer and the valence band energy level of the second tunneling insulating layer are respectively. Forming a staggered tunnel barrier insulating film including the first tunneling insulating film and the second tunneling insulating film by lowering the level and the valence band energy level; Forming a charge accumulation layer on the staggered tunnel barrier insulating film; Forming a blocking insulating layer on the charge accumulation layer; And And forming a gate electrode layer on the blocking insulating layer with a metal material. The method of claim 4, wherein the charge accumulation layer is Floating gate using polysilicon, Nano floating gates having metal, semiconductor or oxide nanocrystals, or A method of manufacturing a nonvolatile memory device having a staggered tunnel barrier, characterized in that it comprises at least one of a charge trap layer comprising at least one of HfO ₂ , ZrO ₂ and Si ₃ N ₄ . 5. The method of claim 4, The first tunneling insulating film is formed of a silicon nitride film, The second tunneling insulating layer is formed of at least one of a material consisting of a hafnium oxide (HfO ₂ ), ZrO ₂ , HfSiOx, ZrSiOx, La ₂ O ₃ Non-volatile memory device having a staggered tunnel barrier Manufacturing method. The method of claim 4, further comprising heat treating the nonvolatile memory device at a temperature of 300 to 500 ° C. in an atmosphere containing hydrogen. The method of claim 4, wherein the charge accumulation layer is formed by an atomic layer deposition (ALD) method when forming the charge accumulation layer.

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