KR101152121B1 - Display device and thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The present invention improves the performance of a display device. A display panel for a transflective liquid crystal display device, wherein a transparent electrode and a reflective electrode are sequentially formed on a substrate, and the reflective electrode includes an amorphous silicon lower layer and a metal upper layer. As described above, an amorphous layer is formed between the transparent electrode formed in the reflective region and the reflective layer, and the substrate is heat-treated to increase the adhesion between the reflective layer and the amorphous layer, thereby reducing the contact resistance, thereby improving the performance of the transflective liquid crystal display.

Thin film transistor display panel, transflective, reflective electrode, amorphous silicon film

Description

Display device, thin film transistor display panel and manufacturing method therefor {DISPLAY DEVICE AND THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 and 5 are layout views of a liquid crystal display including a thin film transistor array panel and a common electrode panel according to an exemplary embodiment of the present invention.

4 and 6 are cross-sectional views taken along line IV-IV and VI-VI, respectively, of a liquid crystal display including the thin film transistor array panel and the common electrode display panel illustrated in FIGS. 3 and 5.

7 and 8 are layout views in an intermediate step of manufacturing the thin film transistor array panel illustrated in FIGS. 3 to 6 according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of the thin film transistor array panel of FIGS. 7 and 8 taken along lines IX-IX 'and IX'-IX' '.

10 and 11 are layout views of a thin film transistor array panel in the next step of FIGS. 7 and 8;

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIGS. 10 and 11 cut along the lines XII-XII 'and XII'-XII' '.

13 and 14 are layout views of a thin film transistor array panel in the next step of FIGS. 10 and 11;

FIG. 15 is a cross-sectional view of the thin film transistor array panel of FIGS. 13 and 14 cut along the lines XV-XV ', XV'-XV' ', and

16 and 17 are layout views of a thin film transistor array panel in the next steps of FIGS. 13 and 14.

FIG. 18 is a cross-sectional view of the thin film transistor array panel of FIGS. 16 and 17 cut along the lines XVIII-XVIII ', XVIII'-XVIII' ', and

FIG. 19 is a cross-sectional view of the thin film transistor array panel of FIG. 18 taken along the lines XVIII-XVIII 'and XVIII'-XVIII' '.

20 is a cross-sectional view of the thin film transistor array panel of FIG. 19 taken along the lines XVIII-XVIII 'and XVIII'-XVIII' '.

※ Explanation of symbols on main parts of drawing ※

110: insulating substrate 121: gate line

124a: gate electrode 131: sustain electrode line

137: sustain electrode 140: gate insulating film

153a: source region 154a: channel region

155a: drain region 171: data line

173a: source electrode 175a: drain electrode

191: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, a thin film transistor array panel, and a manufacturing method thereof, and more particularly, to a thin film transistor array panel of a transflective liquid crystal display device.

Liquid crystal display (LCD) is one of the most widely used flat panel display devices. It consists of two substrates with electrodes and a liquid crystal layer interposed therebetween to control the voltage applied to the electrodes. By rearranging the liquid crystal molecules of the liquid crystal layer to control the transmittance of light passing through the liquid crystal layer. In this case, the light transmittance is determined by phase retardation caused by the optical properties of the liquid crystal material when passing through the liquid crystal layer, and the phase retardation is controlled by adjusting the refractive index anisotropy of the liquid crystal material and the distance between the two substrates. Decide

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor (TFT) that has electrodes on each of two substrates and switches a voltage applied to the electrodes is one of the two liquid crystal display devices. It is generally formed in.

The liquid crystal display device transmits light emitted by a backlight lamp, which is an artificial light source, to the liquid crystal layer to display an image such as a transmissive type and natural light reflected by the reflective electrode of the liquid crystal display device to the liquid crystal layer. A semi-transmissive mode that can be divided into a reflective type to display and which operates in both a reflective mode and a transmissive mode has recently been developed.

On the other hand, the pixels of the transflective liquid crystal display are divided into a transmission area and a reflection area. The transmissive region is the region without the reflective electrode, and the reflective region is the region where the reflective electrode is present.

This reflective electrode is formed on the transparent electrode formed on the protective film. Conventional reflective electrodes are made of opaque and reflective aluminum, silver, chromium or alloys thereof. In addition, the reflective electrode may be formed in a structure further comprising a lower layer made of molybdenum or molybdenum alloy, chromium, titanium, or tantalum.

However, the contact resistance between the upper layer and the lower layer included in the reflective electrode is large, and the molybdenum-based material used as the lower layer is inferior in selectivity to the dry etching process for forming the reflective electrode. For this reason, the performance of the transflective liquid crystal display may be degraded.

In addition, when the reflective electrode of the aluminum-based material having a single layer structure is formed, the reflective electrode may be corroded by reacting with the transparent electrode formed under the reflective electrode.

Accordingly, an object of the present invention is to improve the performance of a display device.

A method for manufacturing a thin film transistor according to the present invention is a display panel for a transflective liquid crystal display device, the substrate comprising a substrate, a transparent electrode formed on the substrate, and a reflective electrode formed on the transparent electrode, wherein the reflective electrode is amorphous Silicon lower film and metal upper film.

The metal upper layer may include aluminum, silver, chromium, or an alloy thereof, and the metal upper layer may be a single layer.

The amorphous silicon underlayer may include conductive impurities.

The display device may further include a thin film transistor formed on the substrate, and a passivation layer formed on the data line.

The protective film may include an organic material, and irregularities may be formed on a surface of the protective film.

The reflective electrode may be curved along the unevenness.

A method of manufacturing a thin film transistor array panel of a transflective liquid crystal display device, the method comprising: forming a transparent electrode on a substrate, laminating an amorphous semiconductor layer on the transparent electrode, laminating a metal layer on the amorphous semiconductor layer, and forming the metal layer Etching to form the upper reflective electrode, and removing the portion of the amorphous semiconductor layer not covered by the upper reflective electrode to form the lower reflective electrode.

The upper reflective electrode may include aluminum, silver, chromium, or an alloy thereof.

The amorphous semiconductor layer may include amorphous silicon, and the amorphous silicon may include conductive impurities.

The metal layer may be a single layer.

The method may further include heat treating the substrate after the lamination of the metal layer.

The heat treatment can be 200 ℃ to 300 ℃.

The method may further include forming a thin film transistor under the transparent electrode, and forming a protective film between the thin film transistor and the transparent electrode.

The method may further include forming irregularities on the surface of the protective film to cause the reflective electrode to be bent, and the protective film may include an organic material.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

A display device, a thin film transistor array panel, and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel unit 300, a gate driver 400 and a data driver 500 connected thereto. ), A gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

Referring to FIG. 1, the display panel unit 300 is connected to a plurality of display panel lines G ₁ -G _n , D ₁ -D _m when viewed in an equivalent circuit and arranged in a substantially matrix form. And a plurality of pixels PX constituting a display area DA.

Referring to FIG. 2, the display panel 300 of the liquid crystal display includes lower and upper display panels 100 and 200 and a liquid crystal layer 3 therebetween. In the case of an organic light emitting diode display, the display panel 300 may include only one display panel.

The display signal lines G ₁ -G _n and D ₁ -D _m transmit a data signal and a plurality of gate lines G ₁ -G _n that transmit a gate signal (also called a “scan signal”). It includes a data line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes at least one switching element (not shown) such as a thin film transistor and at least one capacitor (not shown).

Referring to FIG. 2, each pixel of the liquid crystal display device (PX) is, for example, i-th gate line (G _i) and j th data lines (D _j) pixel display signal lines (G _i, D _j, defined as ) And a switching element Q connected thereto, and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. The display signal lines G _{i and} D _j are disposed on the lower display panel 100, and the storage capacitor C _ST may be omitted as necessary.

The switching element Q, such as a polysilicon thin film transistor, is provided in the lower panel 100 and connected to a control terminal and a data line D ₁ -D _m connected to the gate lines G ₁ -G _n , respectively. It is a three-terminal device that has an input terminal and an output terminal connected to a liquid crystal capacitor (C _LC ) and a storage capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 191 of the lower panel 100 and a common electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 191 and 270. It functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST is a capacitor that assists the liquid crystal capacitor C _LC . A separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 overlap each other, and the separate signal line A predetermined voltage such as the common voltage Vcom is applied to the. However, the storage capacitor C _ST may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

In order to implement color display, each pixel PX uniquely displays one of a plurality of primary colors (spatial division) or alternately displays a plurality of primary colors (time division), so that the spatial In time, the desired color is indicated. Examples of the primary colors include three primary colors including red, green, and blue. FIG. 2 shows an example of spatial division in which each pixel PX includes a color filter 230 representing one color of the primary colors in a corresponding region facing the pixel electrode 191 in the upper panel 200. have. Alternatively, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the display panel unit 300.

Each pixel PX of the organic light emitting diode display includes a switching transistor (not shown) connected to the display signal lines G ₁ -G _n , D ₁ -D _m , a driving transistor (not shown) connected thereto, Sustain capacitors (not shown), and light emitting diodes (not shown). The light emitting diode includes an anode electrode (not shown) and a cathode electrode (not shown) and an organic light emitting member (not shown) therebetween.

Referring back to FIG. 1, the gray signal generator 800 generates a plurality of gray signals related to the transmittance of the pixel PX. The gray level signal generator 800 for the liquid crystal display generates two gray level voltages each having a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to receive a gate signal having two values equal to the gate on voltage Von and the gate off voltage Voff, respectively. G ₁ -G _n ). The gate driver 400 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit constituting the gate driver 400 is connected to one gate line G ₁ -G _n and includes a plurality of N-type, P-type, and complementary polysilicon thin film transistors. The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 and selects a gray voltage from the gray signal generator 800 to select the gray voltage as the data voltage D ₁ -D _m. ) Is applied. Like the gate driver 400, the data driver 500 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit of the data driver 500 is connected to one data line D ₁ -D _m and includes a plurality of N-type, P-type, and complementary polysilicon thin film transistors.

However, the gate driver 400 or the data driver 500 may be mounted on the display panel 300 in the form of one or more integrated circuit (IC) chips or mounted on the flexible printed circuit film attached to the display panel 300. Can be.

The driving units 400 and 500 are positioned in the peripheral area positioned outside the display area DA in the display panel 300.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like, and may be mounted on a printed circuit board (PCB).

Next, the liquid crystal panel assembly illustrated in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 6.

3 and 5 are layout views of a liquid crystal display including a thin film transistor array panel and a common electrode panel according to an exemplary embodiment of the present invention, and FIGS. 4 and 6 are views of the thin film transistor array panel shown in FIGS. The liquid crystal display device including the common electrode panel is a cross-sectional view taken along lines IV-IV and VI-VI, respectively.

Here, it is assumed that the thin film transistor of the pixel PX is N type and the thin film transistor of the gate driver 400 is P type.

First, the thin film transistor array panel will be described in detail.

A blocking film 111 made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the transparent insulating substrate 110. The blocking film 111 may have a multilayer structure.

On the blocking film 111, a plurality of pixel portion island semiconductors 151a and driver unit island semiconductors 151b made of polycrystalline silicon are formed. Each of the semiconductors 151a and 151b includes an extrinsic region containing conductive impurities and an intrinsic region containing little conductive impurities, and a heavily doped region having a high impurity concentration in the impurity region. region and lightly doped region with low impurity concentration.

The intrinsic region of the pixel portion semiconductor 151a includes a channel region 154a, and the high concentration impurity region is sequentially separated from the source region 153a, which is sequentially separated around the channel region 154a. And a region 156a and a drain region 155a. The low concentration impurity region 152 is located between the intrinsic region 154a and the high concentration impurity regions 153a, 155a, and 156a and is narrow in width. In particular, the low concentration impurity region 152 located between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a is referred to as a lightly doped drain region (LDD region). do. This lightly doped drain region may be omitted.

The intrinsic region of the driver semiconductor 151b includes a channel region 154b, and the high concentration impurity region includes a source region 153b and a drain region 155b.

Examples of the conductive impurity include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As). The low concentration doped region 152 prevents leakage current or punch through from the thin film transistor and can be replaced with an offset region free of impurities.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the semiconductors 151a and 151b and the blocking layer 111.

A gate conductor including a plurality of gate lines 121 including a gate electrode 124a and a plurality of control electrodes 124b and a plurality of storage electrode lines on the gate insulating layer 140. An electrode line 131 is formed.

The gate line 121 transmits the gate signal and extends mainly in the horizontal direction. The gate electrode 124a extends upward from the gate line 121 to cross the pixel portion semiconductor 151b, and overlaps the channel region 154a. Each gate line 121 may include a wide end portion for connection with another layer or an external driving circuit. When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The control electrode 124b overlaps the channel region 154b of the driver semiconductor 151b and is connected to another signal line (not shown) to which a control signal is applied.

The storage electrode line 131 receives a predetermined voltage such as a common voltage applied to a common electrode (not shown), and is extended upward to extend the wider portion 137 and the vertical portion 133 extending upward. It includes.

The gate line 121, the sustain electrode line 131, and the control electrode 124b may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper (Cu), or copper alloy. It may be made of a copper-based metal, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W). However, the gate line 121, the storage electrode line 131, and the control electrode 124b may have a multilayer film structure including two conductive films (not shown) having different physical properties. One of these conductive films is a low resistivity metal such as aluminum-based metal or silver so as to reduce the signal delay or voltage drop of the gate line 121, the sustain electrode line 131, and the control electrode 124b. It may be made of a metal of a series, a metal of a copper series. The other conductive layer may be formed of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, titanium, or the like. A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 may be made of various other metals and conductors.

Side surfaces of the gate conductors 121 and 124b and the storage electrode line 131 may be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

An interlayer insulating film 160 is formed on the gate conductors 121 and 124b and the storage electrode line 131. The interlayer insulating layer 160 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The interlayer insulating layer 160 may be formed by having photosensitivity among the organic insulators, and the surface of the interlayer insulating layer 160 may be flat.

A plurality of contact holes 163, 165, 166, and 167 exposing the source and drain regions 153a, 153b, 155a, and 155b are formed in the interlayer insulating layer 160 and the gate insulating layer 140.

The data line 171 transmitting the data signal mainly includes a source electrode 173a extending in the vertical direction to intersect the gate line 121 and connected to the source region 153a through the contact hole 163. One end of the data line 171 may have a large area in order to connect with another layer or an external driving circuit, and when a data driving circuit (not shown) generating a data signal is integrated on the substrate 110 Line 171 may be directly connected to the data driving circuit.

The drain electrode 175a is separated from the source electrode 173a and is connected to the drain region 155a through the contact hole 165. The drain electrode 175a is connected to the extension portion 137 and the vertical portion 133 of the storage electrode line 131. Each includes an overlapping portion 177 and a vertical portion 176. The vertical portion 133 of the storage electrode line 131 is positioned between the vertical portion 176 of the drain electrode 175 and the boundary line facing the data line 171 to prevent signal interference therebetween.

The input electrode 173b and the output electrode 175b are separated from each other with respect to the control electrode 124b and may be connected to another signal line (not shown).

The data line 171, the drain electrode 175, and the storage capacitor conductor 177 for transmitting the data signal are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. . However, these may also have a multilayer structure including a lower layer such as a refractory metal and a low resistance upper layer disposed thereon. Examples of the multilayer structure may include a double layer of a chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer-aluminum (alloy) interlayer-molybdenum (alloy) upper layer.

Like the gate conductors 121 and 121b, the data conductors 171, 172, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to 80 ° with respect to the surface of the substrate 110.

A passivation layer 180 is formed on the data conductors 171, 173b, 175a, and 175b and the interlayer insulating layer 160.

The passivation layer 180 includes a lower layer 180q made of an inorganic insulator such as silicon nitride or silicon oxide and an upper layer 180q made of an organic insulator. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. An opening that exposes a portion of the lower passivation layer 180p is formed in the upper passivation layer 180q, and irregularities are formed on the surface of the upper passivation layer 180q. The passivation layer 180 may have a single layer structure made of an inorganic insulator or an organic insulator.

The passivation layer 180 is provided with a plurality of contact holes 185 exposing the extension 177 of the drain electrode 175a. A plurality of contact holes (not shown) may also be formed in the passivation layer 180 to expose an end portion of the data line 171, and an end portion of the gate line 121 may be formed in the passivation layer 180 and the interlayer insulating layer 160. A plurality of contact holes (not shown) may be formed to reveal the gaps.

A plurality of pixel electrodes 191 are formed on the passivation layer 180.

Each pixel electrode 191 includes a transparent electrode 192 and a reflective electrode 194 thereon. In this case, the reflective electrode 194 includes a lower layer 194p and an upper layer 194q.

The transparent electrode 192 is made of a transparent conductive material such as ITO or IZO, the lower layer 194p of the reflective electrode is made of amorphous silicon (a-Si), and the upper layer 194q of the reflective electrode is made of aluminum (alloy). Is made of a reflective metal of an aluminum-based metal such as) and a silver-based metal of silver (alloy). Amorphous silicon may comprise a conductive material.

The aluminum and silver particles of the upper layer 194q of the reflective electrode may be diffused in the lower layer 194p of the reflective electrode, and the aluminum and silver particles lower the resistance of the lower layer 194p and the lower layer 194p. And the contact resistance between the upper layer 194q can also be lowered.

In addition, the lower layer 194p may prevent a reaction between the upper layer 194q and the transparent electrode 192 and may make various inclinations.

The pixel electrode 191 is curved along the unevenness of the upper passivation layer 180q, and the reflective electrode 194 is positioned in an opening of the upper passivation layer 180q and exposes the transmission window 196 exposing the transparent electrode 192. Have.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175a through the contact hole 185 and receives a data voltage from the drain electrode 175a. The pixel electrode 191 to which the data voltage is applied generates an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage is applied, thereby creating a liquid crystal layer 3 between the two electrodes. Determines the direction of the liquid crystal molecules. The polarization of light passing through the liquid crystal layer 3 varies according to the direction of the liquid crystal molecules determined as described above. The pixel electrode 191 and the common electrode 270 form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The transflective liquid crystal display may be partitioned into a transmissive area TA and a reflective area RA defined by the transparent electrode 192 and the reflective electrode 194. Specifically, the portion of the thin film transistor array panel 100, the common electrode display panel 200, the liquid crystal layer 3, and the like positioned below and below the exposed portion of the transparent electrode 192 becomes the transmission area TA and the reflective electrode. The portion located below and above (194) becomes the reflection area RA. In the transmissive area TA, light is incident on the back side of the liquid crystal display, that is, the thin film transistor array panel 100, passes through the liquid crystal layer and exits the front side, that is, toward the common electrode display panel 200. In FIG. 2, light from the front surface enters the liquid crystal layer 3, is reflected by the reflective electrode 194, passes through the liquid crystal layer again, and exits to the front surface.

The pixel electrode 191 overlaps the storage electrode line 131 including the extension 137, and holds the capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected thereto and overlap the storage electrode line 131. This is called a storage capacitor, and the holding capacitor enhances the voltage holding capability of the liquid crystal capacitor.

On the other hand, a light blocking member 220 called a black matrix is formed on the common electrode display panel 200 facing the thin film transistor array panel 100 on a substrate 210 made of an insulating material such as transparent glass or plastic. The light blocking member 220 prevents light leakage between the pixel electrodes 191 and defines an opening area facing the pixel electrode 191.

The plurality of color filters 230 are formed on the substrate 210 and the light blocking member 220, and are disposed to substantially enter the opening region defined by the light blocking member 220. The color filters 230 disposed between two neighboring data lines 171 and arranged in the vertical direction may be connected to each other to form a band. Each color filter 230 may represent one of three primary colors such as red, green, and blue.

Each color filter 230 is thicker in the transmission area TA than in the reflection area RA so that the number of shades of light passing through the color filter 230 is different in the transmission area TA and the reflection area RA. The difference can be compensated. Alternatively, the color difference may be compensated by maintaining the same thickness of the color filter 230 and forming a hole in the color filter 230 of the reflection area RA.

A common electrode 270 made of a transparent conductive material such as ITO or IZO is formed on the light blocking member 220 and the color filter 230.

Next, a method of manufacturing the thin film transistor array panel of the transflective liquid crystal display device shown in FIGS. 1 and 6 will be described in detail with reference to FIGS. 7 to 25.

7 and 8 are layout views in an intermediate step of manufacturing the thin film transistor array panel illustrated in FIGS. 3 to 6 according to an embodiment of the present invention, and FIG. 9 is an IX-IX view of the thin film transistor array panel of FIGS. 7 and 8. 10 and 11 are layout views of the thin film transistor array panel in the next steps of FIGS. 7 and 8, and FIG. 12 is a thin film of FIGS. 10 and 11. FIG. 13 is a cross-sectional view of the transistor panel cut along the lines XII-XII 'and XII'-XII' ', and FIGS. 13 and 14 are layout views of the thin film transistor array panel in the next steps of FIGS. 10 and 11, and FIG. 13 and 14 are cross-sectional views cut along the XV-XV 'and XV'-XV' lines, and FIGS. 16 and 17 are layout views of the thin film transistor array panel in the next steps of FIGS. 13 and 14. 18 is a thin film transistor array panel of FIGS. 16 and 17. FIG. 19 is a cross-sectional view taken along lines XVIII-XVIII 'and XVIII'-XVIII' ', and FIG. 19 is a cross-sectional view taken along line XVIII-XVIII' and XVIII'-XVIII '' in the next step of FIG. 20 is a cross-sectional view of the thin film transistor array panel in the next step of FIG. 19 cut along the lines XVIII-XVIII 'and XVIII'-XVIII' '.

First, as shown in FIGS. 7 to 9, the blocking layer 111 is formed on the transparent insulating substrate 110, and then, as amorphous silicon by chemical vapor deposition (CVD), sputtering, or the like. The formed semiconductor film is formed. The semiconductor film is then crystallized by laser annealing, furnace annealing or sequential lateral solidification (SLS).

Then, the semiconductor film is patterned to form a plurality of pixel portion and driver island type semiconductors 151a and 151b.

Next, as shown in FIGS. 10 to 12, the gate insulating layer 140 is formed on the semiconductors 151a and 151b by a chemical vapor deposition method or the like, and a plurality of gate lines including the gate electrode 124a is formed thereon. 121, the plurality of sustain electrode lines 131 including the expansion unit 137, and the control electrode 124b are formed. Impurity ions are implanted into the semiconductor layers 151a and 151b to form N-type high concentration impurity regions 153a, 153b, 155a, 155b, and 156a, channel regions 154a, and low concentration impurity regions 152.

Then, as shown in FIGS. 13 to 15, a plurality of layers that expose the source and drain regions 153a, 155a, 153b, and 153b by stacking and photo-etching the interlayer insulating layer 160 on the entire surface of the substrate 110, respectively. Contact holes 163, 165, 166, 167 are formed.

Next, data conductors 173a, 173b, 175a, and 175b connected to the source and drain regions 153a, 155a, 153b, and 153b are formed on the interlayer insulating layer 160.

Next, as shown in FIGS. 16 to 18, the lower passivation layer 180p made of inorganic material is laminated by chemical vapor deposition, and the upper passivation layer 180q made of photosensitive organic material is applied. Subsequently, light is irradiated onto the upper passivation layer 180q through a photo mask (not shown) to develop the convex and convexities on the surface of the upper passivation layer 180q, and partially expose the lower passivation layer 180p. An exposed portion of the passivation layer 180p and a portion of the gate insulating layer 140 under the protective layer 180p are removed to form a plurality of contact holes 185 or the like that expose the extension 177 of the drain electrode 175a of the pixel portion.

Thereafter, a transparent electrode 192 connected to the extension 177 through the contact hole 185 is formed of a transparent conductive material such as indium zinc oxide (IZO) or indium tin oxide (ITO).

Subsequently, an amorphous layer 195 and a reflective layer 196 are sequentially stacked on the substrate 110. Here, the amorphous layer 195 is made of amorphous silicon (a-Si) having a sheet resistance value of 10 ⁹ GPa or more, and the reflective layer 196 is made of aluminum-based metals such as aluminum-nidium (AlNd) and silver (Ag) series. It can be made of metal. In this case, the amorphous silicon may include n-type impurities such as phosphorus.

Next, a high temperature heat treatment process of 200 ° C to 300 ° C is performed. This process causes the reflective layer 196 to diffuse into the amorphous layer 195, thereby increasing the adhesion between the reflective layer 196 and the amorphous layer 195 and lowering the contact resistance.

[Table 1] shows the values measured several times by changing the resistance of the unit area between the amorphous silicon (a -Si) having a different thickness or the conductive layer 195 and the reflecting layer 196 having conductivity. It is shown.

As shown in Table 1, the heat treatment process lowers the resistance value of the amorphous layer 195 to a level of 10 ⁴ kPa, and substantially uniformly distributes the surface resistance value of the contact between the reflective layer 196 and the amorphous layer 195. Make it. Accordingly, the performance of the display device can be improved.

Next, as shown in FIG. 20, the reflective layer 196 is etched to form an upper layer 194q of the reflective electrode, and dry etching is performed using the mask as a mask to form the lower layer 194p of the reflective electrode. . In this case, the tapered structure of the lower layer 194q may be variously made.

The transflective liquid crystal display according to the present invention forms an amorphous layer made of amorphous silicon between the transparent electrode formed in the reflective region and the reflective layer, and heats the substrate to increase the adhesion between the reflective layer and the amorphous layer, thereby improving contact resistance. Can be reduced. Thereby, the performance of a transflective liquid crystal display device can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (16)

As a display panel for a transflective liquid crystal display device, Board, A transparent electrode formed on the substrate, and A reflective electrode formed on the transparent electrode Including; The reflective electrode includes an amorphous silicon lower layer and a metal upper layer Display panel. In claim 1, The metal upper layer includes aluminum, silver, chromium, or an alloy thereof. In claim 1, The metal upper layer is a single layer. In claim 1, The amorphous silicon lower layer includes conductive impurities. In claim 1, A thin film transistor formed on the substrate, and A protective film formed on the thin film transistor Display panel further including. The method of claim 5, The passivation layer includes an organic material, and a display panel having irregularities formed on a surface of the passivation layer. In claim 6, The reflective electrode is curved along the irregularities. As a method of manufacturing a thin film transistor array panel of a transflective liquid crystal display device, Forming a transparent electrode on the substrate, Stacking an amorphous semiconductor layer on the transparent electrode, Depositing a metal layer on the amorphous semiconductor layer, Etching the metal layer to form an upper reflective electrode, and Removing a portion of the amorphous semiconductor layer not covered by the upper reflective electrode to form a lower reflective electrode Method of manufacturing a thin film transistor array panel comprising a. In claim 8, The upper reflective electrode may include aluminum, silver, chromium, or an alloy thereof. In claim 8, And the amorphous semiconductor layer comprises amorphous silicon. In claim 10, And the amorphous silicon comprises a conductive impurity. In claim 8, The metal layer is a single layer thin film transistor array panel manufacturing method. In claim 8, And heat treating the substrate after the metal layer stacking step. In claim 13 The heat treatment is a method of manufacturing a thin film transistor array panel of 200 ℃ to 300 ℃. In claim 8, Forming a thin film transistor under the transparent electrode, and Forming a passivation layer between the thin film transistor and the transparent electrode Method of manufacturing a thin film transistor array panel further comprising. 16. The method of claim 15, Forming irregularities on the surface of the protective film to cause the reflective electrode to bend; The protective film includes an organic material Method of manufacturing a thin film transistor array panel.

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