KR101168331B1 - Method for verifying optical proximity correction - Google Patents

Abstract

An optical proximity correction verification method is presented. According to the present invention, the target layout of the target patterns is set, the layout of the corrected patterns obtained by performing optical proximity effect correction (OPC) on the target patterns is obtained, and the entire area of the corrected layout includes the corrected patterns, respectively. After dividing the verification areas into the verification areas, the verification areas are divided into pixels having different sizes from each other but constant pixels within the areas. Simulation verification is performed on the corrected patterns for each of the pixels.

OPC, Model Base, Rule Base, Pixel, Simulation

Description

Method for verifying optical proximity correction

1 is a layout diagram schematically illustrating a conventional optical proximity correction (OPC) verification method.

FIG. 2 is a layout diagram schematically illustrating an optical proximity correction verifying method according to an exemplary embodiment of the present invention.

3 is a flowchart schematically illustrating an optical proximity correction verification method according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for verifying optical proximity correction (OPC) when fabricating a photo mask.

 As the degree of integration of semiconductor devices increases, the size of patterns required for the devices is rapidly reduced. Accordingly, a resolution of 100 nm or less is required for a lithography process for forming a pattern. As the size of the pattern shape decreases, distortion in the process of transferring the pattern becomes severe. Accordingly, as a method for more effectively coping with the complexity of the design rule by overcoming the limitation of the lithography process, Resolution Enhancement Technologies (RET) that increase the resolution by correcting the optical proximity effect (OPC) Is being presented.

OPC may be understood to correct the layout of a target pattern to be transferred onto the wafer in consideration of the optical proximity effect (OPE). Such OPC can be roughly divided into a rule-based approach and a model-based approach.

The rule base approach is understood as an approach to replace segments that make up a pattern, for example, depending on the size of the pattern shape and its associated environments. Can be. The model-based approach prepares a model of the pattern transfer process, uses this model to simulate an image to be actually printed on the wafer, and desired wafer for such simulated image. It can be understood in a manner of comparative matching with an image.

In addition, a technique for verifying whether or not OPC is properly performed on the results obtained after performing OPC is also recognized as an important technique along with the OPC technique. In general, a process of verifying an OPC layout is based on a method of verifying by a specified rule such as a design rule check (DRC). However, it is difficult to explain abnormal phenomena occurring on the wafer in such a rule base verification process, and a method of verifying using a model-based approach is gradually being used.

1 is a layout diagram schematically illustrating a conventional optical proximity correction (OPC) verification method.

Referring to FIG. 1, the OPC layout data includes a plurality of patterns 10 having different sizes or shapes, for example, a line pattern 11 having a relatively small line width, and a pattern 13 having a relatively large line width. And larger sized isolated patterns 15 and the like.

This model-based approach to OPC data first divides the entire chip size area to be verified into regions of constant size or pixels (pixels) of 20, and then the pixels (or pixels) for these pixels (20). 20) All the corresponding points representing the pattern in the simulation are simulated. This simulation compares the simulated layout against the desired target pattern's layout, ie the original layout, according to the model-based approach (or pixel-based approach) or the grid-based approach. It can be understood as a process.

In this case, the pixels 20 are all set to the same size 21 regardless of the existence of the actual pattern 10. Therefore, since the simulation is performed for all the pixels 20, the amount of data to be simulated is greatly increased, and accordingly, the time required for the simulation is increased.

An object of the present invention is to provide a method for verifying optical proximity effect correction results in a shorter time.

One aspect of the present invention for achieving the above technical problem, setting a target layout of the target patterns, obtaining a layout of the corrected patterns that performed optical proximity effect correction (OPC) for the target patterns, Dividing the entire area of the corrected layout into verification areas each including the corrected patterns, and dividing the verification areas into pixels having different sizes from each other but having a constant size within the areas. And a step of performing a simulation verification on the corrected patterns for each of the pixels.

The verification areas may be set to be divided by setting an area between the corrected patterns as a boundary area having a predetermined width.

The boundary region may be set to a width larger than the optical proximity effect range according to the size of the corrected pattern or the exposure illumination system condition in the adjacent verification region.

The method may further include setting a virtual verification line passing through the boundary area, and simulating and verifying the presence or absence of an unwanted pattern on the verification line.

The size of the pixel in the verification area may be set to about 1/2 to 1/10 times the size of the corrected pattern located in the verification area.

According to the present invention, it is possible to provide a method for verifying the optical proximity effect correction result in a model base approach within a shorter time.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it should not be construed that the scope of the present invention is limited by the embodiments described below. Embodiments of the invention are preferably to be interpreted as being provided to those skilled in the art to more fully describe the invention.

In the embodiment of the present invention, when verifying the OPC results, the pixel-based simulation is improved for all points based on a constant pixel size uniformly across all regions, thereby selecting only the regions where patterns exist. Verification simulation is performed by setting the pixels to the appropriate size for the region.

In this case, the size of the pixel is set depending on the pattern size between the selected areas to improve the verification accuracy and to more effectively reduce the verification time. In order to verify whether there is an abnormal phenomenon in a region where no pattern exists, for example, whether or not a bad pattern exists, a virtual verification line is set past a center portion, and a signal generated along the verification line is set. Analyze and detect abnormalities. Such a verification line may be understood as a boundary line of substantially divided regions.

After dividing the data into a plurality of areas in relation to the size of the pattern, and setting pixels for simulation of different sizes in each verification area, simulation is performed for all areas regardless of the conventional pattern. Verification simulation can be performed more efficiently than in the case.

FIG. 2 is a layout diagram schematically illustrating an optical proximity correction verifying method according to an exemplary embodiment of the present invention. 3 is a flowchart schematically illustrating an optical proximity correction verification method according to an exemplary embodiment of the present invention.

2 and 3, an OPC verification method according to an embodiment of the present invention includes a pixel-base (or grid) that performs simulation on points representing a layout of a pattern based on a set pixel size. Base) simulation. At this time, the OPC verification compares the initial pattern designed and drawn by the designer, that is, the original design pattern and the simulation contour, and verifies whether the OPC correction is appropriately and effectively performed.

In more detail, the corrected patterns for designing and setting the target layout of the target patterns to be transferred and implemented on the wafer (301 of FIG. 3) and performing optical proximity effect correction (OPC) on the target patterns ( A layout of 100 in FIG. 2 is obtained (303 in FIG. 3). OPC layout data (data) is a plurality of different size or shape pattern 100 as shown in Figure 2, for example, a relatively small line width line pattern 101, a relatively large line width pattern 103 And larger sized isolated patterns 105 and the like.

Verification of such OPC data may first include, for example, a pixel-based (or model-based) or grid-based approach, each of which includes patterns 100 that are calibrated over the entire chip size area 200 to be verified. The verification areas are divided into 210, 230, and 250. These verification areas 210, 230, and 250 are divided into areas including different patterns 101, 103, and 105, respectively (305 of FIG. 3).

For example, the verification regions 210, 230, and 250 are set to be divided by setting a region where the pattern between the corrected patterns 101, 103, and 105 is not located as a boundary region 201 of a predetermined width. do. Such setting may be arbitrarily performed by a user.

This boundary region 201 may actually expose the size or patterns 101, 103, 105 of the OPC patterns 101, 103, 105 located in the adjacent verification regions 210, 230, 250, respectively. It is preferable to set the width larger than the optical proximity effect range (OPE range) according to the exposure illumination system conditions, for example, the numerical aperture NA or the exposure equipment. In this case, the boundary area 201 may be set according to the forbidden pitch size.

That is, as the boundary region 201 is set to a width larger than the OPE range considered in the OPC, the verification in the verification regions 210, 230, and 250 may be induced to be performed independently without mutual influence. have. The division of the verification areas 210, 230, and 250 in this manner prevents the verification simulation from being substantially performed on the part where the pattern is not substantially located, such as the boundary area 201, and thus the required time required for verification ( This is because the run time can be effectively reduced.

Although it is set as an area where no patterns are formed in the boundary area 201, an unwanted pattern may be generated due to an unwanted abnormal phenomenon in the boundary area 201. In order to detect the occurrence of such an abnormal phenomenon more simply and effectively, the virtual verification line 205 passing through the preferably center portion of the boundary area 201 between the verification areas 210, 230, and 250 is set (307). .

By simulating the existence of an unwanted pattern on the verification line 205 along the verification line 205, it is possible to simply verify whether an abnormal phenomenon occurs in the boundary area 201 (313 in FIG. 3). That is, by analyzing a signal generated on the verification line 205 along the verification line 205, it is possible to detect the presence of abnormality.

Meanwhile, the divided verification regions 210, 230, and 250 are set to be divided into pixels 211, 231, and 251 having different sizes between regions, but having a constant size in the region (309 of FIG. 3). ). As such, by setting the pixels 211, 231, and 251 to different sizes for each of the verification areas 210, 230, and 250, the simulation time can be reduced more efficiently.

In this case, the sizes of the pixels 211, 231, and 251 in the verification areas 210, 230, and 250 may correspond to the sizes of the patterns 101, 103, and 105 located in the verification areas 210, 230, and 250, respectively. It is set differently depending on the size. For example, the size of each associated pixel 211, approximately 1/2 to 1/10 times, preferably 1/3 to 1/5 times, the size of the OPC patterns 101, 103, 105. 231 and 251 are set. That is, in the case of a pattern having a size of 100 nm, the simulation pixel size is suitably about 20 to 35 nm.

For each of the pixels 211, 231, and 251 set as described above, a comparison verification simulation with respect to the original layout of the OPC corrected patterns 101, 103, and 105 is performed (311 of FIG. 3). At this time, since the sizes of the pixels 211, 231, 251 are specified differently depending on the sizes of the patterns 101, 103, 105, the verification of the patterns 101, 103, 105 may be more accurate. In addition, simulation time can also be reduced.

Simulation verification for such a pixel may consist of simulation of all the corresponding points representing a pattern within the pixel for the pixels, which simulation may be a model-based approach (or a pixel-based approach) or a grid-based approach. Depending on the approach, it can be understood as the process of comparing the layout of the desired target pattern, that is, the simulated layout against the original layout.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, after selectively setting a constant boundary only for the region where the pattern is located, pixel-based simulation is preferably performed only for the verification region within this boundary. In addition, by applying different pixel sizes for each pattern size, it is possible to implement an improvement in accuracy of verification and / or time required.

In addition, a virtual center line is applied within the boundary area so that abnormal phenomena in the boundary area, that is, the boundary area, can be detected. Analyze the signal to detect abnormality. Accordingly, it is possible to implement an improvement in accuracy and / or time required for verification.

Claims (5)

Setting a target layout of target patterns; Obtaining a layout of corrected patterns for performing optical proximity effect correction (OPC) on the target patterns; Dividing the entire area of the corrected layout into verification areas each including the corrected patterns and a border area that is an area where no pattern will be located between the corrected patterns; Establishing a virtual verification line through the boundary area; First simulating the presence or absence of an unwanted pattern on the verification line along the verification line; Setting the verification areas to be divided into pixels having different sizes from one area to another area but having a predetermined size within the area; And And performing a second simulation verification on the corrected patterns for each of the pixels. delete Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, And the boundary region is set to have a width larger than an optical proximity effect range according to the size of the corrected pattern or an exposure illumination system condition in the adjacent verification region. delete Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And the size of the pixel in the verification area is set to 1/2 to 1/10 times the size of the corrected pattern located in the verification area.

Images