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KR101195463B1 - Semiconductor package and method for forming the same - Google Patents

Semiconductor package and method for forming the same Download PDF

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Publication number
KR101195463B1
KR101195463B1 KR1020110013238A KR20110013238A KR101195463B1 KR 101195463 B1 KR101195463 B1 KR 101195463B1 KR 1020110013238 A KR1020110013238 A KR 1020110013238A KR 20110013238 A KR20110013238 A KR 20110013238A KR 101195463 B1 KR101195463 B1 KR 101195463B1
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semiconductor chip
moisture absorption
prevention layer
forming
insulating member
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KR20120093585A (en
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남종현
정관호
이웅선
김시한
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

반도체 패키지 및 그 형성방법이 개시되어 있다. 개시된 반도체 패키지는, 제1면 및 상기 제1면에 대향하는 제2면을 가지며 상기 제1면에 본딩 패드 및 퓨즈가 형성된 반도체 칩과, 상기 본딩 패드 및 상기 퓨즈를 포함한 상기 반도체 칩의 제1면 상에 형성되며 상기 본딩 패드를 노출하는 흡습 방지층과, 상기 반도체 칩의 제2면에 부착되는 기판과, 상기 반도체 칩을 포함한 상기 기판상에 상기 흡습방지층이 노출되도록 형성되는 절연부재와, 상기 흡습 방지층 및 상기 절연부재 상에 형성되며 상기 노출된 본딩 패드와 전기적으로 연결되는 도전막 패턴 및 상기 도전막 패턴 상에 장착되는 외부접속단자를 포함하는 것을 특징으로 한다.A semiconductor package and a method of forming the same are disclosed. The disclosed semiconductor package includes a semiconductor chip having a first surface and a second surface facing the first surface and having a bonding pad and a fuse formed on the first surface, and a first chip of the semiconductor chip including the bonding pad and the fuse. A moisture absorption prevention layer formed on a surface and exposing the bonding pad, a substrate attached to a second surface of the semiconductor chip, an insulation member formed to expose the moisture absorption prevention layer on the substrate including the semiconductor chip, and And a conductive film pattern formed on the moisture absorption prevention layer and the insulating member and electrically connected to the exposed bonding pads, and external connection terminals mounted on the conductive film pattern.

Description

반도체 패키지 및 그 형성방법{SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME}Semiconductor Package and Formation Method {SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME}

본 발명은 반도체 패키지 및 그 형성방법에 관한 것이다.The present invention relates to a semiconductor package and a method of forming the same.

일반적으로 반도체 패키지는 전자기기의 소형화, 경량화, 고기능화의 추세에 따라 경박단소화가 요구된다. 이에 따라, 전기적인 전달을 위한 배선의 길이가 짧고 저항과 인덕턴스가 작으며 신호의 전달 및 노이즈에 유리한 특성을 갖는 반도체 패키지가 요구되는 실정이다. 상기한 신호의 전달 및 노이즈 특성을 개선하기 위하여 기존의 와이어(wire)를 이용한 와이어 본딩(wire bonding) 방식 대신 범프(bump)를 이용하는 플립칩 본딩(flip chip bonding) 방식을 사용하게 되었다. In general, semiconductor packages are required to be light and thin in accordance with the trend of miniaturization, light weight, and high functionality of electronic devices. Accordingly, there is a need for a semiconductor package having a short wire length for electrical transmission, a small resistance and inductance, and advantageous characteristics for signal transmission and noise. In order to improve the signal transmission and noise characteristics, a flip chip bonding method using a bump is used instead of a wire bonding method using a conventional wire.

플립칩 본딩 방식에서는 반도체 칩의 본딩 패드에 접속 전극으로서 활용할 수 있는 범프를 형성하고, 그 범프를 통해 반도체 칩과 기판 또는 반도체 칩과 반도체 칩이 전기적/기계적으로 연결되도록 한 구조로서, 전기적 신호 전달이 단지 범프에 의해서만 이루어지므로 신호 전달 길이가 단축되어 고속화에 유리한 장점을 갖는다.In the flip chip bonding method, a bump is formed on a bonding pad of a semiconductor chip to be used as a connection electrode, and the bump is electrically connected to the semiconductor chip and the substrate or the semiconductor chip and the semiconductor chip. Since only this bump is used, the signal transmission length is shortened, which is advantageous in speeding up.

도 1은 일반적인 플립칩 본딩 방식의 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view illustrating a semiconductor package of a general flip chip bonding method.

도 1을 참조하면, 기판(1) 상에 반도체 칩(2)이 범프(3)를 매개로 플립칩 본딩되고, 조인트 신뢰성을 향상시키기 위하여 기판(1)과 반도체 칩(2) 사이에는 언더필 부재(4)가 충진되고, 반도체 칩(2)을 포함한 기판(1)의 상부면은 EMC(5)에 의해 몰딩된다. 그리고, 기판(1)의 하부면에는 솔더볼(6)이 장착된다. 미설명된 도면부호 2A 및 2B는 각각 반도체 칩(2)에 형성된 본딩 패드 및 퓨즈를 나타낸다. Referring to FIG. 1, a semiconductor chip 2 is flip chip bonded onto a bump 3 on a substrate 1, and an underfill member is disposed between the substrate 1 and the semiconductor chip 2 to improve joint reliability. (4) is filled, and the upper surface of the substrate 1 including the semiconductor chip 2 is molded by the EMC 5. The solder ball 6 is mounted on the lower surface of the substrate 1. Unexplained reference numerals 2A and 2B denote bonding pads and fuses formed in the semiconductor chip 2, respectively.

그러나, 이 같은 플립칩 본딩 방식은 다음과 같은 문제점들이 있었다.However, this flip chip bonding method has the following problems.

1. 반도체 칩이 기판을 통해 외부 장치와 연결되므로 4 레이어(layer) 이상의 고가의 기판(1)을 사용해야 하고, 범프(3), EMC(5) 및 언더필 부재(4)를 형성함으로 인하여 제작 비용이 많이 소모된다.1. Since the semiconductor chip is connected to an external device through a substrate, an expensive substrate 1 of 4 layers or more must be used, and a manufacturing cost due to the formation of bumps 3, EMC 5 and underfill member 4 This is consumed a lot.

2. EMC(5)와 언더필 부재(4)의 계면 또는 언더필 부재(5)의 내부에 보이드가 발생되고 열에 의해 보이드 내부의 공기가 팽창됨으로 인해 크랙이 유발되어 제품의 신뢰성을 확보하기 어렵다.2. Voids are generated at the interface between the EMC 5 and the underfill member 4 or inside the underfill member 5, and cracks are caused by the expansion of air in the void by heat, making it difficult to secure the reliability of the product.

3. 기판(1)의 구리 배선에 존재하는 구리(Cu)가 반도체 칩(2)의 퓨즈(2B)로 이동(migration)되고, 이렇게 이동된 구리로 인해 반도체 칩(2)에 전기적 불량이 발생되어 신뢰성이 낮다.3. Copper (Cu) present in the copper wiring of the substrate (1) is migrated to the fuse (2B) of the semiconductor chip (2), the electrical defect is generated in the semiconductor chip (2) due to this moved copper Low reliability.

4. 범프(3) 및 EMC(5)로 인하여 패키지의 높이 및 부피가 증가된다.4. The bumps 3 and EMC 5 increase the height and volume of the package.

본 발명의 목적은, 저렴한 비용으로 제조 가능하며 경박단소한 구조 및 높은 신뢰성을 갖는 임베디드 패키지를 제공하는데 있다.An object of the present invention is to provide an embedded package which can be manufactured at low cost and has a light and simple structure and high reliability.

본 발명의 다른 목적은, 전술한 임베디드 패키지의 형성방법을 제공하는데 있다.Another object of the present invention is to provide a method of forming the above-described embedded package.

본 발명의 일 견지에 따른 반도체 패키지는, 제1면 및 상기 제1면에 대향하는 제2면을 가지며 상기 제1면에 본딩 패드가 형성된 반도체 칩과, 상기 본딩 패드 및 상기 반도체 칩의 제1면 상에 형성되며 상기 본딩 패드를 노출하는 흡습 방지층과, 상기 반도체 칩의 제2면에 부착되는 기판과, 상기 반도체 칩을 포함한 상기 기판상에 상기 흡습방지층이 노출되도록 형성되는 절연부재와, 상기 흡습 방지층 및 상기 절연부재 상에 형성되며 상기 노출된 본딩 패드와 전기적으로 연결되는 도전막 패턴 및 상기 도전막 패턴 상에 장착되는 외부접속단자를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, a semiconductor package includes a semiconductor chip having a first surface and a second surface opposite to the first surface, and a bonding pad is formed on the first surface, and the bonding pad and the first of the semiconductor chip. A moisture absorption prevention layer formed on a surface and exposing the bonding pad, a substrate attached to a second surface of the semiconductor chip, an insulating member formed to expose the moisture absorption prevention layer on the substrate including the semiconductor chip, and And a conductive film pattern formed on the moisture absorption prevention layer and the insulating member and electrically connected to the exposed bonding pads, and external connection terminals mounted on the conductive film pattern.

상기 흡습 방지층은 실리콘을 포함하는 것을 특징으로 한다.The moisture absorption prevention layer is characterized in that it comprises silicon.

상기 기판은 실리콘 웨이퍼, 실리콘 판넬, 유리 판넬 또는 플라스틱 판넬 중에서 선택된 어느 하나를 포함하는 것을 특징으로 한다.The substrate is characterized in that it comprises any one selected from a silicon wafer, a silicon panel, a glass panel or a plastic panel.

상기 절연부재, 상기 흡습 방지층 및 상기 도전막 패턴 상에 형성되며 상기 외부접속단자가 장착되는 상기 도전막 패턴을 노출하는 개구를 갖는 솔더레지스트 패턴 및 상기 반도체 칩의 제2면과 상기 기판을 부착하는 접착부재를 더 포함하는 것을 특징으로 한다.A solder resist pattern formed on the insulating member, the moisture absorption prevention layer, and the conductive film pattern and having an opening exposing the conductive film pattern on which the external connection terminal is mounted, and attaching the second surface of the semiconductor chip to the substrate; Characterized in that it further comprises an adhesive member.

상기 반도체 칩은 상기 제1면에 형성되는 퓨즈를 더 포함하는 것을 특징으로 한다.The semiconductor chip may further include a fuse formed on the first surface.

본 발명의 다른 견지에 따른 반도체 패키지 형성방법은, 웨이퍼에 본딩 패드를 갖는 반도체 칩을 형성하는 단계와, 상기 본딩 패드가 위치하는 웨이퍼의 일면에 상기 본딩 패드를 노출하는 흡습 방지층을 형성하는 단계와, 상기 웨이퍼를 절단하여 상기 반도체 칩을 개별화시키는 단계와, 기판상에 상기 본딩 패드가 위치하는 반도체 칩의 제1면과 대향하는 제2면을 부착하는 단계와, 상기 반도체 칩을 포함한 상기 기판상에 상기 흡습 방지층이 노출되도록 절연부재를 형성하는 단계와, 상기 흡습 방지층 및 상기 절연부재 상에 상기 노출된 본딩 패드와 전기적으로 연결되는 도전막 패턴을 형성하는 단계 및 상기 도전막 패턴 상에 외부접속단자를 장착하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, a method of forming a semiconductor package includes forming a semiconductor chip having a bonding pad on a wafer, and forming a moisture absorption prevention layer exposing the bonding pad on one surface of the wafer where the bonding pad is located; And cutting the wafer to individualize the semiconductor chip, attaching a second surface facing a first surface of the semiconductor chip on which the bonding pad is located, to the substrate including the semiconductor chip. Forming an insulating member to expose the moisture absorption layer on the substrate; forming a conductive film pattern electrically connected to the exposed bonding pads on the moisture absorption layer and the insulating member; and external connection on the conductive film pattern. And mounting the terminal.

상기 흡습 방지층은 실리콘을 포함하는 것을 특징으로 한다. The moisture absorption prevention layer is characterized in that it comprises silicon.

상기 흡습 방지층은 캐스팅(drop casting), 스핀코팅(spin coating), 딥코팅(dip coating), 분무코팅(spray coating), 흐름코팅(flow coating), 스크린 인쇄(screen printing) 중 어느 하나를 사용하여 형성하는 것을 특징으로 한다.The moisture absorption layer may be formed using any one of drop casting, spin coating, dip coating, spray coating, flow coating, and screen printing. It is characterized by forming.

상기 기판은 실리콘 웨이퍼, 실리콘 판넬, 유리 판넬 또는 플라스틱 판넬 중에서 선택된 어느 하나를 포함하는 것을 특징으로 한다. The substrate is characterized in that it comprises any one selected from a silicon wafer, a silicon panel, a glass panel or a plastic panel.

상기 절연부재를 형성하는 단계는 예비 절연부재를 상기 반도체 칩을 포함한 상기 기판상에 배치하는 단계와, 상기 예비 절연부재를 상기 반도체 칩을 포함한 상기 기판상에 라미네이트하는 단계 및 상기 흡습 방지층이 노출되도록 상기 예비 절연부재를 제거하는 단계를 포함하는 것을 특징으로 한다. The forming of the insulating member may include disposing a preliminary insulating member on the substrate including the semiconductor chip, laminating the preliminary insulating member on the substrate including the semiconductor chip, and expose the moisture absorption prevention layer. And removing the preliminary insulating member.

상기 예비 절연부재를 제거하는 단계는, 에치백(etchback) 공정 또는 디스미어(desmear) 공정을 이용하여 수행하는 것을 특징으로 한다. Removing the preliminary insulating member may be performed by using an etchback process or a desmear process.

상기 흡습 방지층을 형성하는 단계 후, 상기 반도체 칩을 개별화시키는 단계 전에, 상기 웨이퍼의 일면과 대향하는 타면을 식각하는 단계를 더 포함하는 것을 특징으로 한다.After the forming of the moisture absorption prevention layer, before the step of individualizing the semiconductor chip, etching the other surface opposite to one surface of the wafer, characterized in that it further comprises.

상기 도전막 패턴을 형성한 후, 상기 외부접속단자를 장착하기 전에, 상기 절연부재, 흡습방지층 및 도전막 패턴 상에 상기 외부접속단자가 장착될 상기 도전막 패턴 부위를 노출하는 솔더레지스트 패턴을 형성하는 단계를 더 포함하는 것을 특징으로 한다.After forming the conductive film pattern, and before mounting the external connection terminal, a solder resist pattern is formed on the insulating member, the moisture absorption prevention layer and the conductive film pattern to expose the conductive film pattern portion on which the external connection terminal is to be mounted. Characterized in that it further comprises the step.

본 발명에 따르면, 반도체 패키지의 제조 비용이 감소되고 반도체 패키지의 신뢰성 향상 및 경박단소화를 이룰 수 있다.According to the present invention, the manufacturing cost of the semiconductor package can be reduced, and the reliability and light weight of the semiconductor package can be improved.

도 1은 일반적인 플립칩 본딩 방식의 반도체 패키지를 도시한 단면도이다.
도 2는 본 발명의 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 3 내지 도 13은 본 발명의 실시예에 따른 반도체 패키지 형성방법을 설명하기 위한 도면들이다.1 is a cross-sectional view illustrating a semiconductor package of a general flip chip bonding method.
2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
3 to 13 are diagrams for describing a method of forming a semiconductor package according to an embodiment of the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시예에 따른 반도체 패키지는 반도체 칩(10), 흡습 방지층(20), 기판(30), 절연부재(40), 도전막 패턴(50) 및 외부접속단자(60)를 포함한다. 그 외에, 솔더레지스트 패턴(70) 및 접착부재(80)를 더 포함한다. 2, a semiconductor package according to an embodiment of the present invention includes a semiconductor chip 10, a moisture absorption prevention layer 20, a substrate 30, an insulating member 40, a conductive film pattern 50, and an external connection terminal ( 60). In addition, the solder resist pattern 70 and the adhesive member 80 are further included.

반도체 칩(10)은 제1면(10A) 및 제1면(10A)과 대향하는 제2면(10B)을 갖는다. The semiconductor chip 10 has a first surface 10A and a second surface 10B opposite to the first surface 10A.

반도체 칩(10)은, 예를 들어, 데이터를 저장하기 위한 데이터 저장부(미도시) 및 데이터를 처리하기 위한 데이터 처리부(미도시)를 갖는 회로부(미도시)를 포함하며, 제1면(10A)은 활성면으로, 제1면(10A)에는 회로부와 전기적으로 연결된 본딩 패드(11)가 형성된다. 본 실시예에서, 본딩 패드(11)는 반도체 칩(10)의 양측 가장자리를 따라서 배치된다.이와 다르게, 본딩 패드(11)는 반도체 칩(10)의 중심부를 따라서 배치될 수도 있다. 반도체 칩(10)의 제1면(10)에는 본딩 패드(11) 외에 퓨즈(12)가 더 형성된다.The semiconductor chip 10 includes, for example, a circuit unit (not shown) having a data storage unit (not shown) for storing data and a data processing unit (not shown) for processing data, and includes a first surface ( 10A is an active surface, and a bonding pad 11 electrically connected to the circuit portion is formed on the first surface 10A. In the present embodiment, the bonding pads 11 are disposed along both edges of the semiconductor chip 10. Alternatively, the bonding pads 11 may be disposed along the center of the semiconductor chip 10. A fuse 12 is further formed on the first surface 10 of the semiconductor chip 10 in addition to the bonding pad 11.

흡습 방지층(20)은 본딩 패드(11), 퓨즈(12) 및 반도체 칩(10)의 제1면(10A) 상에 형성되며, 본딩 패드(11)를 노출하는 적어도 하나 이상의 홀(21)을 갖는다.The moisture absorption prevention layer 20 is formed on the bonding pad 11, the fuse 12, and the first surface 10A of the semiconductor chip 10, and at least one hole 21 exposing the bonding pad 11. Have

흡습 방지층(20)은 반도체 칩(10)의 활성면과 외부접속단자(60)가 부착되는 표면부의 거리가 짧음으로 인하여 발생되는 흡습 및 이로 인한 본딩 패드(11) 및 퓨즈(12)의 산화를 방지하기 위하여 형성하는 것으로, 흡습 방지층(20)의 재료로는 실리콘(silicon)이 사용될 수 있다.The moisture absorption prevention layer 20 absorbs moisture due to the short distance between the active surface of the semiconductor chip 10 and the surface portion to which the external connection terminal 60 is attached, and thereby oxidizes the bonding pad 11 and the fuse 12. Formed to prevent, silicon (silicon) may be used as the material of the moisture absorption prevention layer 20.

반도체 칩(10)의 제2면(10B)은 접착부재(80)를 매개로 기판(30) 상에 부착된다. 즉, 반도체 칩(10)은 기판(30) 상에 페이스 업(face up) 형태로 부착된다. The second surface 10B of the semiconductor chip 10 is attached onto the substrate 30 via the adhesive member 80. That is, the semiconductor chip 10 is attached to the substrate 30 in the form of face up.

접착부재(80)은 접착 페이스트 또는 양면 접착 테이프를 포함할 수 있고, 기판(30)은, 예를 들어 실리콘 웨이퍼, 실리콘 판넬, 유리 판넬 또는 플라스틱 판넬 중에서 선택된 어느 하나를 포함할 수 있다. The adhesive member 80 may include an adhesive paste or a double-sided adhesive tape, and the substrate 30 may include, for example, any one selected from a silicon wafer, a silicon panel, a glass panel, or a plastic panel.

절연부재(40)는 반도체 칩(10)을 포함한 기판(30) 상에 흡습 방지층(20)이 노출되도록 형성된다. 절연부재(40)는 열경화성 수지 또는 열가소성 수지를 포함할 수 있다.The insulating member 40 is formed to expose the moisture absorption prevention layer 20 on the substrate 30 including the semiconductor chip 10. The insulating member 40 may include a thermosetting resin or a thermoplastic resin.

도전막 패턴(50)은 흡습 방지층(20) 및 절연부재(40) 상에 형성되며, 홀(21)을 통해 본딩 패드(11)와 전기적으로 연결된다. 도전막 패턴(50)은 구리, 니켈, 금 중 적어도 어느 하나를 포함할 수 있다. The conductive film pattern 50 is formed on the moisture absorption prevention layer 20 and the insulating member 40, and is electrically connected to the bonding pad 11 through the hole 21. The conductive film pattern 50 may include at least one of copper, nickel, and gold.

솔더레지스트 패턴(70)은 절연부재(40), 흡습 방지층(20) 및 도전막 패턴(50) 상에 형성되며 도전막 패턴(50)을 일부 노출하는 개구를 갖는다. 외부접속단자(60)는 솔더레지스트 패턴(70)에 의해 노출된 도전막 패턴(50) 상에 장착된다. 외부접속단자(60)는 솔더볼 또는 범프를 포함한다.The solder resist pattern 70 is formed on the insulating member 40, the moisture absorption prevention layer 20, and the conductive film pattern 50 and has an opening that partially exposes the conductive film pattern 50. The external connection terminal 60 is mounted on the conductive film pattern 50 exposed by the solder resist pattern 70. The external connection terminal 60 includes solder balls or bumps.

전술한 구조를 갖는 반도체 패키지의 형성방법은 다음과 같다.A method of forming a semiconductor package having the above structure is as follows.

도 3 내지 도 13은 본 발명의 실시예에 의한 반도체 패지키 형성방법을 설명하기 위한 도면들이다. 3 to 13 are diagrams for describing a method of forming a semiconductor package according to an embodiment of the present invention.

도 3을 참조하면, 먼저 웨이퍼(W)에 반도체 소자 제조 공정을 통하여 본딩 패드(11) 및 퓨즈(12)를 갖는 반도체 칩(10)을 형성한다. Referring to FIG. 3, first, a semiconductor chip 10 having a bonding pad 11 and a fuse 12 is formed on a wafer W through a semiconductor device manufacturing process.

이하, 본딩 패드(11) 및 퓨즈(12)가 위치하는 웨이퍼(W)의 일측면을 일면(A)으로 정의하기로 하고, 일면(A)과 대향하는 웨이퍼(W)의 타측면을 타면(B)으로 정의하기로 하고, 일면(A) 및 타면(B)을 연결하는 연결면을 측면(C)으로 정의하기로 한다. Hereinafter, one side of the wafer W on which the bonding pad 11 and the fuse 12 are located will be defined as one surface A, and the other side of the wafer W facing the one surface A will be defined on the other surface ( It will be defined as B), the connection surface connecting the one surface (A) and the other surface (B) will be defined as the side (C).

도 4를 참조하면, 웨이퍼(W)의 일면(A) 상에 흡습 방지층(20)을 형성한다.Referring to FIG. 4, the moisture absorption prevention layer 20 is formed on one surface A of the wafer W. Referring to FIG.

흡습 방지층(20)의 재료로는 실리콘(silicon)이 사용될 수 있다. 흡습 방지층(20)을 형성하는 방법으로는 드롭 캐스팅(drop casting), 스핀코팅(spin coating), 딥코팅(dip coating), 분무코팅(spray coating), 흐름코팅(flow coating), 스크린 인쇄(screen printing) 중 어느 하나가 사용될 수 있다. 이때, 대기중에 노출시키는 것과 같은 단순 공기 건조법, 경화 공정의 초기 단계에서 진공을 적용하거나 약하게 가열하는 법(100℃이하)과 같은 증발에 적합한 수단을 사용하여 코팅된 실리콘이 경화될 수 있도록 한다. Silicon may be used as the material of the moisture absorption prevention layer 20. The method of forming the moisture absorption prevention layer 20 includes drop casting, spin coating, dip coating, spray coating, flow coating, and screen printing. printing) can be used. At this time, the coated silicon may be cured using a simple air drying method such as exposing to the atmosphere, a method suitable for evaporation such as applying a vacuum or weakly heating (less than 100 ° C.) at an early stage of the curing process.

본 실시예에서는, 흡습 방지층(20)의 웨이퍼(W)의 일면(A) 상에만 형성되는 경우를 도시 및 실명하였으나, 흡습 방지층(20)은 웨이퍼(W)의 일면(A)뿐만 아니라 웨이퍼(W)의 타면(B) 및 측면(C) 상에도 형성될 수 있다.In the present embodiment, the case in which the moisture absorption prevention layer 20 is formed only on one surface A of the wafer W is illustrated and shown. However, the moisture absorption prevention layer 20 is not only the surface A of the wafer W, but also the wafer ( It may also be formed on the other surface (B) and side surface (C) of W).

이어, 흡습 방지층(20)에 본딩 패드(11)를 노출하는 적어도 하나 이상의 홀(21)을 형성한다. 홀(21)을 형성하는 방법으로는 사진 식각 공정, 드릴링 공정, 레이저 드릴링 공정 등이 사용될 수 있다.Next, at least one hole 21 exposing the bonding pad 11 is formed in the moisture absorption prevention layer 20. As a method of forming the hole 21, a photolithography process, a drilling process, a laser drilling process, or the like may be used.

도 5를 참조하면, 제 1항에 있어서, 백그라인딩(backgrinding) 공정으로 웨이퍼(W)의 타면(B)을 식각하여 웨이퍼(W)를 소망하는 두께로 형성한다.Referring to FIG. 5, the other surface B of the wafer W is etched by a backgrinding process to form the wafer W to a desired thickness.

도 6을 참조하면, 웨이퍼(W)를 절단하여 반도체 칩(10)을 개별화시킨다.Referring to FIG. 6, the wafer W is cut to individualize the semiconductor chip 10.

이하, 본딩 패드(11) 및 퓨즈(12)가 위치하는 반도체 칩(10)의 일측면을 제1면(10A)으로 정의하기로 하고, 제1면(A)과 대향하는 반도체 칩(10)의 타측면을 제1면(B)으로 정의하기로 한다. Hereinafter, one side of the semiconductor chip 10 on which the bonding pad 11 and the fuse 12 are positioned will be defined as the first surface 10A, and the semiconductor chip 10 facing the first surface A will be described. The other side of will be defined as the first surface (B).

도 7을 참조하면, 기판(30) 상에 반도체 칩(10)을 페이스 업 형태로 부착한다. 즉, 본딩 패드(11)가 위치하는 반도체 칩(10)의 제1면(10A)과 대향하는 제2면(10B)을 접착부재(80)를 매개로 기판(30) 상에 부착한다. Referring to FIG. 7, the semiconductor chip 10 is attached to the substrate 30 in a face up form. That is, the second surface 10B facing the first surface 10A of the semiconductor chip 10 where the bonding pad 11 is located is attached onto the substrate 30 via the adhesive member 80.

접착부재(80)는 접착 페이스트 또는 양면 접착 테이프를 포함할 수 있고, 기판(30)으로는 실리콘 웨이퍼, 실리콘 판넬, 유리 판넬 또는 플라스틱 판넬 중 선택된 어느 하나를 포함할 수 있다.The adhesive member 80 may include an adhesive paste or a double-sided adhesive tape, and the substrate 30 may include any one selected from a silicon wafer, a silicon panel, a glass panel, or a plastic panel.

도 8을 참조하면, 예비 절연부재(40A)를 흡습 방지층(20)과 마주하도록 반도체 칩(10)을 포함한 기판(30) 상에 배치한다. 예비 절연부재(40A)로는 열경화성 수지 또는 열가소성 수지가 사용될 수 있다. Referring to FIG. 8, the preliminary insulating member 40A is disposed on the substrate 30 including the semiconductor chip 10 to face the moisture absorption prevention layer 20. As the preliminary insulating member 40A, a thermosetting resin or a thermoplastic resin may be used.

도 9를 참조하면, 열 또는/및 압력을 가하여 예비 절연부재(40A)를 반도체 칩(10)을 포함한 기판(30) 상에 라미네이트(laminate)한다. Referring to FIG. 9, the preliminary insulating member 40A is laminated on the substrate 30 including the semiconductor chip 10 by applying heat or / and pressure.

도 10을 참조하면, 흡습 방지층(20)이 노출되도록 예비 절연부재(40A)를 제거하여 절연부재(40)를 형성한다. 예비 절연부재(40A)의 제거는 에치백 공정, 디스미어(desmear) 공정 중 어느 하나를 이용하여 수행될 수 있다. Referring to FIG. 10, the insulating member 40 is formed by removing the preliminary insulating member 40A so that the moisture absorption prevention layer 20 is exposed. Removal of the preliminary insulating member 40A may be performed using any one of an etch back process and a desmear process.

도 11을 참조하면, 홀(21)을 포함한 흡습 방지층 및 절연부재(20,40) 상에 도전막(50A)을 형성한다. 도전막(50A)의 재료로 구리, 니켈, 금 중 적어도 어느 하나가 사용될 수 있으며, 도전막(50A)을 형성하는 방법으로는 라미네이션 공정 또는 전해도금 공정이 사용될 수 있다. Referring to FIG. 11, a conductive film 50A is formed on the moisture absorption prevention layer including the hole 21 and the insulating members 20 and 40. At least one of copper, nickel, and gold may be used as the material of the conductive film 50A, and a lamination process or an electroplating process may be used as a method of forming the conductive film 50A.

도 12를 참조하면, 사진 식각 공정으로 도전막(50A)을 패터닝하여 홀(21)을 통해 본딩 패드(11)와 전기적으로 연결되는 도전막 패턴(50)을 형성한다.Referring to FIG. 12, the conductive layer 50A is patterned by a photolithography process to form a conductive layer pattern 50 electrically connected to the bonding pads 11 through the holes 21.

도 13을 참조하면, 흡습 방지층, 절연부재 및 도전막 패턴(20,40,50) 상에 솔더레지스트(solder resist)를 형성하고, 사진 식각 공정으로 솔더 레지스트를 패터닝하여 도전막 패턴(50)을 일부 노출하는 솔더레지스트 패턴(70)을 형성한다.Referring to FIG. 13, a solder resist is formed on the moisture absorption prevention layer, the insulating member, and the conductive layer patterns 20, 40, and 50, and the solder resist is patterned by a photolithography process to form the conductive layer pattern 50. A partially exposed solder resist pattern 70 is formed.

도 2를 다시 참조하면, 도전막 패턴(50)의 노출 부위에 외부접속단자(60)를 장착한다. 외부접속단자(60)로는 솔더볼이 사용될 수 있다.Referring back to FIG. 2, the external connection terminal 60 is mounted on the exposed portion of the conductive film pattern 50. Solder balls may be used as the external connection terminals 60.

이상에서 상세하게 설명한 바에 의하면, 반도체 칩이 기판을 통하지 않고 외부 장치에 직접 연결되므로 고가의 기판을 사용하지 않아도 되고, 범프, EMC 및 언더필 부재의 구성이 생략되므로 제작 비용이 절감된다. 그리고, 범프, EMC 및 언더필 부재를 형성하지 않으므로 패키지의 높이 및 부피가 감소되고, 보이드성 크랙 발생이 원천적으로 차단되어 신뢰성이 향상된다. 또한, 반도체 칩이 기판상에 페이스 업 형태로 부착되므로, 기판에서 발생되는 이온으로 인한 반도체 칩의 전기적 불량이 방지된다. 요컨데, 제조 비용이 감소되고 신뢰성 향상 및 경박단소화를 달성할 수 있다.As described in detail above, since the semiconductor chip is directly connected to an external device without passing through the substrate, no expensive substrate is used, and the configuration of bumps, EMC, and underfill members is omitted, thereby reducing manufacturing costs. In addition, since the bump, EMC, and underfill members are not formed, the height and volume of the package are reduced, and void generation of cracks is essentially blocked, thereby improving reliability. In addition, since the semiconductor chip is attached to the substrate in a face-up form, electrical failure of the semiconductor chip due to ions generated in the substrate is prevented. In short, manufacturing cost can be reduced and reliability improvement and light weight can be achieved.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

10 : 반도체 칩
20 : 흡습 방지층
30 : 기판
40: 절연부재
50: 도전막 패턴10: Semiconductor chip
20: moisture absorption prevention layer
30: substrate
40: insulation member
50: conductive film pattern

Claims (13)

제1면 및 상기 제1면에 대향하는 제2면을 가지며 상기 제1면에 본딩 패드 및 퓨즈가 형성된 반도체 칩;
상기 본딩 패드 및 상기 퓨즈를 포함한 상기 반도체 칩의 제1면 상에 형성되며 상기 본딩 패드를 노출하는 흡습 방지층;
상기 반도체 칩의 제2면에 부착되는 기판;
상기 반도체 칩을 포함한 상기 기판상에 상기 흡습방지층이 노출되도록 형성되는 절연부재;
상기 흡습 방지층 및 상기 절연부재 상에 형성되며 상기 노출된 본딩 패드와 전기적으로 연결되는 도전막 패턴; 및
상기 도전막 패턴 상에 장착되는 외부접속단자를 포함하는 것을 특징으로 하는 반도체 패키지. A semiconductor chip having a first surface and a second surface opposite to the first surface, wherein a bonding pad and a fuse are formed on the first surface;
A moisture absorption prevention layer formed on the first surface of the semiconductor chip including the bonding pad and the fuse and exposing the bonding pad;
A substrate attached to a second surface of the semiconductor chip;
An insulation member formed to expose the moisture absorption layer on the substrate including the semiconductor chip;
A conductive film pattern formed on the moisture absorption prevention layer and the insulating member and electrically connected to the exposed bonding pads; And
And an external connection terminal mounted on the conductive film pattern. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1항에 있어서, 상기 흡습 방지층은 실리콘을 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the moisture absorption prevention layer comprises silicon. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 has been abandoned due to the setting registration fee. 제 1항에 있어서, 상기 기판은 실리콘 웨이퍼, 실리콘 판넬, 유리 판넬 또는 플라스틱 판넬 중에서 선택된 어느 하나를 포함하는 것을 특징으로 하는 반도체 패키지. The semiconductor package of claim 1, wherein the substrate comprises any one selected from a silicon wafer, a silicon panel, a glass panel, or a plastic panel. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 has been abandoned due to the setting registration fee. 제 1항에 있어서, 상기 절연부재, 상기 흡습 방지층 및 상기 도전막 패턴 상에 형성되며 상기 외부접속단자가 장착되는 상기 도전막 패턴을 노출하는 개구를 갖는 솔더레지스트 패턴; 및
상기 반도체 칩의 제2면과 상기 기판을 부착하는 접착부재를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor device of claim 1, further comprising: a solder resist pattern formed on the insulating member, the moisture absorption prevention layer, and the conductive film pattern and having an opening exposing the conductive film pattern on which the external connection terminal is mounted; And
And a bonding member attaching the second surface of the semiconductor chip to the substrate. 삭제delete 웨이퍼에 본딩 패드 및 퓨즈를 갖는 반도체 칩을 형성하는 단계;
상기 본딩 패드 및 퓨즈가 위치하는 웨이퍼의 일면에 상기 본딩 패드를 노출하는 흡습 방지층을 형성하는 단계;
상기 웨이퍼를 절단하여 상기 반도체 칩을 개별화시키는 단계;
상기 기판상에 상기 본딩 패드 및 퓨즈가 위치하는 반도체 칩의 제1면과 대향하는 제2면을 부착하는 단계;
상기 반도체 칩을 포함한 상기 기판상에 상기 흡습 방지층이 노출되도록 절연부재를 형성하는 단계;
상기 흡습 방지층 및 상기 절연부재 상에 상기 노출된 본딩 패드와 전기적으로 연결되는 도전막 패턴을 형성하는 단계; 및
상기 도전막 패턴 상에 외부접속단자를 장착하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지 형성방법.Forming a semiconductor chip having a bonding pad and a fuse on the wafer;
Forming a moisture absorption prevention layer exposing the bonding pad on one surface of the wafer where the bonding pad and the fuse are located;
Cutting the wafer to individualize the semiconductor chip;
Attaching a second surface facing the first surface of the semiconductor chip where the bonding pad and the fuse are positioned on the substrate;
Forming an insulating member on the substrate including the semiconductor chip to expose the moisture absorption layer;
Forming a conductive film pattern electrically connected to the exposed bonding pads on the moisture absorption prevention layer and the insulating member; And
And mounting an external connection terminal on the conductive film pattern. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제 6항에 있어서, 상기 흡습 방지층은 실리콘을 포함하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 6, wherein the moisture absorption prevention layer comprises silicon. 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 제 6항에 있어서, 상기 흡습 방지층은 드롭 캐스팅(drop casting), 스핀코팅(spin coating), 딥코팅(dip coating), 분무코팅(spray coating), 흐름코팅(flow coating), 스크린 인쇄(screen printing) 중 어느 하나를 사용하여 형성하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 6, wherein the moisture absorption layer is formed of drop casting, spin coating, dip coating, spray coating, flow coating, screen printing, and screen printing. Forming using any one of the). 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 has been abandoned due to the setting registration fee. 제 6항에 있어서, 상기 기판은 실리콘 웨이퍼, 실리콘 판넬, 유리 판넬 또는 플라스틱 판넬 중에서 선택된 어느 하나를 포함하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 6, wherein the substrate comprises any one selected from a silicon wafer, a silicon panel, a glass panel, or a plastic panel. 청구항 10은(는) 설정등록료 납부시 포기되었습니다.Claim 10 has been abandoned due to the setting registration fee. 제 6항에 있어서, 상기 절연부재를 형성하는 단계는 예비 절연부재를 상기 반도체 칩을 포함한 상기 기판상에 배치하는 단계;
상기 예비 절연부재를 상기 반도체 칩을 포함한 상기 기판상에 라미네이트하는 단계; 및
상기 흡습 방지층이 노출되도록 상기 예비 절연부재를 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 6, wherein the forming of the insulating member comprises: disposing a preliminary insulating member on the substrate including the semiconductor chip;
Laminating the preliminary insulating member on the substrate including the semiconductor chip; And
And removing the preliminary insulating member so that the moisture absorption prevention layer is exposed. 청구항 11은(는) 설정등록료 납부시 포기되었습니다.Claim 11 was abandoned upon payment of a setup registration fee. 제 10항에 있어서, 상기 예비 절연부재를 제거하는 단계는, 에치백(etchback) 공정 또는 디스미어(desmear) 공정을 이용하여 수행하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 10, wherein the removing of the preliminary insulating member is performed by using an etchback process or a desmear process. 청구항 12은(는) 설정등록료 납부시 포기되었습니다.Claim 12 is abandoned in setting registration fee. 제 6항에 있어서, 상기 흡습 방지층을 형성하는 단계 후, 상기 반도체 칩을 개별화시키는 단계 전에, 상기 웨이퍼의 일면과 대향하는 타면을 식각하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 6, further comprising etching the other surface opposite to one surface of the wafer after the forming of the moisture absorption prevention layer and before the individualizing of the semiconductor chip. 청구항 13은(는) 설정등록료 납부시 포기되었습니다.Claim 13 was abandoned upon payment of a registration fee. 제 6항에 있어서, 상기 도전막 패턴을 형성한 후, 상기 외부접속단자를 장착하기 전에, 상기 절연부재, 흡습방지층 및 도전막 패턴 상에 상기 외부접속단자가 장착될 상기 도전막 패턴 부위를 노출하는 솔더레지스트 패턴을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 형성방법.The method of claim 6, after forming the conductive film pattern and before mounting the external connection terminal, exposing the conductive film pattern portion on which the external connection terminal is to be mounted on the insulating member, the moisture absorption prevention layer and the conductive film pattern. Forming a solder resist pattern further comprises the step of forming a semiconductor package.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131759A (en) * 1997-07-14 1999-02-02 Sony Corp Mounted circuit substrate having moisture absorption protection film and method for forming moisture absorption protection film of the same substrate
JP2005167191A (en) * 2003-12-03 2005-06-23 Advanced Chip Engineering Technology Inc Fan-out wafer level package structure and manufacturing method thereof
US20090224392A1 (en) 2008-03-10 2009-09-10 Min Suk Suh Semiconductor package having side walls and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131759A (en) * 1997-07-14 1999-02-02 Sony Corp Mounted circuit substrate having moisture absorption protection film and method for forming moisture absorption protection film of the same substrate
JP2005167191A (en) * 2003-12-03 2005-06-23 Advanced Chip Engineering Technology Inc Fan-out wafer level package structure and manufacturing method thereof
US20090224392A1 (en) 2008-03-10 2009-09-10 Min Suk Suh Semiconductor package having side walls and method for manufacturing the same

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