KR101205872B1 - GaN based semiconductor device and method of manufacturing the same - Google Patents

Abstract

A normally off gallium nitride based semiconductor device and a method of manufacturing the same are disclosed.
The disclosed gallium nitride based semiconductor device includes a substrate, a polarity selective layer provided on the substrate, and a plurality of gallium nitride based semiconductor layers on the polarity selective layer, and the gate corresponding regions of the plurality of gallium nitride based semiconductor layers are N−. It has surface polarity.

Description

GaN based semiconductor device and method of manufacturing the same {GaN based semiconductor device and method of manufacturing the same}

An embodiment of the present invention relates to a normally off gallium nitride based semiconductor device and a method of manufacturing the same.

Recently, due to the rapid development of information and communication technology, the technology for the transmission of ultra-high speed and large capacity is rapidly developing. In this regard, as the demand for personal mobile phones, satellite communications, military radars, broadcast communications, communication repeaters, and the like expands in the wireless communication field, there is a demand for high-speed and high-power electronic devices required for ultrahigh-speed information communication systems in the microwave and millimeter wave bands. Is increasing. In other fields besides the communication field, a power device capable of controlling high power has been used for various purposes, and various studies have been conducted.

GaN-based nitride semiconductors have a large energy band gap, high thermal and chemical stability, and excellent physical properties such as high electron saturation rate (˜3 × 10 ⁷ cm / sec). This is possible. Electronic devices using GaN-based nitride semiconductors have various advantages such as high breakdown electric field (~ 3 × 10 ⁶ V / cm), high maximum current density, stable high temperature operating characteristics, and high thermal conductivity. In particular, in the case of a heterostructure field effect transistor (HFET) using a GaN-based heterojunction structure, since the band discontinuity is large at the junction interface, electrons can be concentrated at a high concentration at the junction interface, resulting in electron mobility. increase mobility. Such physical properties make it possible to apply to high power devices.

However, in the AlGaN / GaN HFET structure having such high electron mobility, there is a problem in that power is consumed because current flows even when no signal is applied. In the case of power devices, a large current density is required, so power loss in a normally on device can be a big problem. Recently, a normally off device that implements a MOS HFET has been developed through a recess structure in which an AlGaN layer of a gate portion is removed. However, since the AlGaN layer is very thin, about 30 nm or less, accurate control is difficult. In addition, when using ICP-RIE, the surface may be exposed to plasma, resulting in electrical degradation and the process may be complicated.

An embodiment of the present invention provides a normally off gallium nitride based semiconductor device.

Embodiments of the present invention provide a simple method for manufacturing a normally off gallium nitride based semiconductor device.

A gallium nitride based semiconductor device according to an embodiment of the present invention, the substrate; A polarity selection layer provided on the substrate; A plurality of gallium nitride based semiconductor layers provided on the polarity selection layer; And a source, a gate, and a drain provided on the plurality of gallium nitride based semiconductor layers, and a gate corresponding region of the gallium nitride based semiconductor layer may have an N-plane polarity.

The substrate may include any one of Si, SiC, AlN, GaN, and sapphire substrate.

The plurality of gallium nitride based semiconductor layers may include a GaN layer and an Al x Ga 1-x N (0 ≦ x <1) layer.

The GaN layer may be Al doped.

The Al x Ga 1-x N (0 ≦ x <1) layer may have a thickness in the range of 20-50 nm.

The Al x Ga 1-x N layer may have a composition range of 0.15 ≦ x ≦ 0.6.

The polarity selection layer may include an N-plane polarity region provided in the gate corresponding region, and a Ga-plane polarity region provided in the source corresponding region and the drain corresponding region.

The N-plane polar region may be formed using at least one selected from the group consisting of TMGa, TMAl, TMIn, CP ₂ Mg.

The source corresponding region and the drain corresponding region of the gallium nitride based semiconductor layer may have a Ga-plane polarity.

The source, gate and drain are Ni, Al, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi2, WSi, PtSi, Ir, Zr, Ta, TaN, It may be made of at least one material selected from the group consisting of Cu, Ru, and Co.

A buffer layer may be further provided between the polarity selection layer and the plurality of gallium nitride based semiconductor layers.

The plurality of gallium nitride based semiconductor layers may further include a pseudo insulating layer formed of a high resistance gallium nitride based material.

The substrate can be removed.

A method of manufacturing a gallium nitride based semiconductor device according to an embodiment of the present invention includes the steps of: depositing a silicon oxide layer on a substrate; Etching the silicon oxide layer using a mask to form an N-plane polar pattern region; Growing Ga in the N-plane polar pattern region to form an N-plane polar region; Removing the silicon oxide layer to form a Ga-plane polar pattern region; Growing N in the Ga-plane polarity pattern region to form a Ga-plane polarity region; Stacking a plurality of gallium nitride based semiconductor layers on the N-plane polarity region and the Ga-plane polarity region; And forming a source, a gate, and a drain on the plurality of gallium nitride based semiconductor layers.

In the semiconductor device according to the embodiment of the present invention, the gate is positioned by adjusting the arrangement of the Ga-face polarity region and the N-face polarity region before growing the gallium nitride-based semiconductor layer. Normally off can be realized by preventing the formation of a channel on the gallium nitride surface of the metal nitride. In addition, the recess process is omitted by implementing a normally off process by selectively placing a Ga-face polarity region and an N-face polarity region before growing the gallium nitride based semiconductor layer. This can simplify the process and increase device reproducibility.

1 is a schematic cross-sectional view of a gallium nitride based semiconductor device according to an embodiment of the present invention.
2 shows the crystal structures of a GaN layer having an N-plane polarity and a GaN layer having a Ga-plane polarity.
Figure 3 shows the formation position of the two-dimensional electron gas (2DEG) layer according to the surface polarity of the gallium nitride-based heterojunction structure.
4A to 4E illustrate a manufacturing process of a gallium nitride based semiconductor device according to an embodiment of the present invention.
5 illustrates a mask used in a manufacturing process of a gallium nitride based semiconductor device according to an embodiment of the present invention.

A gallium nitride based semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings refer to like elements, and the size or thickness of each element may be exaggerated for convenience of description. On the other hand, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

1 shows a gallium nitride based semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a substrate 10, a polarity selection layer 20 provided on the substrate 10, a plurality of gallium nitride based semiconductor layers 28 provided on the polarity selection layer 20, and And a source S, a gate G, and a drain D provided on the plurality of gallium nitride based semiconductor layers 28.

The substrate 10 may be formed of any one of Si, SiC, AlN, GaN, and sapphire (Al ₂ O ₃ ) substrates. The polarity selection layer 20 may include an N-plane polarity region 20a and a Ga-plane polarity region 20b. The N-plane polarity region 20a may be a region corresponding to the region where the gate G is located. The Ga-plane polarity region 20b may be a region corresponding to the region where the source S and the drain D are located. Here, the region corresponding to the region where the gate G is located may indicate an area facing the region where the gate G is located. The Ga-plane polarity and the N-plane polarity will be described later.

The plurality of gallium nitride based semiconductor layers 28 may include heterojunction layers. For example, the plurality of gallium nitride based semiconductor layers 28 may include a GaN layer 35 and an Al x Ga 1-x N layer 40. The Al x Ga 1-x N layer may have a composition range of 0 <x <1. Alternatively, the composition may have a composition range of 0.15 ≦ x ≦ 0.6. In addition, the Al x Ga 1-x N layer 40 may have a thickness in the range of 20-50 nm. The GaN layer 35 may be Al doped, for example. When Al-doped GaN layer 35, not only the carrier (electron) concentration can be increased but also the crystallinity can be improved, so that the characteristics of the device can be improved. For example, the thickness of the GaN layer 35 may be about 10 nm to about 500 nm.

A two-dimensional electron gas layer (2DEG) may be formed at an interface between the GaN layer 35 and the Al x Ga 1-x layer 40. In the III-V nitride layer, a 2DEG layer may be formed by spontaneous polarization (P _SP ) and piezo polarization (P _PE ) due to tensile stress. The 2DEG layer may be moved into a current path (channel) between the source S and the drain D. Therefore, the GaN layer 35 may be used as a channel layer. However, in the case where the 2DEG layer is formed over the entire GaN / AlGaN interface, a normal on characteristic may occur in which a current flows between the source S and the drain D even when no voltage is applied to the gate G. . However, in the exemplary embodiment of the present invention, the polarity of the gallium nitride semiconductor layer may be controlled by using the position at which the 2DED layer is formed according to the polarity of the III-V nitride layer, thereby allowing to have a normally off characteristic.

Hereinafter, N-face polarity and Ga-face polarity will be described with reference to FIG. 2.

2 (A) and (B) show the crystal structure of the GaN layer of N-face polarity and the GaN layer of Ga-face polarity, respectively.

Referring to FIG. 2, the Wurtzite structure GaN layer has an N-plane polarity in which N atoms are arranged in the uppermost layer (exposure surface) as in (A), or Ga atoms as in (B). It may have a Ga-plane polarity arranged on the uppermost layer (exposed surface). N-plane polarity can be achieved by growing Ga before N, and Ga-plane polarity can be achieved by growing N before Ga. The N-plane GaN layer of (A) may have [000-1] directionality in the Z-axis direction, and the Ga-plane GaN layer of (B) may have directionality in the Z-axis direction.

On the other hand, in the GaN-based heterojunction structure, for example, GaN / AlGaN structure, the formation position of the 2DEG layer may vary depending on the plane polarity of GaN and AlGaN. Referring to FIG. 3A, when GaN / AlGaN / GaN has an N-plane polarity, spontaneous polarization (P _SP ) and piezo polarization (P _PE ) are formed upward so that the 2DEG layer is formed on GaN above AlGaN. Can be formed. Referring to FIG. 3B, when GaN / AlGaN / GaN has Ga-plane polarity, spontaneous polarization (P _SP ) and piezo polarization (P _PE ) are formed downward so that the 2DEG layer is formed on GaN under AlGaN. Can be formed. As such, the position of the 2DEG layer may vary depending on the plane polarity of the heterojunction GaN-based semiconductor layer.

The surface polarity of the gallium nitride based semiconductor layer 28 may be selectively adjusted in the polarity selection layer 20. The polarity selection layer 20 includes a region 20a that includes an N-plane polarity and a region 20b that includes a Ga-plane polarity, and an N− over the region 20a that includes the N-plane polarity. A gallium nitride based semiconductor layer having a plane polarity may be grown, and a gallium nitride based semiconductor layer having a Ga-plane polarity may be grown over the region 20b including the Ga-plane polarity. Since the region 20a including the N-plane polarity is positioned to correspond to the region where the gate G is located, the GaN / AlGaN junction layer under the gate G may have the N-plane polarity. Therefore, in the GaN / AlGaN junction layer under the gate G, the 2DEG layer may be formed above the AlGaN layer 40 instead of below it. Since the region 20b including the Ga-plane polarity is located corresponding to the region where the source S and the drain D are located, the GaN / AlGaN junction layer under the source S and the drain has a Ga-plane polarity. Can be. Therefore, in the GaN / AlGaN junction layer under the source S and the drain D, a 2DEG layer may be formed below the AlGaN layer 40. As such, by adjusting the position at which the 2DEG layer is formed, the 2DEG layer is not formed in the GaN / AlGaN junction layer under the gate G, thereby preventing the current from flowing without the voltage applied to the gate G. .

The GaN layer 35 may be an aluminum (Al) doped GaN layer. In this case, the GaN layer 35 may be passivated by a gallium attacker (Ga vacancy) that may exist as a defect in the GaN layer by the doped aluminum (Al). It is possible to suppress the growth to two-dimensional and three-dimensional dislocations to improve the crystallinity of the GaN layer. As a high quality 2DEG layer is formed in the aluminum (Al) doped GaN layer with improved crystallinity, the scattering caused by Ga vacancy and other defects during the movement of electrons in the 2DEG layer is low. mobility can be increased.

Meanwhile, a lower layer of GaN layer 35 may include GaN, and may further include a semi-insulating layer 30 having higher resistance than a general semiconductor. The pseudo insulation layer 30 may be an undoped GaN layer or a GaN layer doped with impurities such as Mg, Zn, C, Fe, and the like, and its sheet resistance may be, for example, about 10 ⁹ Ω / sq or more. When the pseudo insulation layer 30 is formed of an undoped GaN layer, it is possible to prevent a problem due to out-diffusion of impurities during device operation. A method of increasing its resistance without doping Mg, Zn, C, Fe, etc. in the pseudo insulation layer 30 will be described later. When the pseudo insulation layer 30 has high resistance (that is, quasi insulation), since leakage of current through the pseudo insulation layer 30 can be suppressed / prevented, it may be advantageous to improve the characteristics of the device.

A buffer layer 25 may be further provided between the gallium nitride based semiconductor layer 28 and the polarity selection layer 20. The buffer layer 25 may include a GaN layer. The buffer layer 25 may be provided to reduce displacement due to mismatch of lattice constant between the substrate 10 and the gallium nitride based semiconductor layer 28, and to suppress crack generation caused by mismatch of thermal expansion coefficient. have.

Meanwhile, the source S, the gate G, and the drain D may include Ni, Al, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi 2, WSi. It may be made of at least one material selected from the group consisting of, PtSi, Ir, Zr, Ta, TaN, Cu, Ru, Co.

Next, a method of manufacturing a gallium nitride based semiconductor device according to an embodiment of the present invention will be described.

Referring to FIG. 4A, for example, a silicon oxide (SiOx) layer 52 is deposited on the substrate 50, and a photoresist 53 is deposited on the silicon oxide layer 52. The photoresist 53 may be patterned by the mask 110 in an N-plane polarity region corresponding pattern. Referring to FIG. 5, the mask 110 may include an N-plane polarity pattern region 112 and a mask region 114. In addition, the mask 110 may further include an alignment key 116 to align when using the gate mask. The photoresist 53 is exposed and patterned using the mask 110, and the silicon oxide layer 52 is etched using the photoresist 53 pattern as shown in FIG. 4B to form an N-plane polarity region. Pattern 54 may be formed. The substrate of the N-plane polarity region pattern 54 is exposed, and Ga is grown on the N-plane polarization region pattern 54 before N, thereby forming the N-plane polarization region 56. N-plane polarity region 56 may be formed using at least one selected from the group consisting of TMGa, TMAl, TMIn, CP ₂ Mg. For example, a Ga atomic layer can be grown from a TMGa source in the N-plane polar region pattern 54 where the substrate is exposed. This allows the region to be gated to have an N-plane polarity. Then, the silicon oxide layer 52 is removed leaving the N-plane polar region 56 as shown in FIG. 4D. When the silicon oxide layer 52 is removed, the substrate of the Ga-plane polar region pattern 62 is exposed.

Referring to FIG. 4E, the Ga-plane polarity region pattern 62 is formed so that N is grown before Ga, thereby forming the Ga-plane polarity region 64. At this time, the N 58 is grown in the N-plane polarity region 56, but the N-plane polarity may be maintained.

As described above, a polar selective layer including an N-plane polarity region and a Ga-plane polarity region is formed through a simple etching process and a growth process, and the polarity of the gallium nitride-based semiconductor layer depends on the polarity of each region of the polarity selection layer. Can be selected. The N-plane polarity region 56 is an area facing the region where the gate G is located (see FIG. 1), and the Ga-plane polarity region 64 is an area where the source S and the drain D are located. It may be patterned into an area facing the. Since the gallium nitride based semiconductor layer grown above the N-plane polarity region 56 has N-plane polarity, no 2DEG layer is formed at the interface of the GaN / AlGaN junction layer. In addition, since the gallium nitride-based semiconductor layer grown above the Ga-plane polarity region 64 has a Ga-plane polarity, a 2DEG layer may be formed at the interface of the GaN / AlGaN junction layer. Therefore, when no voltage is applied to the gate, no current flows under the gate G, thereby maintaining the normally off state.

Meanwhile, the substrate 50 may be removed during or after manufacturing the semiconductor device.

As described above, the gallium nitride-based semiconductor device according to the embodiment of the present invention can implement a normally off state without a voltage applied to a gate, so that the gallium nitride-based semiconductor device can be used in an electronic device having high speed and high power, and can control high power. It can be usefully applied to a power device.

The above embodiments are merely exemplary, and various modifications and equivalent other embodiments are possible to those skilled in the art. Therefore, the true technical protection scope according to the embodiment of the present invention will be defined by the technical spirit of the invention described in the claims below.

10 ... substrate, 20 ... polar selective layer
20a ... Ga-plane polarity zone, 20b ... N-plane polarity zone
25 buffer layer, 28 gallium nitride-based conductor layer
30 ... similar insulation layer, 35 ... GaN layer
40 ... Al _x Ga _{1 - x} N layer, S ... source
G ... gate, D ... drain
2DEG ... 2-dimensional electron gas layer, 110 ... mask

Claims (20)

Board;
A polarity selection layer provided on the substrate;
A plurality of gallium nitride based semiconductor layers provided on the polarity selection layer;
A source, a gate, and a drain provided on the plurality of gallium nitride based semiconductor layers,
A gallium nitride semiconductor device having a gate corresponding region of the gallium nitride semiconductor layer having an N-plane polarity. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
The substrate is a gallium nitride-based semiconductor device comprising any one of Si, SiC, AlN, GaN, sapphire substrate. The method of claim 1,
The gallium nitride-based semiconductor layer is a gallium nitride-based semiconductor device comprising a GaN layer and an Al x Ga 1-x N (0≤x <1) layer. The method of claim 3,
The GaN layer is an Al doped gallium nitride-based semiconductor device. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3,
The Al x Ga 1-x N (0 ≦ x <1) layer has a thickness in the range of 20-50 nm. Claim 6 has been abandoned due to the setting registration fee. The method of claim 3,
The Al x Ga 1-x N layer has a composition range of 0.15≤x≤0.6. 7. The method according to any one of claims 1 to 6,
And the polarity selection layer comprises an N-plane polarity region provided in the gate corresponding region, and a Ga-plane polarity region provided in the source corresponding region and the drain corresponding region. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
The N- polar face area gallium nitride-based semiconductor device formed using at least one selected from the group consisting of _{TMGa, TMAl, TMIn, CP 2} Mg. 7. The method according to any one of claims 1 to 6,
And a gallium nitride based semiconductor device having a Ga-plane polarity in a source corresponding region and a drain corresponding region of the gallium nitride based semiconductor layer. Claim 10 has been abandoned due to the setting registration fee. 7. The method according to any one of claims 1 to 6,
The source, gate and drain are Ni, Al, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi2, WSi, PtSi, Ir, Zr, Ta, TaN, A gallium nitride based semiconductor device comprising at least one material selected from the group consisting of Cu, Ru, and Co. 7. The method according to any one of claims 1 to 6,
The gallium nitride-based semiconductor device further comprises a buffer layer between the polarity selection layer and a plurality of gallium nitride-based semiconductor layer. 7. The method according to any one of claims 1 to 6,
The gallium nitride-based semiconductor layer further comprises a gallium nitride-based semiconductor device further comprises a pseudo insulating layer formed of a high resistance gallium nitride-based material. 7. The method according to any one of claims 1 to 6,
Gallium nitride-based semiconductor device is the substrate is removed. Depositing a silicon oxide layer on the substrate;
Etching the silicon oxide layer using a mask to form an N-plane polar pattern region;
Growing Ga in the N-plane polar pattern region to form an N-plane polar region;
Removing the silicon oxide layer to form a Ga-plane polar pattern region;
Growing N in the Ga-plane polarity pattern region to form a Ga-plane polarity region;
Stacking a plurality of gallium nitride based semiconductor layers on the N-plane polarity region and the Ga-plane polarity region; And
Forming a source, a gate, and a drain on the plurality of gallium nitride based semiconductor layers. Claim 15 is abandoned in the setting registration fee payment. 15. The method of claim 14,
The substrate is a gallium nitride-based semiconductor device manufacturing method comprising any one of Si, SiC, AlN, GaN, sapphire substrate. Claim 16 has been abandoned due to the setting registration fee. 15. The method of claim 14,
And a plurality of gallium nitride based semiconductor layers comprising a GaN layer and an Al x Ga 1-x N (0 ≦ x <1) layer. Claim 17 has been abandoned due to the setting registration fee. 17. The method of claim 16,
The GaN layer is Al doped gallium nitride-based semiconductor device manufacturing method. Claim 18 has been abandoned due to the setting registration fee. 17. The method of claim 16,
The Al x Ga 1-x N layer has a composition range of 0.15≤x≤0.6. The method according to any one of claims 14 to 18,
And the Ga-plane polarity region is located in the gate corresponding region, and the Ga-plane polarity region is located in the source and drain correspondence regions. Claim 20 has been abandoned due to the setting registration fee. 20. The method of claim 19,
And the N-plane polarity region is formed using at least one selected from the group consisting of TMGa, TMAl, TMIn, and CP ₂ Mg.

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