KR101298547B1 - Array substrate for in-plane swithing mode LCD and method for fabricating the same - Google Patents

Abstract

The present invention provides a display device comprising: a plurality of gate wires and data wires formed on a display area for displaying an image and crossing a surface of a substrate on which a non-display area is defined outside the display area and defining a plurality of pixel areas in the display area; A plurality of common wirings formed on the same layer as the gate wirings and extending in parallel to the non-display area; A plurality of gate link wirings connected to the ends of the gate wirings in the non-display area; A gate insulating film covering the plurality of gate link wirings and formed on an entire surface of the substrate; A first auxiliary common line intersecting the plurality of gate link lines in the non-display area over the gate insulating layer and formed of the same material as the data line; A protection formed on a front surface of the substrate, the first auxiliary hole covering the first auxiliary common line and exposing end portions of the plurality of common lines; and a plurality of second contact holes exposing the first auxiliary common line. A layer; Over the protective layer, the first auxiliary common wiring overlaps the first auxiliary common wiring, and contacts the first auxiliary common wiring through the plurality of second contact holes, and simultaneously contacts the plurality of common wirings through the plurality of first contact holes. And a second auxiliary common wiring formed, wherein the second auxiliary common wiring includes a plurality of branching portions extending to ends of each of the plurality of common wirings, and each of the plurality of branching portions forms the plurality of first contact holes. According to an embodiment of the present invention, there is provided an array substrate for a transverse electric field type liquid crystal display device further comprising a third auxiliary common wiring contacting each of the plurality of common wires and connecting both ends of each of the plurality of branches.

Description

Array substrate for transverse electric field type liquid crystal display device and manufacturing method thereof {Array substrate for in-plane swithing mode LCD and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a transverse electric field type liquid crystal display device having reduced contact defects in a gate pad portion of a non-display area, and a method of manufacturing the same.

Recently, as the information society has evolved rapidly, the necessity of a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption has emerged.

Such a flat panel display may be divided according to whether it emits light or not. A light emitting display is one that displays an image by emitting light by itself, and a display is performed by displaying an image using an external light source. It is called a display device. The light emitting display includes a plasma display panel, a field emission display, an electro luminescence display, and the light receiving display includes a liquid crystal display. display).

Dual liquid crystal display devices are being actively applied to notebooks and desktop monitors because of their excellent resolution, color display, and image quality.

The liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal between the two substrates, and then applies a voltage to the two electrodes to form a liquid crystal. It is a device that expresses an image by controlling light transmittance by moving molecules.

The liquid crystal panel for a liquid crystal display device includes a process of manufacturing an array substrate in which pixel electrodes and thin film transistors, which are switching elements, are formed for each pixel, and a common electrode and red, green, and blue colors correspond to each pixel as opposed to the array substrate. After injecting the liquid crystal between the process of manufacturing the color filter substrate is formed and the array substrate and the color filter substrate produced through the two processes, and then proceeds to a series of bonding process is completed.

FIG. 1 is a schematic plan view of an array substrate for a general transverse electric field type liquid crystal display device, FIG. 2 is a cross-sectional view of a portion of FIG. 1 taken along a cutting line II-II, and FIG. 3 is a cutting line of FIG. Sectional drawing about the part cut | disconnected along III-III.

As shown, in the array substrate 1 for a transverse electric field type liquid crystal display device, in the display area AA for displaying an image, a plurality of gate wirings 10 are formed extending in a first direction. A plurality of data wires 40 are formed in the second direction crossing the first direction. In this case, a plurality of pixel regions P are formed by crossing the gate and the data lines 10 and 40, penetrating through the pixel regions P, and spaced apart from each other in parallel with the gate line 10. The common wiring 18 is formed. In addition, a thin film transistor Tr, which is connected to the gate and data lines 10 and 40 and a switching element, is formed in each pixel region P, and is connected to a drain electrode 55 of the thin film transistor Tr. Bar electrodes of a bar shape are formed to be spaced apart from each other, and a plurality of common electrodes alternately with the plurality of bar shape pixel electrodes 80 and electrically connected to the common wiring 18. 20 is formed.

In the non-display area NA formed outside the display area AA, a plurality of gate pad electrodes 22 and data pad electrodes 45 connected to an external driving circuit (not shown) are formed. In addition, the gate pad electrode 22 and the gate line 10 are connected to each other, and a gate link line 13 is formed, and the data pad electrode 45 and the data line 40 are connected to each other. 42) is formed. In addition, a common wiring 18 formed in parallel with the gate wiring 10 extends from the display area AA and is formed in the non-display area NA, and the common wiring 18 has one end thereof. The auxiliary common wiring 50 formed in parallel with the data line 40 and the connection pattern 83 are electrically connected to each other.

At this time, referring to Figures 2 and 3, looking at the cross section of the portion where the common wiring 18 and the auxiliary common wiring 50 is connected, the common wiring 18 is formed on the substrate (1), The auxiliary common wiring 50 is formed on the gate insulating layer 22 covering the common wiring 18, and the protective layer 60 is formed to cover the auxiliary common wiring 50. In addition, corresponding to the side end of the auxiliary common wiring 50 facing each other and the end of the common wiring 18, these wirings are respectively provided for the protective layer 60 alone or the protective layer 60 and the gate insulating film 22, respectively. First and second contact holes 64 and 66 are provided to expose 18 and 50, and the common wiring 18 ends and auxiliary portions exposed through the first and second contact holes 64 and 66 are provided. It can be seen that the common wiring 18 and the auxiliary common wiring 50 are electrically connected to each other by simultaneously contacting the side ends of the common wiring 50 and forming the connection pattern 83. The auxiliary common wiring 50 is formed on a different layer from the common wiring 18. The auxiliary common wiring 50 is connected to a plurality of gate pad electrodes 22 of FIG. 1. It should be formed to cross the link wiring 13, wherein the gate link wiring 13 is formed on the same layer as the gate wiring 10 and the common wiring 18, the auxiliary common wiring to prevent short 50 is formed by forming the common wiring 18 on different layers.

However, the conventional array substrate 1 for a transverse electric field type liquid crystal display device having the above-described structure is in contact with the auxiliary common wiring 50 and the common wiring 18 through the first and second contact holes 64 and 66. In the process of forming the connection pattern 83, a lot of contact and open defects are generated due to a step and an error.

In addition, in recent years, the image display area AA is large, while the non-display area NA formed at its outer portion is gradually decreasing in area, and an attempt has been made to reduce the width of the auxiliary common wiring 50. have. Accordingly, the resistance values at one end and the other end of the auxiliary common wiring 50 are different from each other, so that the size of the common electrode supplied to the display area AA is changed by position, which causes staining to degrade the display quality. to be.

The present invention has been made to solve the above-described problems, and its object is to prevent the display from being lowered due to the increase in the resistance difference for each position due to the increase in the resistance even if the width of the auxiliary common wiring is reduced.

In addition, even if contact defects in the connection pattern occur due to process error between some common wiring and auxiliary common wiring, the common wiring and auxiliary common wiring are proposed by proposing a structure that can supply common voltage to the common wiring in which the contact failure occurred. Another object is to improve the production yield of the product without increasing the material and additional process by preventing contact failure and open failure in the jumping section of the liver.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention for achieving the above object, crosses the display area for displaying an image and one surface of the substrate in which a non-display area is defined outside the display area to the display area. A plurality of gate lines and data lines formed while defining a plurality of pixel regions; A plurality of common wirings formed on the same layer as the gate wirings and extending in parallel to the non-display area; A plurality of gate link wirings connected to the ends of the gate wirings in the non-display area; A gate insulating film covering the plurality of gate link wirings and formed on an entire surface of the substrate; A first auxiliary common line intersecting the plurality of gate link lines in the non-display area over the gate insulating layer and formed of the same material as the data line; A protection formed on a front surface of the substrate, the first auxiliary hole covering the first auxiliary common line and exposing end portions of the plurality of common lines; and a plurality of second contact holes exposing the first auxiliary common line. A layer; Over the protective layer, the first auxiliary common wiring overlaps the first auxiliary common wiring, and contacts the first auxiliary common wiring through the plurality of second contact holes, and simultaneously contacts the plurality of common wirings through the plurality of first contact holes. And a second auxiliary common wiring formed, wherein the second auxiliary common wiring includes a plurality of branching portions extending to ends of each of the plurality of common wirings, and each of the plurality of branching portions forms the plurality of first contact holes. The third auxiliary common wiring further contacts with each of the plurality of common wires and connects all of the ends of each of the plurality of branches.

A plurality of thin film transistors connected to the gate and data lines, the thin film transistors comprising a source electrode and a drain electrode spaced apart from the gate electrode, the gate insulating layer, and the semiconductor layer; A plurality of pixel electrodes electrically connected to the drain electrodes of the thin film transistors and spaced apart from each other in a bar shape; A plurality of common electrodes electrically connected to the common wiring and alternated with the plurality of pixel electrodes in a bar shape; And a data link wiring connected to the plurality of data wirings. In this case, the plurality of common electrodes may be formed on the same layer as the common wiring or on the same layer as the plurality of pixel electrodes.

In the method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention, a plurality of gate wirings are provided on one surface of a substrate on which a display area for displaying an image and a non-display area are defined outside the display area. And a plurality of common wires spaced apart from each of the plurality of gate wires and extending side by side to the non-display area, and simultaneously forming a plurality of gate link wires connected to the plurality of gate wires in the non-display area. Making a step; Forming a gate insulating film on the entire surface of the plurality of gate wirings, the common wirings, and the gate link wirings; A first auxiliary line intersecting each of the plurality of gate lines in the non-display area and defining a pixel area on the gate insulating layer, and simultaneously crossing the plurality of gate link wirings in the non-display area Forming a common wiring; A plurality of first contact holes exposing ends of a plurality of common wires located in the non-display area on the front surface of the plurality of data wires, the first auxiliary common wires, and a plurality of exposures of the first auxiliary common wires. Forming a protective layer having a second contact hole; Overlapping the first auxiliary common wiring over the protective layer and contacting the first auxiliary common wiring through the plurality of second contact holes, and simultaneously contacting the plurality of common wirings through the plurality of first contact holes. And forming a second auxiliary common wiring, wherein the second auxiliary common wiring has a plurality of branching portions extending to ends of each of the plurality of common wirings, and each of the plurality of branching portions is connected to the plurality of first contacts. Contacting each of the plurality of common wires through a hole, and forming a third auxiliary common wire connecting the ends of each of the plurality of branches.

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The forming of the gate wiring may include forming a gate electrode connected to the gate wiring in each of the pixel areas, and forming the data wiring and the first auxiliary common wiring in each of the pixel areas. Forming a source and a drain electrode spaced apart from each other above the semiconductor layer and the semiconductor layer corresponding to the gate electrode, and forming the second auxiliary common wiring contact the drain electrode in each of the pixel regions. The method may include forming a plurality of spaced apart pixel electrodes in a bar shape. The forming of the gate lines or the forming of the plurality of pixel electrodes may include connecting a plurality of common electrodes in a bar shape to be connected to the common wiring in each pixel area and alternate with the plurality of pixel electrodes. It is characterized by including the step of forming.

The array substrate for a transverse electric field type liquid crystal display device according to the present invention manufactured as described above has a second contact hole corresponding to any one of the common wirings in a jumper that makes an electrical connection between the first auxiliary common wiring and each common wiring. Even if contact failure occurs, since the second auxiliary common wiring is formed integrally and the third auxiliary common wiring is further provided, electrical connection is possible. Therefore, there is an effect of improving the product production yield by reducing the contact failure in the jumping part.

In addition, by overlapping the auxiliary common wiring so as to be connected in parallel, even when the narrow bezel is applied, even if the width of the auxiliary common wiring is reduced, there is an effect of preventing the display quality deterioration by position due to increased self-resistance.

Even if the auxiliary common wiring is formed to overlap the different layers with the first and second auxiliary common wiring, there is an advantage of not performing a separate additional mask process.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a schematic plan view of a portion of an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown, the array substrate 101 for a liquid crystal display device according to the present invention has an image display area AA for displaying an image in the center and a non-display area NA outside thereof.

In the display area AA, a plurality of gate lines 110 and a plurality of data lines 140 intersect with each other and define a plurality of pixel regions P. In addition, a plurality of common wires 118 are spaced apart from each other and parallel to the plurality of gate wires 110. Each pixel region P is connected to the gate line 110 and the data line 140, and has a gate electrode 111, a gate insulating layer (not shown), an active layer (not shown), and an ohmic contact layer (not shown). ) And a thin film transistor (Tr) including the source and drain electrodes 153 and 155 spaced apart from each other. In addition, a pixel electrode 180 having a bar shape is connected to each pixel region P through the drain electrode 155 and the drain contact hole 162 of the thin film transistor Tr and spaced apart at regular intervals. In addition, a plurality of bar-shaped common electrodes 120 alternate with the bar-shaped pixel electrodes 180 and electrically connected to the common wiring 118 are formed.

Meanwhile, the non-display area NA outside the display area AA having the above-described structure includes the gate pad part GPA having the gate pad electrode 122 formed on one side thereof, and the data pad electrode 145 on the other side thereof. The formed data pad part DPA is defined. In this case, a plurality of data link wires 142 connected to the plurality of data wires 140 are connected to ends of the plurality of data wires 140 and an external driving circuit (not shown). It is connected to the data pad electrode 145 at the same time.

In the non-display area NA, a plurality of data link wires 113 connected to the plurality of gate wires 110 are connected to the ends of the plurality of gate wires 110 and an external driving circuit in the gate pad part GPA. The gate pad electrode 122 is connected to the furnace (not shown) and is formed at the same time.

In addition, the gate pad part GPA has a first width that crosses the plurality of gate link wires 113 and has a first width in the same direction in which the data line 140 extends. The auxiliary common wiring 150 is formed, and the second auxiliary common wiring 182 overlaps with the first auxiliary common wiring 150. At this time, the first and second auxiliary common wiring (150, 182) is characterized in that it is electrically connected. In addition, the first auxiliary common wiring 150 is formed to have a width smaller than the separation gap between these two components in the region between the ends of each of the plurality of common wirings 118 and the gate pad electrode 122. It is characteristic that there is.

On the other hand, the second auxiliary common wiring 182 is a branched form and the end of each of the plurality of common wiring 118 located at a predetermined interval with respect to one side of the first and second auxiliary common wiring (150, 182) In addition, the plurality of branching portions 184 are electrically connected to the plurality of common wirings 118 through the first contact holes 164 formed by overlapping and exposing ends of the common wirings 118.

In addition, the third auxiliary common wiring 186 of the wiring form for connecting the ends of the plurality of branch portions 184 is characterized in that is further formed. In this case, a plurality of second contact holes 186 are formed to be spaced apart from the first contact holes 164 formed at each end of the common wiring 118 and to respectively expose one side of the first auxiliary common wiring 150. May be In this case, the first auxiliary common wiring 150 and the second auxiliary common wiring 182 naturally form a structure in contact with each other through the plurality of second contact holes 186. It is not necessary to form a separate third contact hole for conduction between the two auxiliary common wirings 150 and 182. However, by forming a separate third contact hole 167 at one end of the first auxiliary common wiring 150 and the second auxiliary common wiring 182 without forming the plurality of second contact holes 166. It may also be in a conductive state. That is, although both the second and third contact holes are illustrated in the drawing, at least one of the two contact holes may be formed.

Therefore, in the case of the array substrate 101 having the above-described structure, as in the prior art, connection patterns formed for electrical connection with the ends of the common wirings and the auxiliary common wirings are not formed corresponding to each common wiring, respectively, and the first auxiliary commons are used. The second auxiliary common wiring electrically connected to the wiring 150 is integrally connected through each common wiring 118 and the first contact hole 164 to connect the second auxiliary common wiring corresponding to the first contact hole. The third auxiliary common wiring 186 may be further configured to prevent contact failure, in particular, the contact failure through the second contact hole 166 between the first auxiliary common wiring 150 and the second auxiliary common wiring 182. have.

That is, even if a contact failure occurs in one second contact hole 166, the second auxiliary common wiring 182 is integrated, so that the second contact hole 166 is connected to the second contact hole 166 or the third contact hole 167. Since the whole is electrically connected to the first auxiliary common wiring 150, there is no problem in the electrical connection with the common wiring 118 that has a poor contact with the second contact hole 166. As a result, contact defects of up to 50% in the common wiring jumper can be reduced.

 In addition, the auxiliary auxiliary common wire 150 and the second auxiliary common wiring 182 overlap each other so as to have a parallel connection structure electrically connected through the second or third contact holes 166 and 167. Even if the line widths of the wirings 150 and 182 are reduced, the difference in the common voltage for each position due to the increase in resistance itself is reduced.

Hereinafter, the cross-sectional structure will be described with a cross-sectional view.

FIG. 5 is a cross-sectional view of a portion taken along the cutting line V-V of FIG. 4, and FIG. 6 is a cross-sectional view of a portion taken along the cutting line VI-VI of FIG. 5, and FIG. 7 is a cut line of FIG. 4. It is sectional drawing about the part cut along VIII-VIII.

As shown in the drawing, in the display area AA, the common wiring 118 is spaced apart from the gate wiring (not shown) in parallel with the gate wiring in one direction. In addition, in each pixel area P, a gate electrode 111 is formed by branching from the gate line (not shown), and branching from the common line 118 to form a plurality of bar-shaped common electrodes 120. Is formed. In this case, although the common electrode 120 is formed on the same layer as the common wiring 118, it is not formed on the same layer as the common wiring 118 and is formed on the same layer as the plurality of pixel electrodes 180. It may be formed of the same material.

In the non-display area NA, a plurality of gate link wirings 113 are formed on the substrate 101, and a plurality of gate link wirings 113 are formed on the substrate 101. A plurality of common wirings 118 are formed to extend. In addition, a gate pad electrode (not shown) is formed at an end of the gate link wiring 113.

Next, a gate insulating layer 122 is formed on the gate wiring (not shown) and the common wiring 118 as an inorganic insulating material on its entire surface. Above the gate insulating layer 122, a plurality of pixel regions P are defined in the display area AA to intersect the plurality of gate lines (not shown), and data lines 140 are formed. In the pixel region P, for example, a semiconductor layer 125 including an active layer 125a of pure amorphous silicon and an ohmic contact layer 125b of impurity amorphous silicon spaced apart from each other is formed corresponding to the gate electrode 111. The source and drain electrodes 153 and 155 are spaced apart from each other on the semiconductor layer 125 to form a thin film transistor Tr. In this case, the source electrode 153 is connected to the data line 140.

Meanwhile, in the data pad part DPA in the display area NA, a plurality of data link wires (not shown) are connected to each of the plurality of data wires 140 formed in the display area AA on the gate insulating layer 122. ) And a data pad electrode (not shown) is formed at each end of each of the plurality of data link wires (not shown). In the gate pad part GPA, the first auxiliary common wire 150 is formed on the gate insulating layer 122 to intersect the plurality of gate link wires 113. At this time, one side of the first common wiring 150 is not overlapped with the ends of each of the plurality of common wiring 118 is characterized in that formed at a predetermined interval apart.

In this case, according to the manufacturing method, as shown in the lower portion of the data line 140, the data link wiring (not shown), the data pad electrode (not shown) and the first auxiliary common wiring 150, The double layer semiconductor pattern 127 (127a, 127b) may be formed of the same material forming the 125a and the ohmic contact layer 125b, or may be omitted.

Next, a protective layer 160 is formed on the data line 140 and the first auxiliary common wiring 150 as an inorganic insulating material or an organic insulating material on the entire surface. In this case, a drain contact hole 162 exposing a part of the drain electrode 155 is formed to correspond to the drain electrode 155 of each pixel area P, and the gate pad part GPA of the display area NA is formed. The plurality of first contact holes 164 exposing one end of each of the plurality of common wirings 118 and the first auxiliary common wiring 150 are spaced apart from each of the first contact holes 164. A plurality of second contact holes 166 exposing the gaps is formed. In this case, although the plurality of second contact holes 166 may appear to correspond to the plurality of first contact holes 164 in the drawing, the plurality of second contact holes 166 may be formed in the first auxiliary common wiring. It is possible to correspond to any part on the 150. Although not shown in the drawings, third contact holes (not shown) may be formed corresponding to both ends of the first auxiliary common wiring 150. In this case, one of the plurality of second contact holes 166 and the third contact hole (not shown) may be omitted.

Although not shown in the drawings, gate and data pad contact holes (not shown) are formed to expose the gate and data pad electrodes (not shown), respectively, corresponding to the gate and data pad electrodes (not shown). In addition, when each of the plurality of common electrodes 120 is not formed on the same layer as the common wiring 118 in each pixel region P, the common wiring 118 in each pixel region P is exposed. The common contact hole (not shown) may be further formed.

Next, in the display area AA, the passivation layer 160 is in contact with the drain electrode 155 through the drain contact hole 162 to be spaced apart from each other in a bar shape. The plurality of pixel electrodes 180 are alternately formed with the plurality of common electrodes 120 formed on the same layer as the common wiring 118. In this case, when the plurality of common electrodes 120 are not formed on the same layer as the common wiring 118, the plurality of pixel electrodes may be in contact with the common wiring 118 through the common contact hole (not shown). In the same layer as that of 180), a plurality of common electrodes may be formed with the same material.

Next, in the non-display area NA, the gate and data pad electrodes (not shown) correspond to the gate and data pad electrodes (not shown) on the passivation layer 160 (not shown). And an auxiliary gate and a data pad electrode (not shown) are formed in contact with each other. In addition, in the gate pad part GPA, a second auxiliary common wiring 182 is formed to overlap with the first auxiliary common wiring 150 and have a wiring shape, and the second auxiliary common wiring 182 is common to each other. A plurality of branching portions 184 are formed to branch corresponding to the ends of the wiring 118, and all the ends of the branching portions 184 are connected to each other, and a third auxiliary common wiring 186 is formed in the form of wiring. In this case, each of the plurality of branch portions 184 is in contact with the common wiring 118 through the first contact hole 164 exposing the end of the common wiring 118.

In addition, the second auxiliary common wiring 182 forms an electrically parallel structure by contacting the first auxiliary common wiring 150 through a plurality of second contact holes 166 or third contact holes (not shown). It is characterized by being connected.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described.

8A to 8G are cross-sectional views illustrating manufacturing steps of a portion cut along the cutting line V-V of FIG. 4, and FIGS. 9A to 9G are manufacturing steps of a portion cut along the cutting line VI-VI of FIG. 4. It is process sectional drawing, FIG. 10A-FIG. 10G is sectional drawing of process steps about the part which cut | disconnected FIG. 4 along the cutting line VIII-VIII.

First, as shown in FIGS. 8A, 9A, and 10A, a first metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, and the like may be formed on a transparent insulating substrate 101. After depositing chromium (Cr) to form a metal layer (not shown), a photoresist having photosensitivity thereon is coated on the entire surface, and the photoresist is exposed to light using a mask, and then developed. Etching the metal layer (not shown) exposed to the outside of the developed photoresist, and patterning the metal layer (not shown) by performing a mask process including a series of steps of stripping the photoresist. ), A plurality of gate wirings (not shown) and common wirings 118 are formed, and in each pixel region P, a gate electrode 111 connected to the gate wiring (not shown) and the common wiring 118 are formed. Bar diverging from Womb to form the common electrode 120. At the same time, in the display area NA, a plurality of gate link wires 113 connected to the plurality of gate lines (not shown) and gate pad electrodes (not shown) connected to the respective gate link wires 113 are formed. . In this case, the common line 118 is formed such that an end thereof extends to the gate pad part GPA.

Next, as illustrated in FIGS. 8B, 9B, and 10B, the gate wiring (not shown), the data electrode 111, the gate link wiring 113, the common wiring 118, the common electrode 120, and the like may be formed. An inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the formed substrate 101 to form the gate insulating layer 122.

Subsequently, as shown in FIGS. 8C, 9C, and 10C, pure amorphous silicon, impurity amorphous silicon, and a second metal material, such as molybdenum (Mo), copper (Cu), and chromium, may be disposed on the gate insulating layer 122. Cr) is continuously deposited to form a pure amorphous silicon layer (not shown), an impurity amorphous silicon layer (not shown), and a metal material layer (not shown). Thereafter, a photoresist is formed on the metal material layer (not shown) to form a photoresist layer (not shown), and a transmission region for transmitting 100% of light, a blocking region for blocking 100% of light, and an amount of light transmission. The gate insulating layer 122 is formed in the display area AA by performing a mask process including diffraction exposure or halftone exposure through an exposure mask (not shown) configured as a transflective area that can be adjusted between 0% and 100%. The data line 140 is defined to define the pixel region P by crossing the plurality of gate lines (not shown). In each pixel area P, a semiconductor layer 125 including an active layer 125a and an ohmic contact layer 125b corresponding to the gate electrode 111, and source and drain electrodes 153 spaced apart from each other above the gate electrode 111. , 155). Further, in the data pad unit DPA in the non-display area NA, data link wires (not shown) connected to the plurality of data wires 140, respectively, and data at ends of the data link wires (not shown). A pad electrode (not shown) is formed. In the non-display area NA, the gate pad part GPA intersects the gate link wires 113 on the gate insulating film 122 to form a first auxiliary common wire 150 having a wiring shape. . In this case, the active layer 125a and the ohmic contact are disposed under the data line 140, the data link wiring (not shown), the data pad electrode (not shown), and the first auxiliary common wiring 150. The double layer semiconductor pattern 127 (127a, 127b) is formed of the same material forming the layer 125b. However, the semiconductor pattern 127 first patterns the pure and amorphous silicon layers through a single mask process, and then forms a metal material layer and then proceeds to another mask process to form the source and drain electrodes 153 and 155 and data. When the wire 140 and the data link wiring (not shown) and the first auxiliary common wiring 150 are formed, they may be omitted.

Next, as shown in FIGS. 8D, 9D, and 10D, the data line 140, the data link line (not shown), the source and drain electrodes 153 and 155, and the first auxiliary common line 150 are disposed on the data line 140. An inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface to form a protective layer 160. In this case, the protective layer 160 may be made of an organic insulating material. Afterwards, the protective layer 160 is patterned by a mask process to form a drain contact hole 162 exposing a portion of the drain electrode 155 in the lower portion of each pixel area P in the display area AA. do. At the same time, in the non-display area NA, a plurality of first contact holes 164 exposing ends of the common wiring 118 and the plurality of first contact holes 164 are spaced apart from each other. A plurality of second contact holes 166 are formed to partially expose the common wiring 150. Further, gate and data pad contact holes (not shown) are formed to correspond to the gate and data pad electrodes (not shown), respectively. In this case, a third contact hole (not shown) may be further formed to correspond to an end portion of the first auxiliary common wiring 150. On the other hand, when the common electrode 120 is not formed on the same layer as the common wiring 118 as a modification, a common contact hole (not shown) for exposing the common wiring in each pixel area P is further formed. You may.

Next, as shown in FIGS. 8E, 9E, and 10E, the first, second, and third contact holes 164, 166 (not shown), the drain contact hole 162, and the gate and data pad contact holes (not shown). ), A conductive material, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or molybdenum (MoTi) is deposited on the passivation layer 160, and is patterned by performing a mask process. As a result, in each pixel area P of the display area AA, the protective layer 160 contacts the drain electrode 155 through the drain contact hole 162 and alternates with the plurality of common electrodes 120. A pixel electrode 180 having a bar shape is formed. In addition, in the non-display area NA, a gate and a data pad electrode (not shown) contacting through each gate and data pad electrode (not shown) and the gate and data pad contact hole (not shown) are formed. do. In addition, the second auxiliary common wiring 182 may be in contact with and overlap the first auxiliary common wiring 150 through the plurality of second contact holes 166 corresponding to the first auxiliary common wiring 150. ) And at the same time overlap the ends of each common wiring 118 in the second auxiliary common wiring 182 and at the same time contact the common wiring 118 through each of the plurality of first contact holes 164. Branch portion 184 is formed. In addition, by forming a third auxiliary common wiring 186 connecting the ends of the plurality of branches 184, the array substrate 101 for a transverse electric field type liquid crystal display device according to the present invention is completed. In this case, when the common contact hole is formed, a plurality of common electrodes may be formed on the same layer in contact with the common wiring through the common contact hole and alternately with the plurality of bar-shaped pixel electrodes. It may be.

1 is a schematic plan view of a conventional array substrate for a transverse electric field type liquid crystal display device.

FIG. 2 is a cross-sectional view of the portion of the array substrate taken along cut line II-II of FIG. 1; FIG.

3 is a cross-sectional view of a portion of the portion taken along the cutting line III-III of FIG.

4 is a schematic plan view of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

5 is a cross-sectional view of a portion cut along line V-V in Fig. 4; Fig.

FIG. 6 is a cross-sectional view of a portion cut along the cutting line VI-VI of FIG. 4. FIG.

FIG. 7 is a cross-sectional view of a portion cut along the cutting line VIII-VIII in FIG. 4. FIG.

8A to 8E are cross-sectional views of manufacturing steps of the portion cut along the cutting line VV of FIG. 4.

9A to 9E are cross-sectional views of manufacturing steps of a portion cut along the cutting line VI-VI of FIG. 4.

10A to 10E are cross-sectional views of the manufacturing steps for the portion cut along the cutting line VIII-VIII in Fig. 4;

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

101: array substrate 110: gate wiring

111: gate electrode 113: gate link wiring

118: common wiring 120: common electrode

122: gate pad electrode 125: semiconductor layer

140: data wiring 142: data link wiring

145: data pad electrode 150: first auxiliary common wiring

153 source electrode 155 drain electrode

162: drain contact hole 164: first contact hole

166: second contact hole 167: third contact hole

168: gate pad contact hole 170: data pad contact hole

180: pixel electrode 182: second auxiliary common wiring

184: branching section 186: third auxiliary common wiring

Claims (10)

A plurality of gate wirings and data wirings formed on the display area for displaying an image and crossing a surface of the substrate on which a non-display area is defined outside the display area to define a plurality of pixel areas in the display area; A plurality of common lines formed side by side on the same layer as the gate lines and extending to the non-display area; A plurality of gate link wirings connected to the gate wirings in the non-display area; A gate insulating film covering the plurality of gate link wirings and formed on an entire surface of the substrate; A first auxiliary common line formed on the gate insulating layer corresponding to the non-display area and crossing the plurality of gate link lines and formed of the same material as the data line; A plurality of first contact holes covering the first auxiliary common wiring and exposing ends of each of the plurality of common wirings; and a plurality of second contact holes exposing the first auxiliary common wiring and formed on the front surface of the substrate. A protective layer formed; Over the protective layer, the first auxiliary common wiring overlaps the first auxiliary common wiring, and contacts the first auxiliary common wiring through the plurality of second contact holes, and simultaneously contacts the plurality of common wirings through the plurality of first contact holes. Second auxiliary common wiring formed / RTI > The second auxiliary common wiring includes a plurality of branching portions extending to ends of each of the plurality of common wirings, and each of the plurality of branching portions contacts each of the plurality of common wirings through the plurality of first contact holes. , And a third auxiliary common wiring connecting both ends of each of the plurality of branch portions. The method of claim 1, A plurality of thin film transistors connected to the plurality of gates and data wires in the plurality of pixel regions, the plurality of thin film transistors comprising a source electrode and a drain electrode connected to a gate electrode, the gate insulating film, and a semiconductor layer formed on the gate insulating film, and spaced apart from each other; Wow; A plurality of pixel electrodes electrically connected to the drain electrodes of each of the plurality of thin film transistors and including a plurality of first bars; A plurality of common electrodes electrically connected to each of the plurality of common wires and including a plurality of second bars alternately formed with the plurality of first bars; A plurality of data link wirings connected to the plurality of data wirings Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 2, And wherein the plurality of common electrodes are formed on the same layer as the plurality of common wires or on the same layer as the plurality of pixel electrodes. delete delete Preparing a substrate including a display area for displaying an image and a non-display area outside the display area; A plurality of gate wires on the display area, a plurality of common wires spaced apart from the plurality of gate wires and extending from the display area to the non-display area, and a plurality of gate wires connected to the plurality of gate wires in the non-display area Forming a gate link wiring line; Forming a gate insulating film on the substrate including the plurality of gate wirings, the plurality of common wirings, and the plurality of gate link wirings; Forming a plurality of data wires on the gate insulating layer corresponding to the non-display area to define pixel regions crossing the plurality of gate wires, and a first auxiliary common wire crossing the plurality of gate link wires; ; A plurality of first contact holes exposing the plurality of common lines positioned in the non-display area on the gate insulating layer including the plurality of data lines and the first auxiliary common line, and exposing the first auxiliary common line. Forming a protective layer having a plurality of second contact holes; Overlapping the first auxiliary common wiring over the protective layer and contacting the first auxiliary common wiring through the plurality of second contact holes, and simultaneously contacting the plurality of common wiring through the plurality of first contact holes. Forming a second auxiliary common wiring / RTI > The second auxiliary common wiring has a plurality of branching portions extending to ends of each of the plurality of common wirings, and each of the plurality of branching portions contacts each of the plurality of common wirings through the plurality of first contact holes. And forming a third auxiliary common wiring connecting the ends of each of the plurality of branched portions to each other. delete delete delete delete

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