KR101338903B1 - Display panel, display apparatus having the panel and method for driving the apparatus - Google Patents

Abstract

Disclosed are a display panel having an improved display quality of an image, a display device having the same, and a driving method thereof. The display panel includes scan wirings, data wirings, organic light emitting diodes, and first and second current controllers. The scan wiring includes first and second sub scan wirings formed adjacent to each other, the data wiring is formed to cross the scan wiring, and the organic light emitting element is supplied with a source current of a source power source to generate light. The first current controller is electrically connected to the first sub scan wiring and the data wiring, the second current controller is electrically connected to the second sub scan wiring and the data wiring, and the first and second current controllers are in parallel with the organic light emitting diode. Is electrically connected to the Here, during the unit period, the first current controller is operated in a light emitting mode for controlling the amount of source current, and the second current controller is operated in a recovery mode for restoring internal characteristics, thereby improving display quality of the display panel. have.

First current controller, second current controller, first scan wiring, second scan wiring

Description

DISPLAY PANEL, DISPLAY APPARATUS HAVING THE PANEL AND METHOD FOR DRIVING THE APPARATUS}

1 is a block diagram conceptually showing a display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram conceptually illustrating a unit pixel of the display panel of FIG. 1.

3 is a circuit diagram illustrating an example of a unit pixel of FIG. 2.

4A, 4B, and 4C are waveform diagrams illustrating a first sub scan signal, a second sub scan signal, and a data signal of FIG. 3.

FIG. 5 is a circuit diagram illustrating another example of the unit pixel of FIG. 2.

6 is a waveform diagram illustrating a source voltage, a first sub scan signal, a second sub scan signal, and a data signal of FIG. 5.

<Explanation of symbols for the main parts of the drawings>

100: timing controller 110: negative voltage generator

200: scan driver 300: data driver

400: display panel 410: organic light emitting device

420: first current controller 430: second current controller

T1: first drive transistor T2: second drive transistor

SL: Scan Wiring SL1: First Sub Scan Wiring

SL2: second sub-scan wiring DL: data wiring

M-con: Image control signal S-con: Scan control signal

D-con: Data control signal SS: Scan signal

SS1: first sub scan signal SS2: second sub scan signal

DS: Data Signal VDS: Source Voltage

VSS: Sink Voltage

The present invention relates to a display panel, a display device having the same, and a driving method thereof, and more particularly, to a display panel having an improved display quality of an image, a display device having the same, and a driving method thereof.

The organic light emitting display device, which is one of the flat panel displays, includes a scan wiring formed in a first direction, a data wiring formed in a second direction perpendicular to the first direction, a driving transistor controlled by the scan wiring and the data wiring, and the driving. Organic light emitting diodes (OLEDs) controlled by transistors to generate light are included.

Specifically, the driving transistor controls the amount of source current applied from the source power source to the organic light emitting device to control the light emission luminance of the organic light emitting device. That is, the amount of the source current flowing through the channel of the driving transistor is controlled according to the data voltage of the amount applied to the gate terminal of the driving transistor, and the emission luminance of the organic light emitting element is controlled to the amount of the source current.

However, since the driving transistor is generally an amorphous silicon thin film transistor (a-Si TFT), when the positive data voltage is continuously applied to the gate terminal of the driving transistor, the driving transistor deteriorates. The threshold voltage can be changed. In this case, the threshold voltage refers to a minimum voltage required for the source current to pass through the channel of the driving transistor.

As such, when the threshold voltage of the driving transistor is changed due to degradation, the light emission luminance of the organic light emitting diode may be changed, and thus the display quality of the organic light emitting diode display may be degraded.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display panel with improved display quality by suppressing deterioration of a driving transistor.

Another object of the present invention is to provide a display device having the display panel described above.

Still another object of the present invention is to provide a method of driving the display device.

The display panel according to an exemplary embodiment of the present invention includes a scan wiring, a data wiring, an organic light emitting diode, a first current controller, and a second current controller.

The scan wiring includes a first sub scan wiring and a second sub scan wiring formed adjacent to each other in a first direction. The data line is formed in a second direction crossing the first direction. The organic light emitting device generates light by receiving a source current from a source power source.

The first current controller is electrically connected to the first sub scan wiring, the data wiring, and the organic light emitting diode, and controls the first current during one unit section to control the amount of the source current supplied to the organic light emitting diode. It is operated in the light emitting mode. The second current controller is electrically connected to the second sub scan wiring and the data wiring, and is electrically connected to the organic light emitting device in parallel with the first current controller, and to restore the deteriorated internal characteristics. The second recovery mode is operated during the unit section.

Further, during the next unit section after the one unit section, the first current controller is operated in a first recovery mode to restore the internal characteristics degraded by the first light emitting mode, and the second current controller is configured to emit the organic light. The second light emitting mode is operated to control the amount of the source current supplied to the device.

Meanwhile, the first current controller includes a first driving transistor for operating in the first emission mode and the first recovery mode, and the second current controller operates in the second emission mode and the second recovery mode. It is preferred to include a second drive transistor to be. Here, when a positive data voltage is applied to the gate terminal of the first driving transistor, the first current controller is operated in the first light emitting mode, and a negative recovery voltage is applied to the gate terminal of the first driving transistor. The first current controller is operated in the first recovery mode, and when a positive data voltage is applied to the gate terminal of the second driving transistor, the second current controller is operated in the second emission mode. When a negative recovery voltage is applied to the gate terminal of the second driving transistor, the second current controller is operated in the second recovery mode.

In accordance with another aspect of the present invention, a display device includes a timing controller, a scan driver, a data driver, and a display panel.

The timing controller outputs a scan control signal and a data control signal in response to an external image control signal. The scan driver outputs a scan signal in response to the scan control signal. The data driver outputs a data signal in response to the data control signal.

The display panel displays an image in response to the scan signal and the data signal. In detail, the display panel is configured such that scan lines are applied to the display panel, scan wirings having first and second sub scan wirings adjacent to each other in a first direction, and the data signal are applied to the display panel. A data line formed in a second direction crossing the second direction, an organic light emitting element configured to generate light by receiving a source current from a source power source, and electrically connected to the first sub scan line, the data line, and the organic light emitting element, In order to control the amount of the source current supplied to the organic light emitting device is electrically connected to the first current control unit which is operated in the first light emitting mode during any one unit section, the second sub-scan wiring and the data wiring, The one stage is electrically connected to the organic light emitting device in parallel with the first current controller, to restore the deteriorated internal characteristics. First and a second electric current control section 2 operates in the recovery mode during intervals.

According to another aspect of the present invention, there is provided a method of driving a display device, wherein the first current controller emits first light to control the amount of source current supplied to the organic light emitting diode during the first period. Operating the second current controller in the second recovery mode, and operating the second current controller in the second light emitting mode to control the amount of the source current during the second period. And operating the first current controller degraded by the first light emitting mode in a first recovery mode. In this case, the first and second sections are preferably repeated every at least one frame.

According to the present invention, when the first current control unit is operated in the first light emitting mode, the second current control unit is operated in the second recovery mode, when the first current control unit is operated in the first recovery mode, the second current As the controller is operated in the second light emitting mode, the controller may suppress the deterioration of the driving transistor in the display device, thereby further improving display quality.

Hereinafter, with reference to the drawings will be described in detail preferred embodiments of the present invention.

1 is a block diagram conceptually illustrating a display device according to an exemplary embodiment of the present invention.

The display device according to the present embodiment will be described with reference to FIG. 1.

The display device according to the present exemplary embodiment includes a timing controller 100, a scan driver 200, a data driver 300, and a display panel 400.

The timing controller 100 controls the scan driver 200 and the data driver 300 in response to an image control signal M-con applied from an external graphic controller.

In detail, the timing controller 100 outputs a scan control signal S-con for controlling the scan driver 200 in response to the image control signal M-con, and the data driver 300. Output a data control signal (D-con) to control the. In this case, the image control signal M-con, the scan control signal S-con and the data control signal D-con are all digital signals.

The timing controller 100 may include a negative voltage generator 110 to generate a data value for a negative recovery voltage applied to the display panel 400. A detailed description of the negative voltage generator 110 will be described later.

The scan driver 200 outputs a scan signal SS to the display panel 400 in response to the scan control signal S-con. In this case, the scan signal SS is actually an analog signal for driving the display panel 400.

The data driver 300 outputs the data signal DS to the display panel 400 in response to the data control signal D-con. In this case, the data signal DS is actually an analog signal having a data voltage for driving the display panel 400.

The display panel 400 displays an image in response to the scan signal SS and the data signal DS. The display panel 400 includes an organic light emitting diode that is controlled by the scan signal SS and the data signal DS and emits light.

FIG. 2 is a circuit diagram conceptually illustrating a unit pixel of the display panel of FIG. 1.

1 and 2, the display panel 400 according to the present exemplary embodiment includes a scan line SL, a data line DL, an organic light emitting element 410, a first current controller 420, and a second current. The control unit 430 is included.

The plurality of scan lines SL are formed in a first direction, and transmit the scan signals SS applied from the scan driver 200.

The scan line SL includes a first sub scan line SL1 and a second sub scan line SL2 formed adjacent to each other. In this case, the scan signal SS may receive the first sub scan signal SS1 applied to the first sub scan wiring SL1 and the second sub scan signal SS2 applied to the second sub scan wiring SL2. Include.

A plurality of data lines DL are formed in a second direction crossing the first direction, and transmit the data signal DS applied from the data driver 300. In this case, the second direction is preferably perpendicular to the first direction.

Meanwhile, a plurality of scan lines SL and data lines DL are formed in a direction crossing each other to define a plurality of unit pixels. In one example, the unit pixels have a rectangular shape. The organic light emitting element 410, the first current controller 420, and the second current controller 430 are formed in each unit pixel.

The organic light emitting element 410 generates light by receiving a source current from a source power source (not shown). Specifically, a hole supplied from an anode of the organic light emitting element 410 and an electron supplied from a cathode of the organic light emitting element 410 combine with each other to excite ( excited atoms) and these excitons fall into a low energy state to generate light.

In the organic light emitting diode 410, the anode is electrically connected to the source power source, and the cathode is electrically connected to a sink power source (not shown). In this case, the source power source has a source voltage VDS, and the sink power source has a sink voltage VSS.

The first and second current controllers 420 and 430 are disposed in parallel between the organic light emitting element 410 and the source power source, and are electrically connected to the organic light emitting element 410 and the source power source. That is, one end of the first and second current controllers 420 and 430 is electrically connected to an anode of the organic light emitting device, and the other end is electrically connected to the source power source.

The first current controller 420 is electrically connected to the first sub scan line SL1 and the data line DL to receive the first sub scan signal SS1 and the data signal DS. .

The second current controller 430 is electrically connected to the second sub scan line SL2 and the data line DL to receive the second sub scan signal SS2 and the data signal DS. .

On the other hand, the first current controller 420 has a first light emission mode for controlling the amount of the source current supplied from the source power source to the organic light emitting element 410 and the internal characteristics degraded by the first light emission mode It is operated in any one of the first recovery mode to recover the.

In addition, the second current controller 420 may have a second light emission mode for controlling the amount of the source current supplied from the source power source to the organic light emitting element 410 and an internal characteristic degraded by the second light emission mode. It is operated in any one of the second recovery mode for recovering.

Specifically, during one unit period, the first current controller 420 is operated in the first light emitting mode, and the second current controller 430 is operated in the second recovery mode. Subsequently, during the next unit section after the unit section, the second current controller 430 is operated in the second light emitting mode, and the first current controller 420 is operated in the first recovery mode.

Therefore, while the first current controller 420 is operated in the first light emitting mode to control the light emission of the organic light emitting element 410, the second current controller 430 is deteriorated in the second light emitting mode. The second recovery mode is operated to restore the internal characteristics. On the other hand, while the second current controller 430 operates in the second light emitting mode to control light emission of the organic light emitting element 410, the first current controller 420 deteriorates in the first light emitting mode. It is operated in the first recovery mode to recover the internal characteristics.

3 is a circuit diagram illustrating an example of a unit pixel of FIG. 2. In this case, the first and second current controllers 420 and 430 illustrated in FIG. 3 illustrate one embodiment of a circuit operated by a voltage writing method.

Referring to FIG. 3, the first current controller 420 includes a first driving transistor T1, a first switching transistor SW1, and a first driving capacitor Cst1, and the second current controller 430. Includes a second driving transistor T2, a second switching transistor SW2, and a second driving capacitor Cst2.

First, the components of the first current controller 420 will be described.

In the first driving transistor T1, a drain terminal is electrically connected to an anode of the organic light emitting element 410, and a source terminal is electrically connected to the source power source. Therefore, the source voltage VDS of the source power source is applied to the source terminal of the first driving transistor T1.

In the first switching transistor SW1, a gate terminal is electrically connected to the first sub scan line SL1, a source terminal is electrically connected to the data line DL, and a drain terminal is connected to the first driving transistor. It is electrically connected to the gate terminal of T1.

One end of the first driving capacitor Cst1 is electrically connected to a gate terminal of the first driving transistor T1, and the other end of the first driving capacitor Cst1 is electrically connected to a source terminal of the first driving transistor T1.

Next, components of the second current controller 430 will be described.

In the second driving transistor T2, a drain terminal is electrically connected to an anode of the organic light emitting element 410, and a source terminal is electrically connected to the source power source. In this case, the second driving transistor T2 is electrically connected to the anode of the organic light emitting element 410 and the source power source to be disposed in parallel with the first driving transistor T1.

The second switching transistor SW2 has a gate terminal electrically connected to the second sub scan line SL2, a source terminal electrically connected to the data line DL, and a drain terminal of the second driving transistor SW2. Is electrically connected to the gate terminal of T2).

One end of the second driving capacitor Cst2 is electrically connected to the gate terminal of the second driving transistor T2, and the other end thereof is electrically connected to the source terminal of the second driving transistor T2.

Meanwhile, the first driving transistor T1, the first switching transistor SW1, the second driving transistor T2, and the second switching transistor SW2 may be thin film transistors made of amorphous silicon (a-Si).

4A, 4B, and 4C are waveform diagrams illustrating a first sub scan signal, a second sub scan signal, and a data signal of FIG. 3.

4A, 4B, and 4C, how the display device illustrated in FIGS. 1 and 3 is driven will be described.

First, referring to FIG. 4A, when the horizontal period 1H of the Nth frame is started by the first sub scan signal SS1 transmitted to the first sub scan line SL1, the first sub scan line SL1 starts. The first switching transistor SW1 is turned on by the first sub scan signal SS1 so that the data signal DS transmitted to the data line DL is the first driving transistor T1. Is applied to the gate terminal of (where N is an integer). In this case, since the data signal DS has a positive data voltage Vdat corresponding to the first sub scan signal SS1, the gate terminal of the first driving transistor T1 has the positive data voltage ( Vdat) is applied.

The positive data voltage Vdat applied to the gate terminal of the first driving transistor T1 is stored by the first driving capacitor Cst1. The positive data voltage Vdat stored as described above controls the organic light emitting diode 410 until the negative recovery voltage Vrfs is applied in the next frame.

Subsequently, when the second sub scan signal SS2 is applied to the second sub scan line SL2 after the first sub scan signal SS1, the second switching transistor SW2 is applied to the second sub scan. The data is turned on by the signal SS2 to transfer the data signal DS to the gate terminal of the second driving transistor T2. In this case, since the data signal DS has a negative recovery voltage Vrfs corresponding to the second sub scan signal SS2, the negative recovery voltage (V) is applied to a gate terminal of the second driving transistor T2. Vrfs) is applied.

The negative recovery voltage Vrfs applied to the gate terminal of the second driving transistor T2 is stored by the second driving capacitor Cst2 so that a new positive data voltage Vdat is applied in the next frame. Until the internal characteristics of the second driving transistor T2 are restored.

Here, the first and second sub scan signals SS1 and SS2 are signals that transmit a high level voltage during the time period in which the horizontal period 1H is divided into two parts. Preferably, each of the first and second sub-scan signals SS1 and SS2 is connected to the high level at the first and second sub-scan wirings SL1 and SL2 for about half of the horizontal period 1H. transmit a high level voltage. The data signal has the positive data voltage Vdat and the negative recovery voltage Vrfs corresponding to the first and second sub scan signals SS1 and SS2.

We will look at the case where the N + 1th frame ((N + 1) th Frame) starts after the Nth frame ends.

When the horizontal period 1H of the N + 1 th frame is started by the first sub scan signal SS1, the first switching transistor SW1 is turned on by the first sub scan signal SS1. The negative recovery voltage Vrfs of the data signal DS is applied to the gate terminal of the first driving transistor T1. The negative recovery voltage Vrfs applied in this way is stored by the first driving capacitor Cst1, and the inside of the first driving transistor T1 until the positive data voltage Vdat is applied in the next frame. Restore the characteristic.

Subsequently, when the second sub scan signal SS2 is applied after the first sub scan signal SS1, the second switching transistor SW2 is turned on by the second sub scan signal SS2. on), the positive data voltage Vdat of the data signal DS is transferred to the gate terminal of the second driving transistor T2. The positive data voltage Vdat applied as described above is stored by the second driving capacitor Cst2 to control the organic light emitting element 410 until the negative recovery voltage Vrfs is applied in the next frame. Play a role.

In general, when the positive data voltage Vdat is continuously applied to the gate terminals of the first and second driving transistors T1 and T2, the first and second driving transistors T1 and T2 deteriorate to a threshold. The voltage can be changed. In this case, the threshold voltage refers to a minimum voltage required for the source current generated from the source power to pass through the channels of the first and second driving transistors T1 and T2.

When the negative recovery voltage Vrfs is continuously applied to the gate terminals of the deteriorated first and second driving transistors T1 and T2, the threshold voltage can be suppressed from being changed. That is, the first and second driving transistors T1 and T2 deteriorated by the positive data voltage Vdat may be restored by the negative recovery voltage Vrfs to maintain the threshold voltage constant. have.

As described above, when the positive data voltage Vdat is applied to the gate terminal of the first driving transistor T1, the negative recovery voltage Vrfs is applied to the gate terminal of the second driving transistor T2. By applying this, the internal characteristics of the second driving transistor T2 are restored, while when the positive data voltage Vdat is applied to the gate terminal of the second driving transistor T2, the first driving transistor is applied. The negative recovery voltage Vrfs is applied to the gate terminal of T1 to restore internal characteristics of the first driving transistor T1. Therefore, even when the display panel 400 is driven for a long time, the threshold voltages of the first and second driving transistors T1 and T2 may be kept constant, thereby maintaining uniform emission luminance of the organic light emitting diode. Can be.

4B, the above-described processes may be repeated every M frames, provided that M is an integer greater than one.

Specifically, a positive data voltage Vdat is applied to the gate terminal of the first driving transistor T1 from the Nth frame to the M frame to control the light emission of the organic light emitting element 410, and the second A negative recovery voltage Vrfs is applied to the gate terminal of the driving transistor T2 to restore internal characteristics of the second driving transistor T2.

On the other hand, a positive data voltage Vdat is applied to the gate terminal of the second driving transistor T2 from the N + Mth frame to the M frame to continuously control the light emission of the organic light emitting element 410, and The negative recovery voltage Vrfs is applied to the gate terminal of the first driving transistor T2 to restore the internal characteristics of the first driving transistor T1.

As described above, when the negative recovery voltage Vrfs is applied to the gate terminals of the first and second driving transistors T1 and T2 deteriorated by the positive data voltage Vdat for a long time, that is, for an M frame. The internal characteristics of the first and second driving transistors T1 and T2 may be restored more effectively.

Subsequently, referring to FIG. 4C, unlike in FIG. 4B, the order of the first and second sub scan signals SS1 and SS2 in the N + M-th frame may be reversed. That is, in the N + Mth frame, the second sub scan signal SS1 may be applied before the first sub scan signal SS1. Therefore, the data signal DS consists of the positive data voltage Vdat and the negative recovery voltage Vrfs.

Meanwhile, referring again to FIG. 1, the timing controller 100 may include a negative voltage generator 110 generating a data value for the negative recovery voltage Vrfs of the data signal DS.

The negative voltage generator 110 includes a data value for the negative recovery voltage Vrfs in the data control signal D-con. That is, the timing controller 100 outputs the data control signal D-con including the data value for the negative recovery voltage Vrfs to the data driver 300. In this case, the negative recovery voltage Vrfs is large enough to restore internal characteristics of the first and second driving transistors T1 and T2 deteriorated by the positive data voltage Vdat in the previous frame. desirable.

The negative voltage generator 110 may generate a data value for the negative recovery voltage Vrfs by a frame memory (not shown) or a look-up table, and the display panel 400 The data value for the negative recovery voltage Vrfs may be changed during driving of.

In addition, the negative voltage generator 110 obtains an average value by adding up the positive data voltages Vdat applied during the M frames, and then multiplies a conversion weighting factor to thereby convert the negative recovery voltages Vrfs. Can generate a data value for.

FIG. 5 is a circuit diagram illustrating another example of the unit pixel of FIG. 2. In this case, the first and second current controllers 420 and 430 illustrated in FIG. 5 illustrate one embodiment of a circuit operated by a current write method.

Referring to FIG. 5, the first current controller 420 includes a first driving transistor T1, a first switching transistor SW1, a second switching transistor SW2, and a first driving capacitor Cst1. The second current controller 430 includes a second driving transistor T2, a third switching transistor SW3, a fourth switching transistor SW4, and a second driving capacitor Cst2.

First, the components of the first current controller 420 will be described.

In the first driving transistor T1, a drain terminal is electrically connected to an anode of the organic light emitting element 410, and a source terminal is electrically connected to the source power source. Therefore, the source voltage VDS of the source power source is applied to the source terminal of the first driving transistor T1.

In the first switching transistor SW1, a gate terminal is electrically connected to the first sub scan wiring SL1, a source terminal is electrically connected to a source terminal of the first driving transistor T1, and a drain terminal is The gate terminal of the first driving transistor T1 is electrically connected.

The second switching transistor SW2 has a gate terminal electrically connected to the first sub scan line SL1, a source terminal electrically connected to the data line DL, and a drain terminal of the second driving transistor SW2. It is electrically connected to the drain terminal of (T1).

One end of the first driving capacitor Cst1 is electrically connected to the gate terminal of the first driving transistor T1, and the other end of the first driving capacitor Cst1 is electrically connected to the drain terminal of the first driving transistor T1.

Next, components of the second current controller 430 will be described.

In the second driving transistor T2, a drain terminal is electrically connected to an anode of the organic light emitting element 410, and a source terminal is electrically connected to the source power source. Therefore, the source voltage VDS of the source power source is applied to the source terminal of the second driving transistor T2.

In the third switching transistor SW3, a gate terminal is electrically connected to the second sub scan wiring SL2, a source terminal is electrically connected to a source terminal of the second driving transistor T2, and the drain terminal is The gate terminal of the second driving transistor T2 is electrically connected.

The fourth switching transistor SW4 has a gate terminal electrically connected to the second sub scan line SL2, a source terminal electrically connected to the data line DL, and a drain terminal of the fourth driving transistor SW4. It is electrically connected to the drain terminal of T2.

One end of the second driving capacitor Cst2 is electrically connected to the gate terminal of the second driving transistor T2, and the other end of the second driving capacitor Cst2 is electrically connected to the drain terminal of the second driving transistor T2.

Meanwhile, the first driving transistor T1, the first switching transistor SW1, the second switching transistor SW2, the second driving transistor T2, the third switching transistor SW3, and the fourth switching transistor SW4 are provided. It is preferable that the thin film transistors are made of amorphous silicon (a-Si).

6 is a waveform diagram illustrating a source voltage, a first sub scan signal, a second sub scan signal, and a data signal of FIG. 5.

Referring to FIG. 6, the waveform diagrams shown in FIG. 6 will be briefly described, and how the display device shown in FIGS. 1 and 5 will be described.

First, the source voltage VDS in the source power supply periodically changes to a high level value and a low level value. For example, the source voltage VDS has 15V and 0V periodically.

The first and second sub scan signals SS1 and SS2 have a low level when the source voltage VDS has a high level, and the source voltage VDS has a low level. When it has a high level value.

Specifically, the first and second sub scan signals SS1 and SS2 have high level values once, when the source voltage VDS has a low level value during an Nth frame or an N + Mth frame. (Where N is an integer and M is an integer of 1 or more). That is, when the first sub scan signal SS1 has a high level value, the second sub scan signal SS1 has a low level value, and the second sub scan signal SS2 has a high level value. When the value has a value, the first sub scan signal SS1 has a low level value. The order in which the first and second sub-scan signals SS1 and SS2 have high-level values may be reversed in the Nth frame and the N + Mth frame, but may be the same.

The data signal includes a zero voltage Vzero and a data current Idat in response to the first and second sub scan signals SS1 and SS2 having high level values. In this case, the order of the zero voltage (Vzero) and the data current (Idat) in the N-th frame and the N + M-th frame is the first and second in the N-th frame and the N + M-th frame The sub scan signals SS1 and SS2 are opposite to the order in which they have a high level value.

Specifically, when the order in which the first and second sub-scan signals SS1 and SS2 have high level values is reversed in the Nth frame and the N + Mth frame, the zero voltage Vzero. And the order of the data current Idat is the same in the Nth frame and the N + Mth frame. On the other hand, when the order in which the first and second sub-scan signals SS1 and SS2 have high level values is the same in the Nth frame and the N + Mth frame, the zero voltage Vzero and the The order of the data current Idat is reversed in the Nth frame and the N + Mth frame.

Next, how the display device illustrated in FIGS. 1 and 5 is driven will be described with reference to the waveform diagrams illustrated in FIG. 6.

First, the source voltage VDS has a low level, the first sub scan signal SS1 has a high level, the second sub scan signal SS2 has a low level, and the data signal DS Has a zero voltage Vzero, the first and second switching transistors SW1 and SW2 are turned on by the first sub scan signal SS1. As a result, 0 V is applied to all of the gate terminal, the source terminal, and the drain terminal of the first driving transistor T1. That is, the first driving capacitor Cst2 stores a voltage of 0 V, and the channel of the first driving transistor T1 is in an off state.

Subsequently, the source voltage VDS has a low level, the first sub scan signal SS1 has a low level, the second sub scan signal SS2 has a high level, and the data signal DS ) Has the data current Idat, OV is applied to both the gate terminal and the source terminal of the second driving transistor T2. In addition, the data current Idat induces a current to flow from the drain terminal of the second driving transistor T2 to the data line DL, whereby a negative terminal is applied to the drain terminal of the second driving transistor T2. The voltage of, for example -6V is formed. That is, since OV and -6V are applied to both ends of the second driving capacitor Cst2, the second driving capacitor Cst2 stores a voltage of 6V. Therefore, the channel of is turned on.

Thereafter, when the source voltage VDS has a high level, the first sub scan signal SS1 has a low level, and the second sub scan signal SS2 has a low level, the source power source. Supplies a source current to the organic light emitting element 410 through the second driving transistor T2.

In detail, when the source voltage VDS is 15V, 15V is applied to the drain terminal of the second driving transistor T2. As a result, 15V is applied to the gate terminal of the second driving transistor T2. 21V is applied by 6V stored in the second driving capacitor Cst2. That is, the second driving transistor T2 is kept in an on state to serve as a current source of the organic light emitting element 410.

Further, since the drain terminal of the first driving transistor T1 is electrically connected to the drain terminal of the second driving transistor T2 through the anode of the organic light emitting diode, the second driving transistor T2 15V is applied in the same way as the drain terminal. However, since the gate terminal of the first driving transistor T1 is continuously maintained at 0 V, the gate terminal of the first driving transistor T1 is viewed based on the drain terminal of the first driving transistor T1. It can be seen that -15V is applied. That is, while the first driving transistor T1 is kept off, the internal characteristics are restored by the negative voltage applied to the gate terminal.

As a result, during the N frame, the second driving transistor T2 serves as a current source of the organic light emitting element 410, and the first driving transistor T1 recovers internal characteristics by a negative voltage applied to the gate terminal. do.

Thereafter, during the N + M frame, the first driving transistor T1 acts as a current source of the organic light emitting element 410, and the second driving transistor T2 is applied by a negative voltage applied to the gate terminal. Internal characteristics are restored.

According to the present invention, while the first current control unit is operated in the first light emitting mode to control the light emission of the organic light emitting device, the second current control unit to recover the second internal characteristics to restore the deteriorated internal characteristics in the second light emitting mode Mode, and while the second current controller is operated in the second light emitting mode to control the light emission of the organic light emitting element, the first current controller enters the first recovery mode to restore the deteriorated internal characteristics in the first light emitting mode. It works.

As a result, the threshold voltage of the first driving transistor of the first current control unit and the second driving transistor of the second current control unit can be suppressed from being deteriorated due to deterioration, thereby stably controlling the light emission of the organic light emitting element.

Accordingly, the first and second current controllers can stably control the light emission of the organic light emitting diode, thereby further improving the display quality of the display device.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (26)

A scan wiring having a first sub scan wiring and a second sub scan wiring formed adjacent to each other in a first direction; A data line formed in a second direction intersecting the first direction; An organic light emitting device for generating light by receiving a source current from a source power source; A first current electrically connected to the first sub scan line, the data line, and the organic light emitting diode, and operated in a first light emitting mode during a unit section to control an amount of the source current supplied to the organic light emitting diode; Control unit; And A second recovery mode electrically connected to the second sub scan line and the data line, electrically connected to the organic light emitting device in parallel with the first current control unit, and to restore the deteriorated internal characteristics; And a second current controller operated by During the next unit section after the unit section, the first current controller is operated in a first recovery mode to restore internal characteristics degraded by the first light emitting mode, and the second current controller is supplied to the organic light emitting device. Operating in a second light emitting mode to control the amount of the source current being The unit section is at least one frame, The first current controller includes a first driving transistor for operating in the first light emitting mode and the first recovery mode, The second current controller includes a second driving transistor for operating in the second light emitting mode and the second recovery mode, When a positive data voltage is applied to the gate terminal of the first driving transistor, the first current controller is operated in the first light emitting mode, and when a negative recovery voltage is applied to the gate terminal of the first driving transistor. The first current controller is operated in the first recovery mode. When a positive data voltage is applied to the gate terminal of the second driving transistor, the second current controller is operated in the second light emitting mode, and when a negative recovery voltage is applied to the gate terminal of the second driving transistor. The second current controller is operated in the second recovery mode, The first and second current controllers are controlled by a voltage writing method. delete delete delete The display panel of claim 1, wherein the first and second driving transistors are thin film transistors made of amorphous silicon (a-Si). delete delete The method of claim 1, wherein the first current control unit A first switching transistor having a gate terminal electrically connected to the first sub scan wiring, a source terminal electrically connected to the data wiring, and a drain terminal electrically connected to the gate terminal of the first driving transistor; And A first driving capacitor for maintaining a voltage applied to a gate terminal of the first driving transistor; The second current controller A second switching transistor having a gate terminal electrically connected to the second sub scan wiring, a source terminal electrically connected to the data wiring, and a drain terminal electrically connected to the gate terminal of the second driving transistor; And And a second driving capacitor which maintains a voltage applied to the gate terminal of the second driving transistor. A scan wiring having a first sub scan wiring and a second sub scan wiring formed adjacent to each other in a first direction; A data line formed in a second direction intersecting the first direction; An organic light emitting device for generating light by receiving a source current from a source power source; A first current electrically connected to the first sub scan line, the data line, and the organic light emitting diode, and operated in a first light emitting mode during a unit section to control an amount of the source current supplied to the organic light emitting diode; Control unit; And A second recovery mode electrically connected to the second sub scan line and the data line, electrically connected to the organic light emitting device in parallel with the first current control unit, and to restore the deteriorated internal characteristics; And a second current controller operated by During the next unit section after the unit section, the first current controller is operated in a first recovery mode to restore internal characteristics degraded by the first light emitting mode, and the second current controller is supplied to the organic light emitting device. Operating in a second light emitting mode to control the amount of the source current being The unit section is at least one frame, The first current controller includes a first driving transistor for operating in the first light emitting mode and the first recovery mode, The second current controller includes a second driving transistor for operating in the second light emitting mode and the second recovery mode, When a positive data voltage is applied to the gate terminal of the first driving transistor, the first current controller is operated in the first light emitting mode, and when a negative recovery voltage is applied to the gate terminal of the first driving transistor. The first current controller is operated in the first recovery mode. When a positive data voltage is applied to the gate terminal of the second driving transistor, the second current controller is operated in the second light emitting mode, and when a negative recovery voltage is applied to the gate terminal of the second driving transistor. The second current controller is operated in the second recovery mode, And the first and second current controllers are controlled by a current writing method. The method of claim 9, wherein the first current control unit A first switching transistor having a gate terminal electrically connected to the first sub scan wiring, and a source terminal and a drain terminal electrically connected to the gate terminal and the source terminal of the first driving transistor; A first driving capacitor electrically connected to the gate terminal and the drain terminal of the first driving transistor and maintaining a voltage applied to the gate terminal of the first driving transistor; And And a second switching transistor having a gate terminal electrically connected to the first sub scan line, a source terminal electrically connected to the data line, and a drain terminal electrically connected to a drain terminal of the first driving transistor. and, The second current controller A third switching transistor having a gate terminal electrically connected to the second sub scan wiring, and a source terminal and a drain terminal electrically connected to the gate terminal and the source terminal of the second driving transistor; A second driving capacitor electrically connected to the gate terminal and the drain terminal of the second driving transistor and maintaining a voltage applied to the gate terminal of the second driving transistor; And And a fourth switching transistor having a gate terminal electrically connected to the second sub scan wiring, a source terminal electrically connected to the data wiring, and a drain terminal electrically connected to the drain terminal of the second driving transistor. Display panel characterized in that. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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