KR101348425B1 - Device for timing calibration of automatic test equipment - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing correction apparatus for automatic test equipment, and more particularly, to a timing correction apparatus for automatic test equipment (ATE), wherein the sink generates a period with a reference clock for calibration. A test header having a board and a main board including a pattern generator (PG), a timing & formatting (TGFC), and a pin electronic (PE); And a timing correction board capable of communicating in real time through the test header and the interface, and configured to configure a virtual test target device (Virtual DUT) for timing correction, and including pin electronics of the test header. Simultaneously measure driver and comparator signals for all channels between virtual devices under test, and apply delays to reference channels that reference the last signal as a reference to all channels. It is characterized by the configuration that the timing correction is performed.
According to the timing correction apparatus of the automatic test equipment proposed by the present invention, by configuring a timing correction board that implements a virtual test target device (Virtual DUT) with FPGA hardware, the pin electronics (PE) of the semiconductor device test equipment (ATE) It is possible to perform timing calibration by measuring driver and comparator signals automatically to the final output terminal (DUT) through the) and through this, SOC (System on Chip) Can reduce the time and manpower required for factory calibration in the early stages for accurate and fast operation of semiconductor device test equipment (ATE) to make good results in manufacturing.

Description

Timing compensator for automatic test equipment {DEVICE FOR TIMING CALIBRATION OF AUTOMATIC TEST EQUIPMENT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing calibration apparatus for automatic test equipment, and more specifically, to a device under test (DUT) which is a final output terminal through pin electronics (PE) of a semiconductor device test equipment (ATE). The present invention relates to a timing correction device for automatic test equipment that automatically measures and calibrate driver and comparator signals for all channels.

In general, an automated test apparatus (ATE) refers to an automated system for testing devices such as computer-driven semiconductors, electronic circuits, and printed circuit board assemblies. The test process for determining the pass / fail of the semiconductor chip manufactured during the semiconductor manufacturing process is a process for inspecting the electrical characteristics of the manufactured chip, using two steps using an automatic test equipment. Carry out an inspection process. The first method examines the electrical characteristics of the fabricated chip and performs the functional operation test of the chip. The operation test during the two-step test process applies a suitable test pattern for the target chip in the pattern generator to the device under test (DUT) through a pin driver, and applies a comparator to the signal output from the DUT. The chip is then used to make final determinations on whether the chip is defective or not compared to the expected data. Automated test devices operated in this way consist of a pattern generator, a pin driver, a comparator and a power supply as the main components, forming a test header or system.

1 is a view showing the overall configuration of a conventional semiconductor device test system. As shown in FIG. 1, the semiconductor device test system conveys a test header 1 for testing the semiconductor device 4 (Device Under Test) and a predetermined quantity of semiconductor devices 4 when the overall configuration is largely divided. And a tester 3 to classify and load the semiconductor devices 4 according to the test results, and are interposed between the test header 1 and the handler 3. It may be configured to include a high-fix (HIFIX) board (2) for establishing an electrical connection between the test header (1). That is, the semiconductor device 4 and the high seated in the insert on the test tray in a state where the high fix board 2 and the test site of the handler 3 where the sockets of the (m × n) matrix are arranged match with each other. By the sockets on the fix board 2 contacting each other, (m × n) semiconductor chips can be tested simultaneously.

2 is a view schematically showing a conventional semiconductor test header device. As shown in FIG. 2, the test header 20 includes a single test header substrate and various circuit elements mounted on one or both surfaces thereof. The test header 20 measures and adjusts a parameter including a programmable power supply (PV21) for supplying power to the semiconductor device 30 and a voltage and a current applied to the semiconductor device 30. Parametric Measurement Unit (PMU) 22, an Algorithmic Pattern Generater (ALPG 23) that generates a predetermined test pattern signal for testing the semiconductor device 30, and a pattern signal and a timing signal input from the ALPG 23 The test pattern read by the semiconductor device 30 and the driver 25 for writing the TGFC 24 (Timing & Formatting) and the test pattern signal output from the TGFC 24 to the semiconductor device 30 are combined. And a pin electronic (PE) 27 including a comparator 26 for comparing the read signal with a reference signal corresponding to the characteristics of the semiconductor and outputting the comparison value. In addition, an interface unit (not shown) for an interface may be included between the test control device 10 and the test header 20, and whether or not to fail the signal output from the comparator 26 of the PE 27. And a digital comparator (not shown) for determining.

Specifically, the PE 27 is a circuit for applying a current and a voltage according to a test pattern directly to a semiconductor provided in the semiconductor device 30, and forms one I / O channel. When the test pattern signal is output by the TGFC 24, the driver 25 of the PE 27 writes the test pattern signal to the test target semiconductor provided in the semiconductor device 30, and the recorded pattern signal is a semiconductor. Read by the device 30 and output to the comparator 26, the comparator 26 transmits a comparison signal to a digital comparator (not shown) according to the result of comparing the read signal of the test pattern with the reference signal, Determining whether the corresponding read signal is fail (fail) and transmits the result to the test control device 10 via the interface unit.

The pin electronics PE of the conventional semiconductor device test equipment ATE as described above includes a driver for applying a signal to a DUT, which is a final output terminal, and a comparator output in response to the signal. The driver outputs in synchronization with the input rate (Rate), and the comparator compares and judges by the input strobe. However, since signal length and timing deviations due to mechanical operation exist, calibration is performed to match measurement signals at the DUT stage. This is necessary to perform factory calibration at an early stage for accurate and fast operation of semiconductor device test equipment (ATE) to make good quality judgment in manufacturing SOC (System on Chip). By calibrating one channel as a reference and measuring the other channels with an oscilloscope, a significant amount of time and manpower was wasted.

The present invention is proposed to solve the above problems of the conventionally proposed methods, by configuring a timing correction board for implementing a virtual device under test (Virtual DUT) with FPGA hardware, semiconductor device test equipment (ATE) It is possible to perform timing calibration by automatically measuring driver and comparator signals for all channels to DUT (Device under test) which is the final output terminal through pin electronics of Reduced time and manpower for factory calibration required in the early stages for accurate and fast operation of semiconductor device test equipment (ATE) for good quality judgment in the manufacture of system on chips (SOC) It is an object of the present invention to provide a timing correction device for automatic test equipment.

Timing correction apparatus of the automatic test equipment according to a feature of the present invention for achieving the above object,

As a timing correction device for automatic test equipment (ATE),

A sink board that generates a Rate with a Reference Clock for Calibration, and includes a Pattern Generator (PG), Timing & Formatting (TGFC), and Pin Electronics (PE). A test header having a main board; And

It is possible to communicate in real time via the test header and the interface (Realtime), and includes a timing correction board for configuring a virtual test target device (Virtual DUT) for timing correction,

The driver and the comparator signal are simultaneously measured for all the channels between the pin electronics of the test header and the virtual device under test, and the delay is matched with a reference channel that refers to the last signal as a reference. It is a feature of the configuration that the timing correction of all channels is performed by applying a delay).

Preferably, the virtual device under test (Virtual DUT),

It can be configured as hardware of a field programmable gate array controller (FPGA).

Preferably, the interface,

A serial peripheral interface bus (SPI bus) capable of real time communication between the test header and the timing correction board may be applied.

Preferably, the interface,

Any one of a serial peripheral interface (SPI), a universal serial bus (USB), a local area network (LAN), and a CAN bus (Controller Area Network) capable of real-time communication between the test header and the timing correction board One can be applied.

Preferably, the correction reference clock,

25 MHz may be used.

More preferably, the pin electronics,

The driver's output data is made 25MHz equal to the rate, and then increased to 500㎰ (Altera Part: EP4SE360F35C2N CHIP Resolution) used as a virtual DUT resolution to determine the position of the edge and the entire channel. Data correction may be performed to match skew of all data based on the data of the last channel.

More preferably, the pin electronics,

From the timing correction board, make it the same clock as the reference clock and send it as a comparator.Increase the strobe to 500Hz (Altera Part: EP4SE360F35C2N CHIP Resolution using virtual DUT) resolution to locate the strobe. Compensation can be performed to match the skew of all strobes based on later strobes.

According to the timing correction apparatus of the automatic test equipment proposed by the present invention, by configuring a timing correction board that implements a virtual test target device (Virtual DUT) with FPGA hardware, the pin electronics (PE) of the semiconductor device test equipment (ATE) It is possible to perform timing calibration by measuring driver and comparator signals automatically to the final output terminal (DUT) through the) and through this, SOC (System on Chip) The time and labor required for factory calibration in the early stages for accurate and fast operation of semiconductor device test equipment (ATE) to make a good product in manufacturing can be reduced.

1 is a diagram showing the overall configuration of a conventional semiconductor device test system.
2 schematically illustrates a conventional semiconductor test header device.
3 is a view showing the overall configuration of the timing correction apparatus of the automatic test equipment according to an embodiment of the present invention.
4 is a diagram illustrating an internal configuration of a main board of a timing correction device of automatic test equipment according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating data correction in a timing correction device of automatic test equipment according to an embodiment of the present invention. FIG.
FIG. 6 is a diagram illustrating comparator correction in a timing correction device of automatic test equipment according to an embodiment of the present invention. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order that those skilled in the art can easily carry out the present invention. In the following detailed description of the preferred embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In the drawings, like reference numerals are used throughout the drawings.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . In addition, the term 'comprising' of an element means that the element may further include other elements, not to exclude other elements unless specifically stated otherwise.

3 is a view showing the overall configuration of the timing correction apparatus of the automatic test equipment according to an embodiment of the present invention, Figure 4 is the inside of the main board of the timing correction apparatus of the automatic test equipment according to an embodiment of the present invention It is a figure which shows a structure. As shown in FIG. 3, the apparatus for correcting timing of automatic test equipment according to an embodiment of the present invention may include a test header 100 and a timing correction board 200.

The test header 100 may include a sink board 110 that generates a rate as a reference clock for calibration, a pattern generator (PG) 121, and a TGFC (Timing & Formatting). And a main board 120 including a pin electronic (PE) 123. The test header 100 simultaneously measures the driver and the comparator signal for all channels between the pin electronics 123 and the virtual device under test 201 to be described later, and refers to the last signal as a reference. A delay is applied to the reference channel so that timing correction of all channels is performed. Here, the pattern generator 121 serves to generate a predetermined test pattern signal, and the TGFC 122 combines and outputs a pattern signal and a timing signal input from the pattern generator 121, and pin electronics ( 123 is composed of a driver 124 and a comparator 125, as shown in Figure 4, the driver 124 serves to record the test pattern signal output from the TGFC 122 to the device under test, the comparator Reference numeral 125 is a configuration for performing a unique function of comparing the read signal of the test pattern read by the device under test with a reference signal corresponding to the characteristic of the semiconductor and outputting the comparison value. The pin electronics 123 makes the output data of the driver 124 at 25 MHz, such as a rate, and then increases it to 500 ㎰ (Altera Part: EP4SE360F35C2N CHIP Resolution) resolution using a virtual DUT resolution. ) And the data correction to adjust the skew of all the data based on the data of the last channel out of all the channels. In addition, the pin electronics 123 are made from the timing correction board 200 to the same clock as the reference clock, and then sent to the comparator 124. Altera Part using the strobe as a 500 ㎰ virtual DUT: EP4SE360F35C2N CHIP Resolution The resolution can be increased to determine the strobe's position and to perform a compensating correction that allows all strobes to be skewed relative to the last strobe. The 500 kHz resolution is a virtual DUT, that is, a resolution of an FPGA (Part: EP4SE360F35C2N) CHIP, and can be 500 같이 as in the present invention depending on the resolution of the chip used, and 78.168 ㎰ (XC6VLX365T-2FFG1759C) may be used. The test header 100 may be connected to the engineer workstation's personal computer (PC) via Ethernet, and the personal computer (PC) may function as a test control device used by the engineer for semiconductor testing. have.

The timing correction board 200 may communicate with the test header 100 in real time through an interface, and configure a virtual test target device (Virtual DUT) 201 for timing correction. The virtual test target device (Virtual DUT) 201 of the timing correction board 200 may be configured as hardware of a field programmable gate array controller (FPGA). That is, the virtual device under test 201 can be easily implemented because the gate can be configured as desired by the user in an FPGA configuration. In addition, the interface may be a serial peripheral interface bus (SPI bus) that can communicate in real time between the test header 100 and the timing correction board 200. The interface also features a universal serial bus (USB), a local area network (LAN), and a CAN, in addition to a serial peripheral interface (SPI) that enables real-time communication between the test header 100 and the timing correction board 200. Any one of a bus (Controller Area Network) may be applied.

Timing calibration in the timing correction apparatus of the automatic test equipment according to the embodiment of the present invention as described above is virtually implemented in an FPGA hardware configuration on the timing correction board 200 of the final output device under test (DUT) stage. Create the device under test 201 and simultaneously drive and comparator all the channels, setting the last signal as the reference as the reference value, and using the phases of the FPGA I / O. By changing the skew to Step by step, a delay is applied to the reference channel to perform timing correction. Such timing correction is possible because the test header 100 and the virtual test target device 201 communicate in real time through an interface (SPI, USB, LAN, CAN, etc.).

FIG. 5 is a diagram illustrating data correction in a timing correction device of automatic test equipment according to an embodiment of the present invention. That is, FIG. 5 illustrates a configuration and timing for data correction between the driver 124 of the pin electronics 123 and the virtual test target device 201 of the timing correction board 200, and is viewed from the timing correction board 200. Indicates a perspective. First, a cycle is generated by a reference clock for calibration in the sink board 110, and output data (test pattern) is output from the driver 124 of the pin electronics 123 of the main board 120. Make the data equal to the period, and then increase the resolution of the edge of the FPGA of the timing correction board 200, that is, the virtual device under test 201. Subsequently, data correction is performed by adjusting the skew of all data based on the data of the last channel among all the channels, and the difference is applied to the TGFC 122.

FIG. 6 is a diagram illustrating comparator correction in a timing correction device of automatic test equipment according to an embodiment of the present invention. That is, FIG. 6 illustrates a configuration and timing for compensator correction between the comparator 125 of the pin electronics 123 and the virtual test target device 123 of the timing correction board 200, and is viewed from the main board 120. Indicates. First, a cycle is made from the sink board 110 to a reference clock for calibration, and a clock such as a reference is generated from the timing correction board 200 and then sent to the comparator 125 of the main board 120. The strobe is increased to a 500 Hz (Altera Part with EPD: EP4SE360F35C2N CHIP Resolution) resolution to locate the strobe. The comparator correction is then performed by matching the skew of all strobes with respect to the last strobe, and the difference is applied to the TGFC 122.

The present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics of the invention.

100: test header 110: sink board
120: main board 121: pattern generator (PG)
122: TGFC 123: pin electronics (PE)
124: driver 125: comparator
200: timing correction board 201: virtual test target device

Claims (7)

As a timing correction device for automatic test equipment (ATE),
A sink board 110 that generates a rate with a reference clock for calibration, and a pattern generator (PG) 121, a timing & formatting (TGFC) 122, and pin electronics. A test header (100) having a main board (120) comprising a Pin Electronic (PE) 123; And
It is possible to communicate in real time (Realtime) via the interface with the test header 100, and includes a timing correction board (200) constituting a virtual test target device (Virtual DUT) 201 for timing correction ,
The driver and the comparator signal are simultaneously measured for all the channels between the pin electronics 123 of the test header 100 and the virtual device under test 201, and the reference is based on the last signal as a reference. Apply a delay to the reference channel so that timing correction of all channels is performed.
As the correction reference clock, 25 MHz is used,
The pin electronics 123,
The output data of the driver 124 is made to be 25 MHz, such as a rate, and then increased to 500 kHz (Altera Part used as a virtual DUT: EP4SE360F35C2N CHIP Resolution) resolution to determine the position of the edge. And performing data correction to adjust skew of all data on the basis of data of the last channel among all the channels.
The method of claim 1, wherein the virtual device under test (Virtual DUT) 201,
An apparatus for correcting timing of automatic test equipment, comprising: hardware of a field programmable gate array controller (FPGA).
The method of claim 1, wherein the interface,
Serial Peripheral Interface Bus (SPI bus) that is capable of real-time communication between the test header (100) and the timing correction board (200) is applied, timing correction apparatus of automatic test equipment.
The method of claim 1, wherein the interface,
Serial Peripheral Interface (SPI), Universal Serial Bus (USB), Local Area Network (LAN), and CAN bus (CPI) capable of real time communication between the test header 100 and the timing correction board 200. Any one of a controller area network) is applied.
delete delete The method of claim 1, wherein the pin electronics 123,
The timing correction board 200 is made into the same clock as the reference clock and sent to the comparator 124, and the strobe is increased by changing the strobe to 500 Hz (Altera Part: EP4SE360F35C2N CHIP Resolution) using a virtual DUT. A device for correcting timing of automatic test equipment, characterized in that the position is determined and a compensating is performed to match the skew of all strobes based on the last strobe.

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