KR101343497B1 - Method for fabricating lcd - Google Patents

Abstract

The present invention discloses a method for manufacturing a liquid crystal display device which can improve the side profile of the first gate line and the second gate line at the boundary portion of the circuit portion n-channel TFT region and the circuit portion p-channel TFT region. The disclosed method includes providing a substrate in which a pixel portion divided into a TFT region and a storage region and a circuit portion divided into a p-channel TFT region and an n-channel TFT region are defined; Forming a second active layer and a third active layer in an n-channel TFT region and a p-channel TFT region of the circuit portion of the substrate, respectively; Forming a gate insulating film, a first metal film, and a second photoresist film pattern on a substrate having the second and third active layers; By selectively patterning the first metal film using the second photoresist pattern, the first gate line and the first gate line arranged in one direction over the entire n-channel region and p-channel TFT region of the circuit part and a predetermined distance from the first gate line. Forming a second gate line spaced apart from each other, and forming a circuit portion first gate electrode connected to the first gate line in a p-channel TFT region of the circuit portion; After removing the second photoresist layer pattern, p + doping is performed on a substrate having the first gate electrode and the first gate line of the circuit part, thereby forming a circuit part first source / drain region on the third active layer under both sides of the first gate electrode of the circuit part. Forming; Forming a third photoresist pattern on the substrate having the first gate electrode, the first gate line, and the second gate line; Selectively patterning the first metal layer using the third photoresist pattern to form a pixel portion gate electrode and a common line in the pixel portion, and a circuit portion connected to the second gate line in an n-channel TFT region of the circuit portion Forming a second gate electrode; Performing a n + doping on a substrate having the circuit portion second gate electrode to form a circuit portion second source / drain region in the second active layer under both sides of the circuit portion second gate electrode; Forming a protective film on the substrate having the circuit portion second gate electrode; And after forming a second metal film on the passivation layer, selectively patterning the second metal film to form a circuit part second source / drain electrode and a first source / drain electrode in the n-channel TFT region and the p-channel TFT region, respectively. It includes a step.

Description

Manufacturing method of liquid crystal display device {METHOD FOR FABRICATING LCD}

1A to 1F are cross-sectional views of processes for explaining a method of manufacturing a liquid crystal display device according to the related art.

FIG. 2 is a partial plan view of the substrate showing the circuit portion of FIG. 1D; FIG.

3 is a partial plan view of the substrate showing the circuit portion of FIG. 1E;

4A to 4G are cross-sectional views of processes for explaining a method of manufacturing a liquid crystal display device according to the present invention.

Fig. 5 is a partial plan view of the substrate showing the circuit portion of Fig. 4D.

FIG. 6 is a partial plan view illustrating a substrate in which the second photoresist pattern is removed in FIG. 5; FIG. 7 is a partial plan view of the substrate showing the circuit portion of FIG. 4E;

FIG. 8 is a partial plan view illustrating a substrate in which the third photoresist pattern is removed in FIG. 7; FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a liquid crystal display device having gate lines arranged long over a circuit portion n-channel TFT region and a circuit portion p-channel TFT region.

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), which is the flagship product of Flat Panel Display (FPD), is not only capable of satisfying these conditions of display but also has mass productivity. Therefore, And has become a core parts industry that can gradually replace conventional cathode ray tubes (CRTs).

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form to adjust a light transmittance of the liquid crystal cells. to be.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

The amorphous silicon thin film transistor technology was established in 1979 by LeComber et al. In England, and was commercialized as a 3 "liquid crystal portable television in 1986. Recently, a large area thin film transistor liquid crystal display device of 50" or more has been developed. In particular, the amorphous silicon thin film transistor has been actively used because it is possible to use a low-cost insulating substrate to enable a low temperature process.

However, the electrical mobility (˜1 cm ² / Vsec) of the amorphous silicon thin film transistor is limited to use in peripheral circuits requiring high-speed operation of 1 MHz or more. As a result, studies are being actively conducted to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate by using a polycrystalline silicon (poly-Si) thin film transistor having a larger field effect mobility than the amorphous silicon thin film transistor. It's going on.

Polycrystalline silicon thin film transistor technology has been applied to small modules such as camcorders since liquid crystal color television was developed in 1982, and has the advantage of being able to manufacture driving circuits directly on the board because of its low sensitivity and high field effect mobility. .

Increasing the mobility may improve the operating frequency of the driving circuit unit that determines the number of driving pixels, thereby facilitating high definition of the display device. In addition, the distortion of the transmission signal is reduced due to the reduction of the charging time of the signal voltage of the pixel portion, thereby improving the picture quality.

In addition, the polycrystalline silicon thin film transistor can be driven at less than 10V compared to the amorphous silicon thin film transistor having a high driving voltage (~ 25V) has the advantage that the power consumption can be reduced.

Hereinafter, a method of manufacturing a liquid crystal display device will be described in detail with reference to FIGS. 1A to 1F.

As shown in FIG. 1A, an insulating substrate 101 is provided. The insulating substrate 101 has a pixel portion divided into an n-channel (or p-channel) TFT region and a storage region, and a circuit portion divided into an n-channel TFT region and a p-channel TFT region, respectively. That is, both the n-channel TFT and the p-channel TFT can be formed in the pixel portion, and the n-channel TFT and the p-channel TFT are both formed in the circuit portion to form a CMOS. Subsequently, a buffer layer 103, a polysilicon film 105, an insulating film 107, and a storage electrode film 109 are sequentially formed on the insulating substrate 101. The insulating layer 107 may be a gate insulating layer. The insulating film 107 may be omitted. The storage electrode film 109 may be an n + silicon layer or a metal film.

As shown in FIG. 1B, the first photoresist layer pattern 130 is formed on a substrate having the storage electrode layer using a slit or halftone mask (not shown). In the first photoresist pattern 130, the n-channel TFT region and the p-channel TFT region of the circuit portion, and the n-channel TFT region of the pixel portion are formed relatively thinner than the storage region of the pixel portion. By selectively primary etching the storage electrode film, the insulating film, and the polysilicon film by using the first photoresist film pattern 130, the pixel pattern 110P1 covering the pixel portion, the n-channel TFT region and the p-channel TFT region of the circuit portion are formed. First and second circuit patterns 110P2 and 110P3 respectively covering are formed. The storage electrode film, the insulating film, and the polysilicon film may be simultaneously etched.

As shown in FIG. 1C, the first photoresist pattern is ashed. The first photoresist pattern 130P remaining after the ashing is removed from the n-channel TFT region and the p-channel TFT region of the relatively thin circuit portion, and the TFT region of the pixel portion is removed, and selectively remains only in the storage region of the pixel portion. do. Next, the storage electrode layer and the insulating layer are selectively removed from the pixel pattern 110P1 and the first and second circuit patterns 110P2 and 110P3 exposed by the remaining first photoresist layer pattern 130P. As a result, the storage electrode 109P formed of the remaining storage electrode film is formed in the storage region of the pixel portion. At this time, each of the first, second and third active layers 105P1 and 105P2 formed of a polysilicon film is formed in the n-channel TFT region of the pixel portion, the n-channel TFT region of the circuit portion, and the p-channel TFT region of the circuit portion. 105P3) is formed.

As shown in FIG. 1D, the remaining first photoresist pattern is removed. The gate insulating layer 111, the first metal layer 113, and the second photoresist layer pattern 133 are sequentially formed on the substrate having the first, second, and third active layers 105P1, 105P2, and 105P3.

On the other hand, the second photoresist pattern 133 is patterned to selectively cover the entire portion of the pixel portion, the entire n-channel TFT region of the circuit portion, and a portion where the p-channel gate electrode of the p-channel TFT region is to be formed. That is, the second photoresist pattern 133 is patterned to selectively expose only a portion where the source / drain region is to be formed in the circuit portion p-channel TFT region.

Subsequently, the first metal layer is etched using the second photoresist layer pattern 133 to form a circuit part first gate electrode 113P1 in the p-channel TFT region of the circuit part. At this time, the entire pixel portion and the circuit portion n-channel TFT region are masked by the second photoresist pattern 133, so that the first metal film is left without being patterned.

2 is a partial plan view of the substrate showing the circuit portion of FIG. 1D. The cut surface of the line II of FIG. 2 corresponds to the circuit part of FIG. 1D. Reference numeral 113G1 corresponds to a first gate line connected to the circuit unit first gate electrode 113P1 in the circuit unit p-channel TFT region. At this time, the first gate line 113G1 is not patterned in the n-channel TFT region because the n-channel TFT region is covered by the second photosensitive film pattern 133.

Reference numeral 113G2 corresponds to the second gate line in the circuit portion p-channel TFT region, and is not patterned in the n-channel TFT region because the n-channel TFT region is covered by the second photosensitive film pattern 133. The first gate line 113G1 and the second gate line 113G2 are formed to be arranged at a predetermined interval.

As shown in FIG. 1E, the second photoresist pattern is removed. Subsequently, p + doping is performed on the substrate having the first gate electrode 113P1. As a result, a circuit portion first source / drain region 105P3S (105P3D) is formed in the third active layer 105P3. Next, a third photoresist pattern 135 is formed on the entire surface of the substrate having the first gate electrode 113P1. The third photoresist layer pattern 135 includes a portion where each pixel portion gate electrode and a common line are to be formed in the pixel portion, a portion in which a circuit portion second gate electrode is to be formed in an n-channel TFT region of the circuit portion, and the p-channel TFT. Patterned to cover the entire area.

Subsequently, the remaining first metal layer is etched using the third photoresist pattern to form a pixel portion gate electrode 113P2 and a common line 113P3 in the pixel portion, and at the same time, in the n-channel TFT region of the circuit portion. The circuit portion second gate electrode 113P4 is formed. As a result, the pixel portion gate electrode 113P2, the common line 113P3, and the circuit portion second gate electrode 113P4 may be excessively etched laterally.

3 is a partial plan view of the substrate showing the circuit portion of FIG. 1E. The cut surface of the II-II 'line | wire of FIG. 3 corresponds to the circuit part of FIG. 1E. In FIG. 3, reference numeral 113G2 corresponds to a second gate line connected to the second gate electrode 113P4 of the circuit unit. In this case, the first gate line connected to the circuit portion first gate electrode 113P1 and the circuit portion first gate electrode 113P1 corresponding to the circuit portion p-channel TFT region is covered by the third photosensitive film pattern 135. Reference numeral 113G1 denotes a first gate line corresponding to the n-channel TFT region of the circuit portion. Reference numeral 113G2 denotes a second gate line in the circuit portion n-channel TFT region.

Thereafter, as shown in FIG. 1F, the third photoresist pattern is removed. Subsequently, n + ion doping is performed on the substrate having the third photoresist pattern. As a result, the pixel portion source region 105P1S and the pixel portion drain region 105P1D are formed in the n-channel TFT region of the pixel portion, and the circuit portion second source region 105P2S and the circuit portion second are formed in the n-channel TFT region of the circuit portion. Drain region 105P2D is formed. That is, the pixel portion source region 105P1S and the pixel portion drain region 105P1D are formed in the first active layer 105P1 under both sides of the pixel portion gate electrode 113P2. The circuit portion second source region 105P2S and the circuit portion second drain region 105P2D are formed in the second active layer 105P2 under both sides of the circuit portion second gate electrode 113P4.

Next, the LED doping (n−) is applied to the entire surface of the substrate using the pixel portion gate electrode 113P2 and the circuit portion second gate electrode 113P4 as a mask. As a result, a first LED region 105P1L is formed in the n-channel TFT region of the pixel portion, and a second LED region 105P2L is formed in the n-channel TFT region of the circuit portion. The first and second LED regions 105P1L and 105P2L are formed as wet CD biases, and may be obtained by doping the entire substrate without a separate mask.

In the above-described manufacturing method of the liquid crystal display device in the prior art, the circuit portion corresponding to the p-channel TFT region of the pixel portion by covering the n-channel TFT region of the pixel portion and selectively patterning a metal film on the p-channel TFT region of the pixel portion, the first gate electrode and the circuit portion A first gate line connected to the first gate electrode and a second gate line disposed at regular intervals from the first gate line are formed. Subsequently, a second gate line connected to the circuit part second gate electrode and the circuit part second gate electrode corresponding to the n-channel TFT region of the pixel portion by covering the p-channel TFT region of the pixel portion and selectively patterning a metal film on the n-channel TFT region of the pixel portion. And first gate lines disposed at predetermined intervals from the second gate line.

However, in the related art, when the p-channel gate electrode, the first gate line connected to the p-channel gate electrode, the n-channel gate electrode, and the second gate line connected to the n-channel gate electrode are formed, the n-channel TFT region is formed. First, patterning and patterning the p-channel TFT region. Therefore, there is a problem in that the profile of the first gate line and the second gate line corresponding to the boundary between the n-channel TFT region and the p-channel TFT region is poor. That is, there is a problem in that the side profile at the boundary between the first gate line and the second gate line covered by the second photoresist pattern and the third photoresist pattern is poor.

In addition, the side profile of the first gate line and the second gate line is deteriorated at the boundary portion of the n-channel TFT region of the circuit portion and the p-channel TFT region of the circuit portion, so that a space is provided between the first gate line and the second gate line. Therefore, it is disadvantageous to high integration.

Accordingly, to solve the above problem, an object of the present invention is to manufacture a liquid crystal display device which can improve the side profile of the first gate line and the second gate line at the boundary portion of the circuit portion n-channel TFT region and the circuit portion p-channel TFT region. To provide a way.

In order to achieve the above object, a method of manufacturing a liquid crystal display device according to the present invention includes the steps of providing a substrate in which a pixel portion divided into a TFT region and a storage region and a circuit portion divided into a p-channel TFT region and an n-channel TFT region are defined. ; Forming a second active layer and a third active layer in an n-channel TFT region and a p-channel TFT region of the circuit portion of the substrate, respectively; Forming a gate insulating film, a first metal film, and a second photoresist film pattern on a substrate having the second and third active layers; By selectively patterning the first metal film using the second photoresist pattern, the first gate line and the first gate line arranged in one direction over the entire n-channel region and p-channel TFT region of the circuit part and a predetermined distance from the first gate line. Forming a second gate line spaced apart from each other, and forming a circuit portion first gate electrode connected to the first gate line in a p-channel TFT region of the circuit portion; After removing the second photoresist layer pattern, p + doping is performed on a substrate having the first gate electrode and the first gate line of the circuit part, thereby forming a circuit part first source / drain region on the third active layer under both sides of the first gate electrode of the circuit part. Forming; Forming a third photoresist pattern on the substrate having the first gate electrode, the first gate line, and the second gate line; Selectively patterning the first metal layer using the third photoresist pattern to form a pixel portion gate electrode and a common line in the pixel portion, and a circuit portion connected to the second gate line in an n-channel TFT region of the circuit portion Forming a second gate electrode; Performing a n + doping on a substrate having the circuit portion second gate electrode to form a circuit portion second source / drain region in the second active layer under both sides of the circuit portion second gate electrode; Forming a protective film on the substrate having the circuit portion second gate electrode; And after forming a second metal film on the passivation layer, selectively patterning the second metal film to form a circuit part second source / drain electrode and a first source / drain electrode in the n-channel TFT region and the p-channel TFT region, respectively. It includes a step.

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(Example)

4A to 4G are cross-sectional views illustrating processes of manufacturing a liquid crystal display device according to the present invention. 5 is a partial plan view of a substrate showing the circuit portion of FIG. 4D. A cut plane of the III-III ′ line of FIG. 5 corresponds to the circuit portion of FIG. 4D. FIG. 6 is a partial plan view illustrating a substrate in which the second photosensitive film pattern is removed in FIG. 5. 7 is a partial plan view of the substrate showing the circuit portion of FIG. 4E. A cross section taken along the line IV-IV ′ of FIG. 7 corresponds to the circuit portion of FIG. 4E. FIG. 8 is a partial plan view illustrating a substrate in which the third photoresist pattern is removed in FIG. 7.

Hereinafter, a method of manufacturing a liquid crystal display device according to the present invention will be described with reference to FIGS. 4A to 4G.

As shown in FIG. 4A, an insulating substrate 201 is provided. The insulating substrate 201 defines pixel portions divided into n-channel (or p-channel) TFT regions and storage regions, and circuit portions divided into n-channel TFT regions and p-channel TFT regions, respectively. That is, both the n-channel TFT and the p-channel TFT can be formed in the pixel portion, and the n-channel TFT and the p-channel TFT are both formed in the circuit portion to form a CMOS. The insulating substrate 201 may be an array substrate. The insulating substrate 201 may be a transparent substrate such as glass. A buffer layer 203, a polysilicon film 205, an insulating film 207, and a storage electrode film 209 are sequentially formed on the insulating substrate 201. The insulating layer 207 may be a gate insulating layer. The insulating layer 207 may be a silicon oxide layer SiO 2. The insulating film 207 may be omitted. The storage electrode film 209 may be an n + silicon layer or a metal film.

As shown in FIG. 4B, the first photoresist layer pattern 230 is formed on the substrate 201 having the storage electrode layer 209 using a slit or halftone mask (not shown). In the first photoresist pattern 230, an n-channel TFT region and a p-channel TFT region of the circuit portion, and an n-channel TFT region of the pixel portion are formed relatively thinner than the storage region of the pixel portion. A pixel pattern 210P1 covering the pixel portion by selectively primary etching the storage electrode layer, the insulating layer, and the polysilicon layer using the first photoresist layer pattern 230, and an n-channel TFT region and a p-channel TFT region of the circuit portion First and second circuit patterns 210P2 and 210P3 respectively covering the first and second circuit patterns 210P2 and 210P3 are formed. The storage electrode film, the insulating film, and the polysilicon film may be simultaneously etched. The etching process may be performed in a dry or mixed manner of wet and dry.

As shown in FIG. 4C, the first photoresist pattern is ashed. The first photoresist pattern 230P remaining after the ashing is removed from the n-channel TFT region and the p-channel TFT region of the relatively thin circuit portion and the TFT region of the pixel portion, and is selectively retained only in the storage region of the pixel portion. . Next, the storage electrode layer and the insulating layer are selectively removed from the pixel pattern 210P1 and the first and second circuit patterns 210P2 and 210P3 exposed by the remaining first photoresist layer pattern 230P. As a result, the storage electrode 209P made of the remaining storage electrode film is formed in the storage region of the pixel portion. At this time, the n-channel TFT region of the pixel portion, the n-channel TFT region of the circuit portion, and the p-channel TFT region of the circuit portion are formed of first, second and third active layers 205P1, 205P2, and 205P3 made of a polysilicon film. Are formed respectively.

As shown in FIG. 4D, the remaining first photoresist pattern is removed. A gate insulating film 211, a first metal film 213, and a second photosensitive film pattern 233 are sequentially formed on a substrate having the first, second, and third active layers 205P1, 205P2, and 205P3. Meanwhile, as shown in FIG. 4A, when the insulating film 207 is interposed between the polysilicon film 205 and the storage electrode film 209, the insulating film 207 corresponds to a first gate insulating film, and the gate insulating film 211. ) May correspond to the second gate insulating layer. As described above, when the gate insulating film has a double structure of the first gate insulating film and the second gate insulating film, the total thickness of the gate insulating film having the double structure is the sum of the first gate insulating film and the second gate insulating film. Corresponds to Therefore, the gate insulating film having the double structure according to the present invention is formed to the same thickness as the conventional one by appropriately adjusting the thicknesses of the first gate insulating film and the second gate insulating film.

The second photoresist pattern 233 is patterned to cover the entire pixel portion and the n-channel TFT region and to cover a portion where the gate electrode of the circuit portion p-channel TFT region is to be formed.

Referring to FIG. 5, the shape of the second photoresist layer pattern 233 in the circuit unit will be described in more detail as follows.

The second photoresist pattern 233 covers the entire pixel portion, and as shown in FIG. 5, the first photoresist is elongated in one direction throughout the p-channel TFT region of the circuit portion and the n-channel TFT region of the circuit portion. A gate line region, a second gate line region spaced apart from the first gate line region, and a circuit portion n-channel TFT region connected to the second gate line region; Patterned to further cover the circuit portion p-channel gate electrode region connected to the one gate line region.

Subsequently, the first metal layer is etched using the second photoresist pattern 233. At this time, the entire pixel portion and the circuit portion n-channel TFT region are masked by the second photosensitive film pattern 233, so that the first metal film is left without being patterned. Next, the second photosensitive film pattern is removed. As a result, as shown in FIG. 6, the circuit portion first gate electrode 213P1 and the first gate line 213G1 are formed.

Next, the second photoresist pattern is removed. Then, p + doping is performed on the substrate having the first gate electrode 213P1 and the first gate line 213G1. As a result, circuit portion first source / drain regions 205P3S and 205P3D are formed in the third active layer 205P3 under both sides of the circuit portion first gate electrode 213P1.

Subsequently, as shown in FIG. 4E, a third photoresist pattern 235 is formed on the entire surface of the substrate having the first gate electrode 213P1. The third photoresist pattern 235 includes a portion where each pixel portion gate electrode and a common line are to be formed in the pixel portion, a portion in which a circuit portion second gate electrode is to be formed in an n-channel TFT region of the circuit portion, and the p-channel TFT. Patterned to cover the entire area. Referring to FIG. 7, the shape of the third photoresist layer pattern 235 in the circuit unit will be described in more detail as follows.

As shown in FIG. 7, the third photoresist layer pattern 235 has a first gate line region arranged in one direction and is uniform with the first gate line region throughout the circuit portion p-channel TFT region and the circuit portion n-channel TFT region. A circuit portion n-channel gate electrode covering the second gate line region and the circuit portion p-channel TFT region connected to the first gate line region spaced apart from each other, and connected to the second gate line region in the circuit portion n-channel TFT region. Patterned to further cover the area.

Subsequently, the remaining first metal layer is etched using the third photoresist pattern 235. As a result, a pixel portion gate electrode 213P2 and a common line 213P3 are formed in the pixel portion, and as shown in FIGS. 4E and 7, the circuit portion second gate electrode is formed in the n-channel TFT region of the circuit portion. A second gate line 213G2 connected to the second gate electrode 213P4 and the second gate electrode 213P4 is formed. In this case, the remaining first metal layer etching process may be performed by wet etching. As a result, the pixel portion gate electrode 213P2, the common line 213P3, and the circuit portion second gate electrode 213P4 may be excessively etched laterally.

As shown in FIG. 4F, n + ion doping is performed on the substrate having the second gate electrode 213P4. As a result, a pixel portion source region 205P1S and a pixel portion drain region 205P1D are formed in an n-channel TFT region of the pixel portion, and a circuit portion second source region 205P2S and a circuit portion second are formed in the n-channel TFT region of the circuit portion. Drain region 205P2D is formed. That is, the pixel portion source region 205P1S and the pixel portion drain region 205P1D are formed in the first active layer 205P1 under both sides of the pixel portion gate electrode 213P2. The circuit portion second source region 205P2S and the circuit portion second drain region 205P2D are formed in the second active layer 205P2 under both sides of the circuit portion second gate electrode 213P4.

Thereafter, the third photoresist pattern is removed. Subsequently, the LED doping (n−) is applied to the entire surface of the substrate using the pixel portion gate electrode 213P2 and the circuit portion second gate electrode 213P4 as a mask. As a result, a first LED region 205P1L is formed in the n-channel TFT region of the pixel portion, and a second LED region 205P2L is formed in the n-channel TFT region of the circuit portion. The first and second LED regions 205P1L and 205P2L are formed by wet CD biases, and may be obtained by doping the entire substrate without a separate mask. The third photoresist pattern is removed.

As shown in FIG. 4G, a protective film 221 is formed on a substrate having the first and second LED areas 205P1L and 205P2L. The protective film 221 may use a silicon oxide film (SiO 2) and a silicon nitride film (SiN x) that are sequentially stacked. At this time, the protective film 221, (1) the silicon oxide film is deposited and activated heat treatment, and then the silicon nitride film is deposited and hydrogenated heat treatment, or (2) the silicon oxide film (SiO2) and silicon nitride film (SiNx ) Are formed in sequence, and these films are formed by heat treatment. Here, when the protective film 221 is formed by the method of (2), activation of the silicon oxide film (SiO2) and hydrogenation of the silicon nitride film (SiNx) may be simultaneously performed through one heat treatment.

Subsequently, the passivation layer and the gate insulating layer are etched using a separate mask (not shown) to form first, second, third, fourth, fifth, and sixth contact holes 221H1, 221H2, 221H3, and 221H4. 221H5 and 221H6. The first contact hole 221H1 and the second contact hole 221H2 expose the pixel portion source region 205P1S and the pixel portion drain region 205P1D. The second contact hole 221H2 is patterned to expose not only the pixel portion drain region 205P1D but also a portion of the storage electrode 209P. The third contact hole 221H3 and the fourth contact hole 221H4 expose the circuit portion second source region 205P2S and the circuit portion second drain region 205P2D. The fifth contact hole 221H5 and the sixth contact hole 221H6 expose the circuit portion first source region 205P3S and the circuit portion first drain region 205P3D.

Next, a second metal film is formed on the substrate having the contact holes. The second metal layer is patterned to form a pixel portion source electrode 223S1 and a pixel portion drain electrode 223D1 covering the first contact hole 221H1 and the second contact hole 221H2 in the pixel portion n-channel TFT region. . The circuit part second source covering the third contact hole 221H3 and the fourth contact hole 221H4 in the n-channel TFT region of the circuit part while the pixel part source electrode 223S1 and the pixel part drain electrode 223D1 are formed. The electrode 223S3 and the circuit portion second drain electrode 223D3 are formed. In addition, a circuit portion first source electrode 223S2 and a circuit portion first drain electrode 223S2 are formed in the circuit portion p-channel TFT region to cover the fifth contact hole 221H5 and the sixth contact hole 221H6.

Subsequently, a transparent conductive film is formed on the substrate having the source electrodes 223S1, 223S2, 223S3 and drain electrodes 223D1, 223D2, and 223D3. The transparent conductive film is patterned to form a pixel portion source electrode pattern 225P1 covering the pixel portion source electrode 223S1 and a pixel portion drain electrode pattern 225P2 covering the pixel portion drain electrode 223D1. Here, the pixel portion drain electrode pattern 225P2 is patterned to cover the pixel portion drain electrode 223D1 and extend toward the pixel region, as shown in FIG. 4. The pixel portion drain electrode pattern 225P2 may be a pixel electrode. At the same time, circuit portion first and second source electrode patterns 225P5 and 225P3 are formed in the p-channel TFT region and the n-channel TFT region of the circuit portion to cover the circuit portion first and second source electrodes 223S2 and 223S3. In addition, the circuit part first and second drain electrode patterns 225P6 and 225P4 covering the circuit part first and second drain electrodes 223D2 and 223D3 are formed.

As described above, in the present invention, when the circuit portion first gate electrode, the first gate line connected to the circuit portion first gate electrode, the circuit portion second gate electrode, and the second gate line connected to the circuit portion second gate electrode are formed. First, the first gate line and the second gate line are patterned in one direction over the entire circuit portion n-channel TFT region and the circuit portion p-channel TFT region, and the first gate line is patterned to include the circuit portion p-channel gate electrode. Subsequently, the circuit unit n-channel gate electrode connected to the second gate line is patterned. At this time, the first gate line and the second gate line may be patterned once more in one direction while the n-channel gate electrode is patterned. Therefore, the present invention can solve the existing problem that the profile of the first gate line and the second gate line corresponding to the boundary between the n-channel TFT region and the p-channel TFT region becomes poor.

According to the present invention, a circuit portion first gate electrode connected to the first gate line is formed while patterning the first gate line and the second gate line in one direction over the entire circuit portion n-channel TFT region and the circuit portion p-channel TFT region. . Subsequently, the second gate electrode of the circuit part connected to the second gate line is patterned. Therefore, the present invention can prevent the side profile of the first gate line and the second gate line from deteriorating at the boundary portion of the circuit portion n-channel TFT region and the circuit portion p-channel TFT region.

In addition, the present invention provides a space between the first gate line and the second gate line in consideration of poor side profile of the first gate line and the second gate line at the boundary portion of the circuit portion n-channel TFT region and the circuit portion p-channel TFT region. Since there is no need, there is an advantage in high integration.

Claims (7)

Providing a substrate in which a pixel portion divided into a TFT region and a storage region and a circuit portion divided into a p-channel TFT region and an n-channel TFT region are defined; Forming a second active layer and a third active layer in an n-channel TFT region and a p-channel TFT region of the circuit portion of the substrate, respectively; Forming a gate insulating film, a first metal film, and a second photoresist film pattern on a substrate having the second and third active layers; By selectively patterning the first metal film using the second photoresist pattern, the first gate line and the first gate line arranged in one direction over the entire n-channel region and p-channel TFT region of the circuit part and a predetermined distance from the first gate line. Forming a second gate line spaced apart from each other, and forming a circuit portion first gate electrode connected to the first gate line in a p-channel TFT region of the circuit portion; After removing the second photoresist layer pattern, p + doping is performed on a substrate having the first gate electrode and the first gate line of the circuit part, thereby forming a circuit part first source / drain region on the third active layer under both sides of the first gate electrode of the circuit part. Forming; Forming a third photoresist pattern on the substrate having the first gate electrode, the first gate line, and the second gate line; Selectively patterning the first metal layer using the third photoresist pattern to form a pixel portion gate electrode and a common line in the pixel portion, and a circuit portion connected to the second gate line in an n-channel TFT region of the circuit portion Forming a second gate electrode; Performing a n + doping on a substrate having the circuit portion second gate electrode to form a circuit portion second source / drain region in the second active layer under both sides of the circuit portion second gate electrode; Forming a protective film on the substrate having the circuit portion second gate electrode; And After forming the second metal film on the passivation layer, the second metal film is selectively patterned to form circuit part second source / drain electrodes and first source / drain electrodes in the n-channel TFT region and the p-channel TFT region, respectively. Method of manufacturing a liquid crystal display device comprising the step. The storage area of the pixel portion according to claim 1, wherein when the second active layer and the third active layer are formed in the n-channel TFT region and the p-channel TFT region of the circuit portion, respectively, the first active layer is formed in the TFT region of the pixel portion. Forming a storage electrode in the liquid crystal display device characterized in that. 3. The semiconductor device of claim 2, wherein a first active layer and a storage electrode are formed in a TFT region and a storage region of the pixel portion, respectively, and a second active layer and a third active layer are formed in an n-channel TFT region and a p-channel TFT region, respectively. The steps to Sequentially forming a buffer layer, a polysilicon film, an insulating film, and a storage electrode film on the substrate; Forming a first photoresist pattern on the substrate having the storage electrode layer; First and second etching of the storage electrode film, the insulating film, and the polysilicon film by using the first photoresist pattern, the pixel pattern covering the pixel portion, and the first and second covering the n-channel TFT region and the p-channel TFT region of the circuit portion, respectively. Forming two circuit patterns; Ashing the first photoresist pattern to form a remaining first photoresist pattern; And A storage electrode layer formed on the storage region of the pixel portion by selectively etching the storage electrode layer and the insulating layer selectively from the pixel pattern and the first and second circuit patterns exposed using the remaining first photoresist layer pattern; Forming an electrode and forming first, second and third active layers each of the polysilicon film in the TFT region of the pixel portion, the n-channel TFT region and the p-channel TFT region of the circuit portion, respectively. A method of manufacturing a liquid crystal display device. The first gate line region of claim 1, wherein the second photoresist pattern covers the entire pixel portion, and is arranged in the p-channel TFT region and the n-channel TFT region of the circuit portion in one direction. Covers the second gate line region spaced apart from the first gate line region and the n-channel TFT region of the circuit portion connected to the second gate line region, and the first gate line region in the p-channel TFT region of the circuit portion. And patterning the substrate to further cover a p-channel gate electrode region connected to the substrate. The semiconductor device of claim 4, wherein the third photoresist layer pattern is disposed at a predetermined interval from the first gate line region and the first gate line region arranged in one direction over the entire p-channel TFT region and n-channel TFT region of the circuit portion. An n-channel gate electrode covering the p-channel TFT region of the circuit portion connected to the second gate line region and the first gate line region spaced apart from each other, and connected to the second gate line region in the n-channel TFT region of the circuit portion Patterned to cover the region further. The liquid crystal of claim 1, wherein the patterning of the first metal layer using the third photoresist pattern is performed by wet etching to over-etch the sidewalls of the pixel portion gate electrode, the common line, and the circuit portion second gate electrode. Method for manufacturing a display device. 7. The method of claim 6, wherein the circuit portion second source / drain regions are formed in the second active layers under both sides of the circuit portion second gate electrode. Removing the third photoresist pattern; And And n-doping the entire surface of the substrate using the pixel portion gate electrode and the circuit portion second gate electrode as a mask to form an LED region in the n-channel TFT region of the circuit portion. Manufacturing method.

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