KR101354239B1 - Apparatus and method for interleaving/de-interleaving channel in a mobile communication system - Google Patents

Abstract

The present invention relates to a channel interleaving method in a mobile communication system having an encoder and a channel interleaver using a low density parity check (LDPC) code. When the inputted code bits correspond to modulation symbols, the inputted code bits are classified so that they can be output for each corresponding position, and the bit strings are output for each position, and the channel interleaver performs channel interleaving and outputs the inputted bit strings. In the mapper, a process of converting each of the channel strings interleaved and outputted into modulation symbols is performed.

Channel interleaving, reliability, order, variable node, check node, modulation symbol, channel deinterleaving

Description

Apparatus and method for channel interleaving / deinterleaving in a mobile communication system {APPARATUS AND METHOD FOR INTERLEAVING / DE-INTERLEAVING CHANNEL IN A MOBILE COMMUNICATION SYSTEM}

1 is a diagram illustrating a parity check matrix of a general (8, 2, 4) LDPC code;

2 is a diagram illustrating a factor graph of a general (8, 2, 4) LDPC code;

3 is a diagram schematically illustrating a structure of a mobile communication system using an LDPC code according to an embodiment of the present invention;

4 is a graph illustrating BER per bit of an LDPC code having a codeword length of 576 and a code rate of 1/2;

5 is a diagram illustrating an operation of a channel interleaver according to the first embodiment of the present invention;

6 is a view for explaining the detailed operation of the channel interleaver of FIG.

7 is a flowchart illustrating a channel interleaving control method in a mobile communication system using an LDPC code according to an embodiment of the present invention.

The present invention relates to a channel interleaving / deinterleaving apparatus and method in a mobile communication system, and more particularly to a channel interleaving / deinterleaving apparatus in a mobile communication system using a Low Density Parity Check (LDPC) code. And to a method.

With the rapid development of mobile communication systems, there is a demand for the development of a technology capable of transmitting a large amount of data approaching the capacity of a wired network in a wireless network. As a high-speed and high-capacity communication system capable of processing and transmitting various information such as video and wireless data is required beyond the voice-oriented service, it is necessary to improve the system transmission efficiency by using an appropriate channel coding method As a result. However, due to the characteristics of the mobile communication system, the mobile communication system inevitably generates an error due to noise, interference, fading, etc. according to channel conditions when transmitting data. Loss of information data due to error occurs.

In order to reduce information data loss due to such an error, reliability of the mobile communication system can be improved by using various error-control schemes according to the characteristics of the channel. Among the above error control techniques, error control techniques most commonly used are techniques using error-correcting codes. Representative codes of the error correction code include a turbo code, an LDPC code, and the like.

The turbo code is known to have a superior performance gain in high-speed data transmission, compared to a convolutional code used mainly for error correction. The turbo code effectively corrects errors due to noise generated in a transmission channel and transmits data. It has the advantage of increasing the reliability of. In addition, the LDPC code may be decoded using an iterative decoding algorithm based on a sum-product algorithm on a factor (hereinafter, referred to as a 'factor') graph. Since the decoder of the LDPC code uses an iterative decoding algorithm based on the sum product algorithm, the LDPC code not only has a lower complexity than the decoder of the turbo code but also can be easily implemented as a parallel processing decoder.

Shannon's channel coding theorem, on the other hand, says that reliable communication is possible only at data rates that do not exceed the capacity of the channel. However, Shannon's channel coding theory has not provided any concrete method for channel encoding and decoding that supports data rates up to the maximum channel capacity limit. Generally, random codes with very large block sizes show performance close to the channel capacity limit of Shannon's channel coding theory, but use a maximum a posteriori (MLAP) or maximum likelihood (ML) decoding method. In this case, there was a huge load in the calculation amount, and the actual implementation was impossible.

을 사용하여 비트 에러 레이트(Bit Error Rate, BER)

에서 Shannon의 채널 부호화 이론의 채널 용량 한계에서 단지 0.04[dB] 정도의 차이를 가지는 성능을 나타낸다. 또한, q>2인 갈로아 필드(Galois Field, 이하 'GF'라 칭함), 즉 GF(q)에서 정의된 LDPC 부호는 그 복호화 과정에 있어서 복잡도가 증가하긴 하지만 이진(binary) 부호에 비해 훨씬 더 우수한 성능을 보인다. 그러나, 상기 GF(q)에서 정의된 LDPC 부호의 반복 복호화 알고리즘의 성공적인 복호화에 대한 만족스런 이론적인 설명은 아직 이루어지지 않고 있다.The turbo code was proposed in 1993 by Berrou, Glavieux, and Thitimajshima, and has excellent performance approaching the channel capacity limit of Shannon's channel coding theory. Due to the proposal of the turbo code, studies on iterative decoding and graph representation of the code have been actively conducted, and at this point, the LDPC code, which Gallallager has already proposed in 1962, is newly illuminated. In addition, a cycle exists on the factor graph of the turbo code and the LDPC code, and it is well known that iterative decoding on the factor graph of the LDPC code in which the cycle exists is suboptimal, The LDPC code has also been experimentally proved to have excellent performance through the iterative decoding. The best performing LDPC code known to date is block size

Bit Error Rate (BER)

Shows a performance of only 0.04 [dB] in the channel capacity limit of Shannon's channel coding theory. In addition, an LDPC code defined in Galois Field (hereinafter, referred to as 'GF'), that is q> 2, ie, GF (q), is much more complicated than binary code, although its complexity is increased in the decoding process. Better performance. However, a satisfactory theoretical explanation for successful decoding of the iterative decoding algorithm of the LDPC code defined in the GF (q) has not been made yet.

In addition, the LDPC code is a code proposed by Gallager, and is defined by a parity check matrix in which most elements have a value of 0 and very few elements other than the elements having a value of 0 have a value of 1. do. For example, the (N, j, k) LDPC code is a linear block code having a block length of N, elements having j values of 1 for each column, and each row. A sparse structure consisting of elements having k values of 1 per (row), and all elements except 0 having values of 1 are elements having a value of 0. It is defined by the parity check matrix of.

As described above, the order of each column in the parity check matrix is constant as j, and the order of each row in the parity check matrix is constant as k. The LDPC code is referred to as a regular LDPC code. Here, the degree represents the number of elements having a non-zero value among elements constituting the generation matrix and parity check matrix of the LDPC code. In contrast, an LDPC code in which the order of each column and the order of each row in the parity check matrix is not constant is called an irregular LDPC code. In general, it is known that the performance of the non-uniform LDPC code is superior to that of the uniform LDPC code. However, in the case of the non-uniform LDPC code, since the order of each column and the order of each row in the parity check matrix are not constant, that is, they are nonuniform, the order of each column in the parity check matrix and the order of each row must be properly adjusted. Can be guaranteed.

Next, a parity check matrix of an (N, j, k) LDPC code, for example, an (8, 2, 4) LDPC code will be described with reference to FIG. 1.

1 is a diagram illustrating a parity check matrix of a general (8, 2, 4) LDPC code.

Referring to FIG. 1, first, the parity check matrix H of the (8, 2, 4) LDPC code is composed of eight columns and four rows, and the order of each column is equal to two, and the order of each row is Uniform to 4 In this way, since the order of each column and the order of each row in the parity check matrix are uniform, the (8, 2, 4) LDPC code shown in FIG. 1 becomes a uniform LDPC code.

In FIG. 1, a parity check matrix of an (8, 2, 4) LDPC code has been described. Next, a factor graph of the (8, 2, 4) LDPC code described with reference to FIG. 1 will be described with reference to FIG. 2. do.

FIG. 2 is a diagram illustrating a factor graph of the (8, 2, 4) LDPC code of FIG.

(211)과,

(212)과,

(213)과,

(214)과,

(215)과,

(216)과,

(217)과,

(218)와, 4개의 검사 노드(check node)(220)들(221,222,223,224)로 구성된다. 상기 (8, 2, 4) LDPC 부호의 패리티 검사 행렬의 i번째 행과 j번째 열이 교차하는 지점에 1의 값을 가지는, 즉 0이 아닌 값을 가지는 엘리먼트가 존재할 경우 변수 노드

와 j번째 검사 노드 사이에 브랜치(branch)가 생성된다.Referring to FIG. 2, the factor graph of the (8, 2, 4) LDPC code includes eight variable nodes 210, that is,

(211),

(212),

(213),

(214),

215,

216,

(217),

218 and four check nodes 220 (221, 222, 223, 224). Variable node when an element having a value of 1, that is, a nonzero value, exists at a point where the i th row and the j th column of the parity check matrix of the (8, 2, 4) LDPC code intersect.

A branch is created between and the j th check node.

As described above, since the parity check matrix of the LDPC code has a very small order, it can be decoded through iterative decoding even in a block code having a relatively long length, and if the block length of the block code is continuously increased, as in the turbo code, It shows performance close to Shannon's channel capacity limit. In addition, MacKay and Neal have already demonstrated that the iterative decoding process of the LDPC code using the flow transfer method has a performance almost close to the iterative decoding process of the turbo code.

Meanwhile, in order to generate a high performance LDPC code, several conditions must be satisfied. The above conditions are described below.

(1) The cycle on the factor graph of the LDPC code must be considered.

The cycle represents a loop formed by an edge connecting a variable node and a check node in a factor graph of an LDPC code, and the length of the cycle is defined as the number of edges constituting the loop.

The long length of the cycle indicates that the number of edges connecting the variable nodes and the check nodes constituting the loop in the factor graph of the LDPC code is large. On the contrary, the shorter cycle length indicates that the number of edges connecting the variable nodes and the check nodes constituting the loop in the factor graph of the LDPC code is small.

The longer the cycle on the factor graph of the LDPC code is generated, the better the performance of the LDPC code is.

This is because when a long cycle on the factor graph of the LDPC code is generated long, performance degradation such as an error floor generated when there are many short length cycles on the factor graph of the LDPC code does not occur.

(2) Consideration should be given to efficient coding of LDPC codes.

The LDPC code has a higher coding complexity than a convolutional code or a turbo code due to the characteristics of the LDPC code. In order to reduce the coding complexity of the LDPC code, a repeat accumulate code (Repeat Accumulate (RA) code) or the like has been proposed, but the repeat accumulator code also has a limitation in reducing the coding complexity of the LDPC code. Therefore, efficient coding of LDPC codes must be considered.

(3) The order distribution on the factor graph of the LDPC code should be considered.

In general, a non-uniform LDPC code performs better than a uniform LDPC code because the degree on the factor graph of the non-uniform LDPC code has various orders. Here, the order represents the number of edges connected to each node, that is, variable nodes and check nodes, on the factor graph of the LDPC code. In addition, the order distribution on the factor graph of the LDPC code indicates how many nodes among the nodes have a certain order. Richardson et al. Have already demonstrated that the performance of LDPC codes with a particular order distribution is superior.

However, no consideration has been given to a specific method of performing channel interleaving / deinterleaving in consideration of the characteristics of the LDPC code in the mobile communication system using the LDPC code. In addition, there is a problem that an error that cannot be restored even after repeated decoding due to effects of fading occurs. Accordingly, there is a need for a specific method of performing channel interleaving / deinterleaving in consideration of the characteristics of the LDPC code in a mobile communication system using the LDPC code.

Accordingly, the present invention provides a channel interleaving / deinterleaving apparatus and method in a mobile communication system using an LDPC code.

The present invention also provides a channel interleaving / deinterleaving apparatus and method for minimizing an error rate in a mobile communication system using an LDPC code.

The present invention also provides a channel interleaving / deinterleaving apparatus and method considering the characteristics of the LDPC code in a mobile communication system using the LDPC code.

In addition, the present invention provides a channel interleaving / deinterleaving apparatus and method for classifying each bit string by the order of a variable node in a parity check matrix in a mobile communication system using an LDPC code.

In addition, the present invention provides a channel interleaving / deinterleaving apparatus and method for dividing each bit string by a predetermined number in a mobile communication system using an LDPC code.

A channel interleaving method in a mobile communication system according to an embodiment of the present invention is a channel interleaving method in a mobile communication system having an encoder and a channel interleaver using a low density parity check (LDPC) code. In the demux, when the channel coded coded bits are input, when the input coded bits correspond to modulation symbols, the demux classifies them to be output for each corresponding position and outputs the bit strings for each position, and in the channel interleaver. And a process of channel interleaving and outputting the inputted bit strings, and converting each of the bit strings output from the channel interleaved and output to a modulation symbol in a mapper. The process of outputting the channel interleaving includes: For each of the bit streams classified by the order of the corresponding variable node in the parity check matrix And a second step of channel interleaving so as to maximize a distance between bits corresponding to variable nodes connected to the same check node with respect to the sorted bit streams, the order of the variable node and the channel. The number of interleavers is the same.

In the mobile communication system according to an embodiment of the present invention, the channel interleaving apparatus is a channel interleaving apparatus in a mobile communication system having an encoder and a channel interleaver using a Low Density Parity Check (LDPC) code. When the channel coded coded bits are input, a demux for classifying the input coded bits to be output for each corresponding position when the corresponding coded bits correspond to modulation symbols, and outputting the bitstreams for each position, and interleaving the inputted bitstreams And a mapper for converting each of the channel interleaved bit streams into modulation symbols, wherein the channel interleaver classifies the bit interleaves according to the order of variable nodes corresponding to the parity check matrix. Performing the first step of performing the same step with respect to the classified bit streams. To maximize the distance between the bit corresponding to the variable nodes connected to the node performing the second step of channel interleaving, the number of the order and the channel interleaver in the variable node is characterized in that it is the same.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

The present invention proposes a channel interleaving / de-interleaving apparatus and method for minimizing an error rate in a mobile communication system using an LDPC code. In particular, the present invention proposes a channel interleaving / deinterleaving apparatus and method for maximizing code performance by channel interleaving to minimize an error rate when a coded LDPC codeword is transmitted in a fading channel.

3 is a diagram schematically illustrating a structure of a communication system using an LDPC code according to the present invention.

Referring to FIG. 3, first, the communication system includes a transmitter 300 and a receiver 350.

The transmitter 300 includes an encoder 311, a channel interleaver 313, and a modulator 315.

In addition, the receiver 350 includes a de-modulator 351, a channel de-interleaver 353, and a decoder 355.

First, the transmitter 300 will be described.

First, when information data bits are input, the information data bits are transferred to the encoder 311. The encoder 311 receives the transmitted information data bits, encodes them using a predetermined encoding scheme, generates a codeword, and outputs the encoded words to the channel interleaver 313. Here, the encoder 311 is an LDPC encoder, so the codeword generated by the encoder 311 is an LDPC codeword.

The channel interleaver 313 receives the LDPC codeword output from the encoder 311, interleaves the channel interleaving method, and outputs the LDPC codeword to the modulator 315. In this case, the channel interleaver 313 uses the LDPC codeword output from the encoder 311 as the channel interleaving method to prevent an error that cannot be restored even after repeated decoding due to fading or the like. To interleave. Here, the channel interleaving operation of the channel interleaver 313 is performed corresponding to the channel interleaver method proposed in the present invention, which will be described in detail below, and thus the detailed description thereof will be omitted.

The modulator 315 modulates a signal output from the channel interleaver 313, that is, a channel interleaved LDPC codeword, using a predetermined modulation scheme, and then transmits the receiver through a transmit antenna 317 (Tx. Ant). 350). In this case, the channel interleaver 313 performs channel interleaving so that the modulator 315 can allocate the LDPC codewords interleaved with the channel to the modulation symbol in a form that minimizes an error rate when modulating the channel interleaved LDPC code. That is, the channel interleaver 313 is designed using a cycle characteristic of variable nodes of a corresponding parity check matrix of an LDPC codeword and a characteristic in which the bit error rate of each bit of the LDPC codeword differs according to the order distribution. Since this will be described in detail below, detailed description thereof will be omitted.

Secondly, the receiver 350 will be described.

The signal transmitted from the transmitter 300 is received through the receiving antenna 351 (Rx.Ant), and the signal received through the receiving antenna 351 is transmitted to the demodulator 353. The demodulator 353 demodulates the signal received through the receiving antenna 351 in a demodulation method corresponding to the modulation method applied by the modulator 315 of the transmitter 300 and then outputs the demodulated signal to the channel deinterleaver 355. do.

The channel deinterleaver 355 deinterleaves the signal output from the demodulator 353 by the channel deinterleaving method corresponding to the channel interleaving method applied by the interleaver 313 of the transmitter 300, and then the decoder 357. Will output Here, the channel deinterleaving operation of the channel deinterleaver 353 is also performed corresponding to the channel interleaver method proposed in the present invention, which will be described in detail below, and thus the detailed description thereof will be omitted.

The decoder 357 decodes a decoding method corresponding to the encoding method applied by the encoder 311 of the transmitter 300 to restore the final information data bit.

Meanwhile, in FIG. 3, a transmitter structure for a separate radio frequency (RF) signal transmission process after the modulator 315 and an RF signal reception process before the demodulator 351 are shown. Although the structure of the receiver is not shown, a signal output from the modulator 315 is RF-processed and transmitted through the transmitter, and a signal received by RF-processing through the receiver is provided to the demodulator 353.

Hereinafter will be described in detail with respect to the channel interleaver according to the present invention.

In general, fading channels have similar fading characteristics in contiguous channels. That is, signals transmitted in concatenated time or concatenated subcarriers on the time or frequency axis experience similar fading paths. Therefore, an error phenomenon may occur in which signals concatenated in a fading channel continuously generate an error. When the LDPC codeword is used, it is difficult to recover the codeword bits corresponding to the low order variable node in the parity check matrix. In particular, when variable nodes corresponding to codeword bits in which consecutive errors occur are connected to the same check node, recovery of the error becomes difficult even if the codeword bits are decoded. Therefore, the interleaver should be designed in consideration of the above characteristics.

Here, referring to FIG. 4, a bit error rate (hereinafter, referred to as BER) of an LDPC code having a codeword length of 576 and a coding rate of 1/2 is referred to. Let's explain.

4 is a graph illustrating BER per bit of an LDPC code having a codeword length of 576 and a code rate of 1/2.

Referring to FIG. 4, first, the x-axis represents each of the first to 576th bits, and corresponds to the first to 576th columns of the parity check matrix. Next, the y-axis represents the BER of each of the first to 576th bits.

The LDPC code having a codeword length of 576 and a coding rate of 1/2 corresponds to a variable node of degree 3 from the first bit to the 192nd bit, and the 193 th to 288th bits are the variable node of degree 6 The remaining bits correspond to variable nodes of degree 2 or 3. Here, the order of the variable node corresponds to the order of the corresponding column.

As shown in FIG. 4, the BERs of the first to 192th bits and the 289th to 576th bits, which correspond to the variable nodes having a low order, are the 192th bits to the variable nodes having a high order. It can be seen that the BER is higher than the 288th bit.

The LDPC code may be decoded using an iterative decoding algorithm based on a sum-product algorithm on a factor (hereinafter, referred to as a 'factor') graph. However, since the reliability of each coded bit is affected by the variable node order structure due to the nature of the sum product algorithm, in general, as the number of bits corresponding to a small order variable node, that is, the number of check nodes connected to the variable node is small, The reliability of the corresponding bit is lowered. On the other hand, the higher the number of bits corresponding to the high variable node, that is, the number of check nodes connected to the variable node, the higher the reliability of the bit corresponding to the variable node.

In conclusion, the reliability of the LDPC code is also affected by the number of check nodes connected to the variable nodes on the factor graph, that is, the order of the variable nodes. high.

Accordingly, the present invention designs a channel interleaver capable of maximizing the distance between bits corresponding to a variable node having low reliability in consideration of node order characteristics, and the design method is as follows.

<Channel Interleaving Method According to First Embodiment of the Present Invention>

First step: classify each bit string by the order of the corresponding variable node in the parity check matrix.

Second step: It is possible to maximize the distance between the bits corresponding to the variable node connected to the same check node for the classified bit streams in the first step. At this time, the bit strings corresponding to the lowest order are first positioned to satisfy the condition, and then the bit strings corresponding to the lower order are positioned to be as far as possible from the position other than the position. The above method is repeated so that all bits can be located.

An interleaver operation according to the channel interleaving method will be described with reference to the first embodiment.

5 is a diagram illustrating channel interleaver operation in a transmitter according to an embodiment of the present invention.

FIG. 5 illustrates a case where a 16-QAM (Quardrature Amplitude Modulation) scheme, which is a modulation scheme generally used in a mobile communication system, is applied.

로 구성된다. 각각의 위치들은 부호화된 비트들이 매핑되며 본 발명에서는 인터리빙된 부호화된 비트들이 매핑된다. 각 변조 심볼에 대응되는 비트 위치별로 대응되는 비트들을 다수의 비트열들로 분리한다. 즉, QPSK를 사용할 경우 2개 비트열들로 분리되며, 16-QAM을 사용할 경우 4개의 비트들로 분리되며, 64-QAM을 사용할 경우 6개의 비트열들로 분리 된다. In 16-QAM, one modulation symbol

. Each position is mapped to coded bits and in the present invention, interleaved coded bits are mapped. Bits corresponding to bit positions corresponding to each modulation symbol are divided into a plurality of bit strings. In other words, when QPSK is used, it is divided into two bit strings. When 16-QAM is used, it is divided into four bits. When 64-QAM is used, it is divided into six bit strings.

When the channel coded coded bits are input to a demux 510, the demux 510 classifies the bit strings by each position so that the input code bits may be output by corresponding positions when the input code bits correspond to modulation symbols. Output In the present embodiment, only the 16-QAM modulation method has been described, but it is obvious that the present invention can be applied to a case in which other modulation methods are used.

Bit strings corresponding to the first position of the modulation symbol are input to interleaver 1 520, bit strings corresponding to the second position of the modulation symbol are input to interleaver 2 521, and third bits of the modulation symbol are input. The bit strings corresponding to the position are input to the interleaver 3 522, and the bit strings corresponding to the fourth position of the modulation symbol are input to the interleaver 4 523. When the input of the respective bit strings is input to each of the interleavers 520, 521, 522, and 523, the respective interleaver 1 520, the interleaver 2 521, the interleaver 3 522, and the interleaver 4 523 are inputted. After the interleaved bit streams are interleaved by the first and second channel interleaving methods, the output bit streams are inputted to a mapper 530 and converted into modulation symbols. Print a string of values and an imaginary string. In this case, operations of the interleaver 1 520, the interleaver 2 521, the interleaver 3 522, and the interleaver 4 523 will be described in detail below with reference to FIG. 6.

FIG. 6 is a diagram for describing a detailed operation of the channel interleaver of FIG. 5. Hereinafter, detailed operations of the interleavers of FIG. 5 will be described with reference to FIG. 6.

In the first embodiment of the present invention, it is assumed that there are three types of orders of variable nodes of the LDPC code used for better understanding of the present invention. If the order type is not 3, the number of interleavers is the same as the number of branches of the order type. When the bit streams input to the interleaver are input to the demux 610, the demux 610 may determine the order of the variable node corresponding to each bit in the parity check matrix according to the first step of the interleaver design method. Classified bitstreams are input to the interleavers 620, 621, and 622. At this time, the bit string corresponding to the low order variable node is input to interleaver 1 620, and the bit string corresponding to the next order variable node is input to interleaver 2 621, and then to the next order variable node. The corresponding bit string is input to interleaver 3 611. The interleaver 1 620, the interleaver 2 621, and the interleaver 3 622 interleave each input bit string and output the interleaved bit streams to the mux 630. In this case, each of the interleavers 620, 621, and 622 increases the distance between bits corresponding to the variable node connected to the same check node.

The mux 630 arranges and outputs the distance between the output bits of the interleaver 1 620 having interleaved the bit streams corresponding to the variable node having the lowest order according to the second step of the interleaver method. The output bits of the interleaver 1 620, which interleaves the bit streams corresponding to the next low order variable node, are arranged to have the largest distance among the remaining positions after the arrangement, and the above operation is repeated to repeat the operation of the interleaver 3. Arrange and output the output bits.

,

,

,

,

,

이며, 차수가 3인 변수 노드가 4개이며 대응되는 비트열이

,

,

,

이며, 차수가 12인 변수 노드가 2개이며 대응되는 비트열이

,

라고 가정하자. 상기 인터리버 1(620)에 입력되어지는 비트열은

,

,

,

,

,

이고 인터리버 2(621)에 입력되어지는 비트열은

,

,

,

이며 상기 인터리버 3(622)에 입력되어지는 비트열은

,

이다. 이때 인터리버 1(620)의 출력 비트열이

,

,

,

,

,

이고 인터리버 2(621)의 출력 비트열이

,

,

,

이고 인터리버 3(622)의 출력 비트열이

,

이라고 하자. 상기 먹스(630)의 출력 비트열은 다음과 같이 구할 수 있다.For example, there are six variable nodes of degree 2 and the corresponding bit strings

,

,

,

,

,

4 variable nodes of degree 3 and the corresponding bit string

,

,

,

Two variable nodes of degree 12 and the corresponding bit string

,

. The bit string input to the interleaver 1 620 is

,

,

,

,

,

And the bit string input to the interleaver 2 621 is

,

,

,

The bit string input to the interleaver 3 (622) is

,

to be. At this time, the output bit string of the interleaver 1 620 is

,

,

,

,

,

And the output bit stream of interleaver 2 (621)

,

,

,

And the output bit stream of interleaver 3 (622)

,

. The output bit string of the mux 630 can be obtained as follows.

,

,

, ....,

)에 대하여

=

,

=

,

=

,

=

,

=

,

=

으로 결정한다. 인터리버 2(621)의 출력 비트열에 대하여 상기 먹스(630)의출력 위치를 결정할 수 있다. 이때 상기 인터리버 1(620)의 출력 비트들이 있는 위치를 제외하고 거리가 멀도록 결정할 수 있다. 즉,

=

,

=

,

=

,

=

으로 결정할 수 있다. 그리고 인터리버 3(622)의 출력 비트열에 대하여 상기 먹스(630)의 출력위치를 결정할 수 있다. 이때 상기 인터리버 1(620)의 출력 비트들과 상기 인터리버 2(621)의 출력 비트들이 있는 위치를 제외하고 거리가 멀도록 결정할 수 있다. 즉,

=

,

=

으로 결정할 수 있다. As described above, the output position of the mux 630 may be determined with respect to the output bit string of the interleaver 1 620. At this time, in order to make the distance between each bit large, it may be decided to come in even-numbered positions. Therefore, the output bits of the mux 630 (

,

,

, ....,

)about

=

,

=

,

=

,

=

,

=

,

=

Decide on An output position of the mux 630 may be determined with respect to an output bit string of the interleaver 2 621. In this case, it may be determined that the distance is far except for the location where the output bits of the interleaver 1 620 are located. In other words,

=

,

=

,

=

,

=

Can be determined. The output position of the mux 630 may be determined with respect to the output bit string of the interleaver 3 622. In this case, it may be determined that the distance is far except for the position where the output bits of the interleaver 1 620 and the output bits of the interleaver 2 621 are located. In other words,

=

,

=

Can be determined.

In the first step of the channel interleaving method, each bit stream is divided according to an order, but may be input to the interleaver of FIG. The second embodiment of the present invention proposes a channel interleaving method for dividing each bit stream by a predetermined number without separating each bit stream according to the order.

<Channel Interleaving Method According to Embodiment 2 of the Present Invention>

First step: A predetermined number is distinguished for each bit string.

Second step: It is possible to maximize the distance between the bits corresponding to the variable node connected to the same check node for the classified bit streams in the first step. In this case, when the ordered variable nodes have a chain structure, the separated bit strings may be sequentially arranged. That is, the bit sizes of the interleavers of the interleaver 1 620 to the interleaver 3 622 of FIG. 6 are the same, and in the MUX 630, the output bits of the interleaver 1 620 to the interleaver 3 622 are sequentially ordered. Will output At this time, it is obvious that the interleaver may be three or more.

와 출력 비트들

사이의 관계식은 하기 <수학식 1>과 같다.If the bit sizes of the interleaver 1 520 to the interleaver 4 523 of FIG. 5 are I, the blocks are divided into B blocks. The number of bits in each block is A = I / B. In this case, the input bits of the e th interleaver

And output bits

The relationship between the equations is shown in Equation 1 below.

I, j in Equation 1 is an index i = 0, 1 ..., B-1, j = 0, 1, ..., A-1. For example, A = N / 16, B = 8 in a system using QPSK, A = N / 24, B = 6 when using 16QAM, A = N / 24, B = when using 64QAM. 4 can be used. Here, N means LDPC codeword length.

Hereinafter, a transmission method according to an exemplary embodiment of the present invention will be described with reference to FIG. 7. 7 is a flowchart illustrating control during transmission according to an embodiment of the present invention.

In step 700, LDPC encoding is performed. In step 710, LDPC codewords are separated into a plurality of bit streams according to a modulation scheme. As described above, when 16QAM is used, it is divided into four bit streams. It is obvious that it may not be separated into multiple bit streams. In operation 720, the separated bit streams are interleaved by an inverber designed for the channel interleaving method according to the first and second embodiments of the present invention. In step 730, the signal is modulated according to the set modulation scheme and transmitted to the receiver in step 740.

The above-described interleaver may be obtained through the same steps as described above, but it is obvious that the interleaver may be used using a look-up table. In addition, the present invention has been described with respect to the interleaver, it is obvious that it can be applied to the deinterleaver.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention.

In the present invention that operates as described in detail above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

The present invention has the advantage of improving the reliability of the LDPC code by controlling to perform channel interleaving in consideration of non-uniform reliability characteristics in a mobile communication system using the LDPC code.

In particular, the present invention improves the reliability of bits having low reliability among the bits constituting the LDPC code through the channel interleaving so that they are robust in a radio channel environment where a burst error such as a fading channel is likely to occur. Improve reliability In addition, the reliable transmission and reception of the LDPC code can reduce the error rate of the entire system and enable high-speed and reliable communication.

Claims (9)

In a channel interleaving method in a mobile communication system having an encoder and a channel interleaver using a low density parity check (LDPC) code, In the demux, when the channel coded coded bits are input, classifying the coded bits so that they can be output by corresponding positions when the coded bits correspond to modulation symbols, and outputting a bit string for each position; Outputting the channel by interleaving the bit streams in a channel interleaver; In the mapper, converting each of the bit streams output from the channel interleaved to a modulation symbol, The process of outputting the channel interleaving, A first step of classifying the respective bit strings by the order of the corresponding variable node in the parity check matrix; A second step of channel interleaving for maximizing the distance between bits corresponding to the variable node connected to the same check node for the classified bit strings; And the order of the variable nodes and the number of channel interleavers are the same. The method of claim 1, The channel interleaver positions the bit streams corresponding to the lowest order so as to satisfy the first and second steps first, and then positions the bit streams corresponding to the lower order as far as possible from the position. A channel interleaving method in a mobile communication system. The method of claim 1, The channel interleaving method, Classifying a predetermined number of bits for each bit string; And channel interleaving for the classified bit strings to maximize a distance between bits corresponding to variable nodes connected to the same check node. The method of claim 3, wherein Input bits for the classified bit strings

And output bits

The relationship between the channel interleaving method in a mobile communication system comprising satisfying the following Equation 2, &Quot; (2) &quot;

Here, i, j is an index i = 0, 1 ..., B-1, j = 0, 1, ..., A-1, and A = N / 16, B = in a system using QPSK. 8 uses A = N / 24, B = 6 for systems using 16QAM, A = N / 24, B = 4 for systems using 64QAM, where N is the LDPC codeword length Means. A channel interleaving apparatus in a mobile communication system having an encoder and a channel interleaver using a low density parity check (LDPC) code, When the channel coded coded bits are input, a demux for classifying the input coded bits to be output for each corresponding position when the corresponding coded bits correspond to modulation symbols, and outputting bit strings for each position; The channel interleaver for channel interleaving and outputting the bit strings; A mapper for converting each of the channel interleaved bit strings into a modulation symbol, The channel interleaver performs a first step of classifying each of the bit streams by the order of the corresponding variable node in the parity check matrix, and bit corresponding to the variable node connected to the same check node with respect to the classified bit streams. Performing a second step of channel interleaving so as to maximize the distance between them, And the order of the variable node and the number of channel interleavers are the same. delete The method of claim 5, The channel interleaver, A channel in the mobile communication system including classifying each bit string by a predetermined number and interleaving the channel to maximize the distance between bits corresponding to the variable nodes connected to the same check node. Interleaving device. The method of claim 7, wherein Input bits for the classified bit strings

And output bits

The relationship between the channel interleaving apparatus in the mobile communication system, including satisfying the following equation (3), &Quot; (3) &quot;

Here, i, j is an index i = 0, 1 ..., B-1, j = 0, 1, ..., A-1, and A = N / 16, B = in a system using QPSK. 8 uses A = N / 24, B = 6 for systems using 16QAM, A = N / 24, B = 4 for systems using 64QAM, where N is the LDPC codeword length Means. The method of claim 5, The channel interleaver, Positioning the bit streams corresponding to the lowest order so as to satisfy the first and second steps first, and then positioning the bit streams corresponding to the lowest order as far as possible from the position. Channel interleaving apparatus in a mobile communication system.

Images