KR101365428B1 - Apparatus for fast memory testing in solid state drive tester - Google Patents

Abstract

A high-speed memory test device is disclosed in a solid state drive tester that adds the ability to test memory or large scale integrated circuits (LSIs) to the storage tester, allowing the memory or LSI to be tested at high speed without additional cost.
The high speed memory test apparatus in the disclosed solid state drive tester includes: a host terminal for receiving a test condition for storage or memory or a large scale integrated circuit (LSI) test from a user; In the case of the storage test, a test pattern corresponding to a test condition is generated from the host terminal to test the storage, and in the case of the memory or LSI test, the memory or LSI test is performed based on the pattern data transmitted from the host terminal. Test control means for generating a test pattern to test the memory or the LSI; In the case of the memory or LSI test, synchronization control means is provided to synchronize the test pattern to the memory or the LSI such that the test pattern generated by the test control means changes at the same time.

Description

Apparatus for fast memory testing in solid state drive tester

The present invention relates to a high speed memory test apparatus in a solid state drive (SSD) tester, and more particularly, to a high speed memory test apparatus in a solid state drive tester for testing storage at high speed. will be.

To date, hard disks (HDDs) are the most commonly known and used mass storage media. However, in recent years, as the price of NAND flash semiconductor devices having the characteristic of storing the largest capacity among the semiconductor devices having a memory function and the data stored therein are not erased even when the power is not supplied, the semiconductor devices having the memory function have been used. New mass media storage devices such as SSDs are emerging.

These SSDs have three to five times faster write and read speeds than conventional hard disks, and hundreds of times read / write speeds for random addresses required by database management systems. It has excellent performance. In addition, since SSD operates in a silent manner, it can solve the problem of noise, which is a disadvantage of the existing hard disk, and operates at a low power level that is incomparable with that of a hard disk. It is known to be the most suitable.

In addition, it has the advantages of being more durable than conventional hard disks against external shocks, and in terms of design for external appearance, it can be manufactured in a smaller and more diverse form compared to a hard disk of a standard shape. It is possible to make the appearance of the electronic product in which the device is used smaller, which has many advantages in terms of its application.

Due to these advantages, SSD devices are rapidly spreading not only to existing desktop computers and laptop computers, but also to storage media for search, home shopping, video service servers, storage media for various research and development, and special equipment fields. Forecasts are expected to expand.

In order to test such an SSD device, a conventional SSD test device is disclosed in FIG. 1.

The conventional SSD test apparatus illustrated in FIG. 1 includes a host terminal 10, a network 20, test control means 30, and a memory 50. In FIG. 1, reference numeral 60 denotes a storage unit 60 under test.

The test control unit 30 includes a communication interface unit 31, an embedded processor 32, and a storage interface unit 33. The test control means 30 implements a plurality of devices in one chip using a field programmable gate array (FPGA).

The storage interface unit 33 includes a plurality of multi-interfacers 41 to 41 + N to test a plurality of storage at the same time, and the plurality of multi-interfacers 41 to 41 + N respectively have internal configuration and Since the operations are the same, only one multi-interface 41 will be described below for convenience of explanation.

The network 20 maintains a wired or wireless network connection with the host terminal 10. The network 20 may be connected to the host terminal 10 through wired communication such as LAN, USB, or RS-232, and may be connected to the host terminal through short-range wireless communication such as Bluetooth, Zigbee, or UWB. 10) can be connected.

The user inputs a test condition through the host terminal 10, and the test condition thus input is received by the test control means 30 through the network 20, and the embedded processor through the internal communication interface 31. Is passed to 32.

The embedded processor 32 generates a test pattern for testing the storage 60 in association with the memory 50 according to the test condition that is passed. The test pattern may be implemented as various types of test patterns widely used for testing various storage devices including SSDs.

The embedded processor 32 controls the test of the storage 60 by using the generated test pattern. For example, the test signal may be generated based on the test pattern, and the test signal may be transmitted to the storage 61 through the storage interface 33 to control the test of the storage 61.

Here, in order to interface the storage 61, the multi-interfacer 41 may include a Serial-ATA (SATA) interface device supporting a Serial-ATA (SATA) interface and a Serial Attached SCSI (SAS) supporting a Serial Attached SCSI (SAS) interface. A PCIe interface (PCIe) interface device supporting a PCIe interface (PCIe), and an interfacer corresponding to the interface of the storage 61 is selected under the control of the embedded processor 32, and the storage 61 is selected. Data is written into or the data recorded in the storage 61 is read. The data transfer rates of the SATA / SAS / PCIe and the like are differential according to specifications, but are usually about 1.5 Gbps to 6 Gbps.

The embedded processor 32 compares the read data with the write data to determine the state of the storage 61.

However, the prior art as described above can be tested for storage, but devices such as memory or LSI cannot be tested.

For example, memory or LSI can be tested at a fairly high speed, which is not possible with conventional storage testers, and requires the use of expensive equipment capable of a separate high speed test.

Therefore, in order to test memory or LSI, expensive memory test equipment must be provided separately from the storage tester, which is a burden in terms of cost, and it is necessary to replace the equipment according to the test target (storage, memory, LSI, etc.). There was also discomfort.

Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art,

The problem to be solved by the present invention is to provide a high-speed memory test device in a solid state drive tester that adds the ability to test the memory or LSI to the storage tester to test the memory or LSI at high speed without additional cost There is.

The high speed memory test apparatus in the solid state drive tester according to an embodiment of the present invention for solving the above problems,
A host terminal for receiving a test condition for a storage test from a user;

And test control means for generating a test pattern corresponding to a test condition input from the host terminal to test the storage.

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The test control means may include a device for interfacing user information, a device for interfacing the storage and memory, a device for generating a test pattern and controlling a test, a device for processing failure data generated during a test, and failure data. A device that is stored separately is configured as one chip using a field programmable gate array (FPGA).

The test control means in the above,

A communication interface unit for interfacing with the host terminal;

A vector memory for receiving and storing a pattern for testing an LSI from the host terminal and outputting vector data when the LSI is tested;

Store the pattern data transmitted from the host terminal in the internal memory for the test of the memory and the LSI, and generates and outputs a test pattern from the pattern data stored in the internal memory during the test of the memory, the test of the LSI A pattern generator for outputting vector data output from the vector memory as a test pattern;

An embedded processor controlling pattern generation for storage, memory, and LSI testing in the pattern generator;

And pattern interface means for transmitting a test pattern generated in the pattern generator to a storage or memory or an LSI under the control of the embedded processor, and interfacing read data read from the storage or memory or the LSI to the pattern generator. It is characterized by.

In the above, the pattern generator,

Read data from the storage or memory or LSI to compare with the previously stored expected data to determine the failure, to store the failure information occurred when the failure, and to transmit the stored failure information to the host terminal when the test is finished. It is done.

In the above, the pattern generator,

An interface unit for receiving register values and pattern data transmitted from the host terminal and transmitting test result data to the host terminal;

A pattern sequence controller which stores the pattern data in a pattern memory and controls generation of a test pattern during a memory test;

A pattern generator extracting pattern data from the pattern memory under the control of the pattern sequence controller and generating a test pattern for a memory test;

A pin data selector for selecting an output channel of a test pattern generated in the pattern generator;

And a formatter for converting the format of the pattern signal output from the pin data selector and transmitting the converted format signal to the pattern interface means.

In the above, the pattern generator,

A comparator for comparing the expected data stored in the pattern memory or the vector memory with the read data read from the device under test and generating a signal as a result of the comparison;

The apparatus may further include a failure memory for storing a comparison result signal generated by the comparator.

The pattern interface means in the above,

It comprises a plurality of multiple interfacers for testing a plurality of storage or memory or LSI at the same time.

In the above, the multi interface device,

A plurality of interfaces to correspond to the interface of the storage, memory, or LSI; and selecting one of the plurality of interfaces according to an interface selection signal corresponding to a storage interface in the embedded processor to select one of the plurality of interfaces and the storage, memory, or LSI; It is characterized by the interface.

In the above, the multi interface device,

An Advanced Host Controller Interface (AHCI) device for interfacing command data generated in the embedded processor;

A Direct Memory Access (DMA) device for interfacing write data generated in the embedded processor;

A Serial-ATA (SATA) interface unit supporting a Serial-ATA (SATA) interface between the advanced host controller interface device and the direct memory access device and the device under test;

A Serial Attached SCSI (SAS) interfacer for supporting a Serial Attached SCSI (SAS) interface between the advanced host controller interface and the direct memory accessor and the device under test;

A PCIe express (PCIe) interfacer supporting the PCIe interface between the advanced host controller interface and the direct memory accessor and the device under test;

The test target device and the embedded processor may be selected by selecting any one of the Serial-ATA (SATA) interface, the Serial Attached SCSI (SAS) interface device, and the PCIe Express (PCIe) interface device according to the interface selection signal generated by the embedded processor. It characterized in that it comprises a multiplexer (multiplexer) for connecting.

In the synchronous adjustment means,

When the test object is a memory or LSI, it characterized in that it comprises a plurality of synchronization controller for adjusting the synchronization so that the value of the test pattern output from each channel of the test control means is changed at the same time.

According to the present invention, by adding a function to test the memory or LSI to the storage tester, there is an advantage that can test the memory or LSI at high speed without additional cost.

In addition, by adding a simple function to the storage tester according to the present invention can test the memory or LSI at high speed, there is an advantage to improve the function of the storage tester.

1 is a schematic configuration diagram of a conventional solid state drive test apparatus,
2 is a configuration of a preferred embodiment of a high speed memory test apparatus in the solid state drive tester according to the present invention;
3 is a configuration diagram of another embodiment of a high speed memory test apparatus in the solid state drive tester according to the present invention;
4 is an embodiment configuration diagram of a pattern generator in the present invention,
5 is a configuration diagram of an embodiment of the pattern interface means in the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

2 is a block diagram illustrating a preferred embodiment of a high speed memory test apparatus in the solid state drive tester according to the present invention. The host terminal 110, the network 120, the test control unit 130, the memory 140, and the synchronization adjusting unit may be described. It consists of 160. In FIG. 2, reference numeral 200 denotes a memory or LSI under test.

3 is a configuration diagram of another embodiment of a high speed memory test apparatus in the solid state drive tester according to the present invention, which includes a host terminal 110, a network 120, a test control unit 130, a memory 140, and a synchronization adjusting unit. It consists of 160. In FIG. 3, reference numeral 300 denotes a storage unit under test.

The difference between FIG. 2 and FIG. 3 differs only in whether the test object is storage, memory, or LSI. When the test object is the memory and the LSI, the synchronization adjusting means 160 operates. In contrast, when the test object is the storage, the synchronization adjusting means 160 bypasses the test pattern and the read data without any action. .

Hereinafter, for convenience of description, the description will be given with reference to FIGS. 2 and 3.

The host terminal 110 serves to receive a test condition for testing the storage or memory or the LSI from the user. When the test target is the memory or the LSI, the host terminal 110 transmits the pattern data to the test control means 130, and the network 120 is responsible for the data interface between the host terminal 110 and the test control means 130.

The memory 140 includes a program for testing an SSD and serves as a data storage device for storing pattern data for generating a test pattern and data generated during the SSD test during the storage test.

The test control unit 130 generates a test pattern corresponding to a test condition from the host terminal 110 in the case of a storage test to test the storage, and a pattern transmitted from the host terminal 110 in the case of a memory and an LSI test. A test pattern for testing the memory or LSI is generated based on data to test the memory or LSI.

The test control unit 130 may include a device for interfacing user information, a device for interfacing the storage or memory or an LSI, a device for generating a test pattern and controlling a test, and a device for processing failure data generated during a test. And it is desirable to implement a device that stores the failure data separately in one chip using a field programmable gate array (FPGA).

Well-known test control means 130 includes a communication interface unit 131 for interfacing with the host terminal 110; A vector memory 134 for receiving and storing a pattern for testing an LSI from the host terminal 110 and outputting vector data when the LSI is tested; Pattern data transmitted from the host terminal 110 is stored in an internal memory for testing the memory and the LSI, and a test pattern is generated and output from the pattern data stored in the internal memory when the memory is tested. A pattern generator 133 for outputting the vector data output from the vector memory 134 as a test pattern during the LSI test; An embedded processor 132 for controlling pattern generation of the pattern generator 133 for storage, memory, and LSI testing; Under the control of the embedded processor 132, the test pattern generated by the pattern generator 133 is transmitted to storage or memory or LSI, and the pattern generator 133 reads data read from the storage or memory or LSI. It is preferred to include a pattern interface means 135 to interface to.

The pattern generator 133 reads data from the storage, memory, or LSI, compares the expected data with pre-stored expected data, determines whether the failure occurs, stores failure information generated when the failure occurs, and stores the failure information when the test is finished. It is preferable to transmit to the host terminal 111.

More preferably, as shown in FIG. 4, the pattern generator 133 receives the register value and the pattern data transmitted from the host terminal 110 and transmits test result data to the host terminal 110. An interface device 133a; A pattern sequence controller (133b) for storing the pattern data in a pattern memory (133c) and controlling generation of a test pattern during a memory test; A pattern generator (133d) for extracting pattern data from the pattern memory (133c) and generating a test pattern for a memory test under the control of the pattern sequence controller (133b); A pin data selector (133e) for selecting an output channel of the test pattern generated in the pattern generator (133d); A formatter 133f converts the format of the pattern signal output from the pin data selector 133e and transmits the format of the pattern signal to the pattern interface unit 135.

In addition, the pattern generator 133 compares the expected data (write data or vector data) stored in the pattern memory 133c or the vector memory 134 with read data (read data) read from the device under test. A comparator 133g for generating a signal as a result of the comparison; And a failure memory 133h for storing the comparison result signal generated in the comparator 133g.

In addition, the pattern interface means 135 includes a plurality of multiple interfacers 141 to 141 + N for simultaneously testing a plurality of storage or memory or LSIs, and a plurality of multiple interfacers 141 to 141 + N. Includes a plurality of interfaces to correspond to the interface of the storage, memory, or LSI, and selects any one of the plurality of interfaces according to an interface selection signal corresponding to a storage interface in the embedded processor 132. Interface with memory or LSI. Here, since each of the multiple interface units constituting the multiple interface units 141 to 141 + N has the same internal configuration and operation, only one multi interface unit 141 will be described below for convenience of description. .

As shown in FIG. 5, the multi-interfacer 141 includes an advanced host controller interface (AHCI) device 141a for interfacing command data generated by the embedded processor 132; A direct memory access (DMA) device 141b for interfacing write data generated by the embedded processor 132; A Serial-ATA (SATA) interface (141c) for supporting a Serial-ATA (SATA) interface between the advanced host controller interfacer (141a) and the direct memory accessor (141b) and the device under test; A Serial Attached SCSI (SAS) interfacer (141d) for supporting a Serial Attached SCSI (SAS) interface between the advanced host controller interfacer (141a) and the direct memory accessor (141b) and the device under test; A PCIe interface (PCIe) interfacer (141e) supporting a PCIe interface (PCIe) interface between the advanced host controller interfacer (141a) and the direct memory accessor (141b) and the device under test; Among the serial-ATA (SATA) interface device 141c, the SAS (Serial Attached SCSI) interface device (141d), and the PCIe (PCI express) interface device (141e) according to the interface selection signal generated by the embedded processor (132). It includes a multiplexer (141f) for selecting any one to connect the device under test and the embedded processor (132).

In addition, when the test target is a memory or an LSI, the synchronization adjusting unit 160 adjusts the synchronization so that the value of the test pattern output from each channel of the test control unit 130 is changed at the same time. It is preferable to include the regulator (161 ~ 160 + N).

In the solid state drive tester according to the present invention configured as described above, the high-speed memory test apparatus includes a plurality of test devices for testing a device under test (storage, memory, LSI) on a single board using an FPGA, and thus the overall test. It reduces the size of the device, minimizes power consumption, and solves the heating problem that occurs when multiple devices are driven by a single chip drive.

By adding a simple feature for testing memory or LSI to a test device that tests storage, a device such as memory or LSI can be tested at high speed using a test device that tests storage at no additional cost.

In more detail, when the device under test is a memory or an LSI, the user connects to the test target 200 to test the solid state drive tester and inputs a test condition through the host terminal 110. . In this case, the test condition may include an interface selection signal for interfacing with the test object, and a register value and pattern data.

The test condition of the user input through the host terminal 110 is transmitted to the one-chip test control unit 130 via the network 120.

The communication interface 131 of the test control unit 130 receives the test condition input by the user through the network 120 and transmits the test condition to the embedded processor 133. When the test condition is input by the user, the embedded processor 133 transmits the pattern data to the pattern generator 133 and stores the pattern data. When the test command is received, the embedded processor 133 operates the pattern generator 133 to generate a test pattern. do. Here, the pattern generator 133 may be implemented by an algorithm pattern generator (ALPG).

For example, the pattern generator 133 receives the pattern data through the interface device 133a, and the pattern sequence controller 133b sets a register value and stores the received pattern data in the pattern memory 133c.

After storing the pattern data in each register of the pattern generator 133 and the pattern memory 133c, the pattern sequence controller 133b sequentially addresses the pattern memory 133c in accordance with a test command to designate the pattern signal. Data is passed to the pattern generator 133d. At this time, the pattern sequence controller 133b receives the opcode and openrand from the pattern memory 133c and performs the necessary instructions (NOP, JUMP, CALL, RETURN, etc.).

The pattern generator 133d receives the pattern data from the pattern memory 133c and generates various signals (Address, data, command, etc.) for testing the memory.

The signals for the memory test generated as described above are transferred to the pin data selector 133e, and the pin data selector 133e selects a channel so that the signal generated by the pattern generator 133d can be selected as a desired channel. In this case, the pin data selector 133e may arbitrarily set an attribute of a channel output to the test target in order to support various test boards (TBs).

The pattern signal generated by the pattern generator 133d is transmitted to the formatter 133f through the pin data selector 133e, and the formatter 133f transmits the transmitted pattern signal to RZ (Return-to-zero) or NRZ ( Non-return-to-zero) or the like, and transmits write data to the pattern interface means 135.

Also, when the test target is the LSI, the pattern sequence controller 133b reads the vector data stored in the vector memory 134 by designating the address of the vector memory 134 to read the pin data selector 133e. This allows the vector data to be output to the desired channel. As in the memory test, the vector data passing through the pin data selector 133e is generated in the desired format in the formatter 133f and then transferred to the pattern interface means 135.

The interface selection signal is applied from the embedded processor 132 to the multiplexer 141f of the multiple interface 141 of the pattern interface means 135, and the multiplexer 141f receives a plurality of interfaces (SATA) according to the applied interface selection signal. , SAS, PCIe). That is, the interface corresponding to the interface of the memory or LSI under test is selected.

Afterwards, the command data output for testing by the embedded processor 132 is input to the SATA interface 141c, the SAS interface 141d, and the PCIe interface 141e through the advanced host controller interface 141a.

In addition, the write data output from the embedded processor 132 may be transferred to the SATA interface 141c, the SAS interface 141d, and the PCIe interface 141e through a direct memory access (DMA) device 141b. Each is input.

In addition, the pattern data generated by the pattern generator 133 is also input to the multiplexer 141f.

In this state, the command data and the write data output from the embedded processor 132 are input to each interface device, and the multiplexer 141f selects only one interface device according to the interface selection signal. Thereafter, command data, write data, and pattern data input to the selected interface unit are output to the test target.

The test data output to the test target is input to the synchronization controller 161 of the synchronization controller 160, and the synchronization controller 161 synchronizes the values of the respective channels (pattern data) at the same time. . For example, the synchronization controller 161 is made of a delay element to delay the timing so that the timing of each output changes. The delay value of the synchronization controller is preferably set such that the timing of each output channel is changed at the same time point through timing calibration.

The pattern data and the command data through the sync controller 161 are recorded in the memory or the LSI which is the test target 200.

Thereafter, the data recorded in the memory or the LSI, which is the test target 200, is read, and the read data is then controlled by the test controller 130 in a state in which the timing of the channel is synchronized by the sync controller in the sync controller 160. To the pattern interface means 135.

Read data is transferred to the multiplexer 141 in the pattern interface means 135 to the multiplexer 141f in the reverse order of the configuration as shown in Fig. 5, and again the SATA interface 141c corresponding to the interface of the memory or LSI. ) Or response data for command data is transmitted to the pattern generator 133 through the AHCI device 141a through the interface device of either the SAS interface device 141d or the PCIe interface device 141e, and the read data (read). Data) is transferred to the pattern generator 133 via a DMA 141b.

The comparator 133g of the pattern generator 133 compares the read data with the expected data stored in the vector memory or the pattern memory, and if it is the same, transmits a determination signal to the failed memory 133h that is the same, and reads the data and the expectation. If the data are not the same, a failure signal is generated and transferred to the failure memory 133h.

The failure memory 133h stores the transmitted test result signal, and transmits a test result signal to the embedded processor 132 through the interface 133a when the test for the test target is completed.

The embedded process 132 outputs a test result signal to the network 120 through the communication interface unit 131, and the test result signal is transmitted to and displayed on the host terminal 110 through the network 120. The test terminal of the test target can be easily confirmed through the host terminal 110.

Herein, the present invention can reduce the burden on the embedded processor 132 by processing the test target failure in the pattern generator 133 separately from the embedded processor 132 instead of performing the failure process in the embedded processor 132. This can shorten the test time of the test target.

On the other hand, the present invention is to test the storage through the configuration as shown in Figure 3, if the test target is not the memory or LSI as described above.

The configuration shown in FIG. 2 and the configuration of FIG. 3 are the same, and when the test target is the storage, the test processor generates a test pattern corresponding to the test condition without using the pattern generator 133 and generates a pattern of the pattern interface. Forward to 135.

The pattern interface unit 135 outputs a test pattern through the multiple interface unit 141 as shown in FIG. 5, and the test pattern is output to the storage 301 by bypassing the synchronization adjusting unit 160. The test pattern is recorded. For example, when the test target is storage, data does not need to be output at the same time point of each channel, so that the synchronous adjustment means does not work.

Thereafter, the read data read from the storage 301 is bypassed to the synchronization adjusting means 160 as it is, and then transferred to the multi interface unit 141 of the pattern interface unit 135, and in the multi interface unit 141. After the processing, it is transferred to the pattern generator 133 through the embedded processor 132.

The comparator 133g of the pattern generator 133 compares the read data with the expected data obtained from the embedded processor 132, and if it is the same, transmits a determination signal to the failed memory 133h that is the same, and compares the read data with the read data. If the expected data is not the same, a failure signal is generated and transferred to the failure memory 133h.

The failure memory 133h stores the transmitted test result signal, and transmits a test result signal to the embedded processor 132 through the interface 133a when the test for the test target is completed.

The embedded process 132 outputs a test result signal to the network 120 through the communication interface unit 131, and the test result signal is transmitted to and displayed on the host terminal 110 through the network 120. The test result of the test target (storage) can be easily confirmed through the host terminal 110.

The present invention described above can test a memory or LSI at a high speed without additional cost by adding a function to test a memory or LSI to a storage tester, and add a simple function to the storage tester at a high speed. By testing, you can improve the functionality of your storage tester.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims and their equivalents. Of course, such modifications are within the scope of the claims.

110 ... Host terminal
120 ... network
130 ... Test control means
132 ... Embedded processor
133 ... Pattern generator
134 ... Vector memory
135 ... Pattern interface means
160 ... Synchronous control
161 ... Synchronous regulator

Claims (10)

A host terminal for receiving a test condition for a storage test from a user;
Test control means for generating a test pattern corresponding to a test condition input from the host terminal to test the storage;
Wherein the test control means comprises:
A communication interface unit for interfacing with the host terminal;
A vector memory configured to receive and store a pattern for testing storage from the host terminal and to output vector data when the storage is tested;
A pattern generator for storing pattern data transmitted from the host terminal in an internal memory for testing the storage, and generating and outputting a test pattern from the pattern data stored in the internal memory when the storage is tested;
An embedded processor configured to control pattern generation for a storage test in the pattern generator;
And a pattern interface means for transmitting a test pattern generated in the pattern generator to storage under the control of the embedded processor and interfacing read data read from the storage to the pattern generator. High speed memory tester.
The method according to claim 1, wherein the test control means,
Field Programmable Gate Array (FPGA) includes a device for interfacing user information, a device for interfacing the storage, a device for generating a test pattern and controlling a test, a device for processing failure data generated during a test, and a device for storing failure data separately. A high-speed memory test apparatus in a solid state drive tester, characterized in that consisting of one chip using).
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Read the data from the storage to compare with the expected data stored in advance to determine whether the failure, failure information generated when the failure, and when the test is completed, the solid state characterized in that for transmitting the stored failure information to the host terminal High speed memory tester in drive tester.
The method according to claim 4, The pattern generating unit,
An interface unit for receiving register values and pattern data transmitted from the host terminal and transmitting test result data to the host terminal;
A pattern sequence controller configured to store the pattern data in a pattern memory and to control generation of a test pattern in a storage test;
A pattern generator extracting pattern data from the pattern memory under the control of the pattern sequence controller and generating a test pattern for a storage test;
A pin data selector for selecting an output channel of a test pattern generated in the pattern generator;
And a formatter for converting a format of the pattern signal output from the pin data selector and transferring the format of the pattern signal to the pattern interface means.
The method according to claim 5, The pattern generation unit,
A comparator for comparing the expected data stored in the pattern memory or the vector memory with the read data read from the device under test and generating a signal as a result of the comparison;
And a failure memory for storing the comparison result signal generated by the comparator.
The method according to claim 1, wherein the pattern interface means,
A high speed memory test apparatus in a solid state drive tester, characterized in that it comprises a plurality of multiple interfaces for testing a plurality of storage at the same time.
The method according to claim 7, wherein the multiple interface unit,
And a plurality of interfaces to correspond to the interfaces of the storage, and selecting one of the plurality of interfaces according to an interface selection signal corresponding to a storage interface in the embedded processor to interface with the storage. High speed memory tester in drive tester.
The method of claim 8, wherein the multiple interface unit,
An Advanced Host Controller Interface (AHCI) device for interfacing command data generated in the embedded processor;
A Direct Memory Access (DMA) device for interfacing write data generated in the embedded processor;
A Serial-ATA (SATA) interface unit supporting a Serial-ATA (SATA) interface between the advanced host controller interface device and the direct memory access device and the device under test;
A Serial Attached SCSI (SAS) interfacer for supporting a Serial Attached SCSI (SAS) interface between the advanced host controller interface and the direct memory accessor and the device under test;
A PCIe express (PCIe) interfacer supporting the PCIe interface between the advanced host controller interface and the direct memory accessor and the device under test;
The test target device and the embedded processor may be selected by selecting any one of the Serial-ATA (SATA) interface, the Serial Attached SCSI (SAS) interface device, and the PCIe Express (PCIe) interface device according to the interface selection signal generated by the embedded processor. A high speed memory test device in a solid state drive tester, characterized in that it comprises a multiplexer (multiplexer) to connect.

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