KR101406040B1 - Method for manufacturing array substrate for liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device capable of improving driving characteristics of a thin film transistor.

Particularly, the impurity amorphous silicon layer according to the present invention includes the steps of: depositing the impurity amorphous silicon layer in a mixed gas atmosphere of SiH ₄ and PH ₃ in a process chamber of a plasma chemical vapor deposition apparatus; Subjecting the impurity amorphous silicon layer to an H ₂ plasma treatment; And then performing a PH ₃ plasma treatment on the plasma-treated impurity amorphous silicon layer.

The impurity amorphous silicon layer fabricated by such a process can improve the contact resistance with the source and drain electrodes, thereby improving the driving characteristics of the thin film transistor.

Description

[0001] The present invention relates to a method of fabricating an array substrate for a liquid crystal display device,

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device capable of improving driving characteristics of a thin film transistor.

Generally, the driving principle of a liquid crystal display utilizes the optical anisotropy and polarization property of a liquid crystal. Since the liquid crystal has a long structure, the liquid crystal has directionality in the arrangement of molecules, and an electric field is artificially applied to the liquid crystal, Can be controlled.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal due to optical anisotropy, so that image information can be expressed.

Currently, active matrix liquid crystal display (AM-LCD), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, has been receiving the most attention because of its excellent resolution and video realization capability.

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display device.

As shown in the figure, a gate wiring 20 is formed in one direction on a substrate 10, and a data wiring 30 that defines a pixel region P in a direction perpendicular to the gate wiring 20 is formed.

A thin film transistor T is formed at a point of intersection of the gate line 20 and the data line 30.

The thin film transistor T includes a gate electrode 25 extending from the gate wiring 20, a semiconductor layer (not shown) located on top of the gate electrode 25, A source electrode 32 extending from the source electrode 32 and a drain electrode 34 spaced from the source electrode 32.

The semiconductor layer includes an active layer 40 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities.

A pixel electrode 70 which is in contact with the drain electrode 34 through a drain contact hole CH1 exposing a part of the drain electrode 34 corresponds to the pixel region P. [

Hereinafter, a conventional method of manufacturing an array substrate for a liquid crystal display will be described with reference to the accompanying drawings.

2A to 2E are cross-sectional views showing the process of cutting along the line II-II in FIG.

2A, a step of defining a switching region S and a pixel region P on the substrate 10 is proceeded. (Al), an aluminum alloy (AlNd), molybdenum (Mo), tungsten (W), chromium (Cr), or the like on the substrate 10 on which the plurality of regions S and P are defined. A gate metal layer (not shown) is formed and patterned to form a gate wiring (20 in FIG. 1) and a gate electrode 25 extending in the gate wiring in one direction.

Next, a gate insulating film 45 is formed on the entire upper surface of the substrate 10 on which the gate electrode 25 and the gate wiring are formed, with one selected from the group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) .

2B, a pure amorphous silicon layer 40a made of pure amorphous silicon is formed on the substrate 10 having the gate insulating film 45 formed thereon. At this time, the pure amorphous silicon layer 40a is formed in the process chamber of the plasma chemical vapor deposition apparatus through the H ₂ plasma process after the deposition process in the SiH ₄ atmosphere.

Subsequently, an impurity amorphous silicon layer 41a is formed on the substrate 10 on which the pure amorphous silicon layer 40a is formed. The doping amorphous silicon layer 41a is doped in a mixed gas atmosphere of SiH ₄ and PH ₃ in the process chamber of the plasma chemical vapor deposition apparatus, and the H ₂ plasma treatment is performed in a subsequent process.

Next, as shown in FIG. 2C, when the pure amorphous silicon layer 40a (FIG. 2B) and the impurity amorphous silicon layer 41a (FIG. 2B) are patterned, the active layer 40 And an ohmic contact layer 41 are sequentially stacked. The active layer 40 and the ohmic contact layer 41 form a semiconductor layer 42.

A conductive metal group such as molybdenum (Mo), aluminum (Al), aluminum alloy (AlNd), and chromium (Cr) is formed on the substrate 10 on which the semiconductor layer 42 is formed, (30 in FIG. 1) perpendicularly intersecting with the gate wiring, and source and drain electrodes (not shown) extending in the data wiring and spaced apart from each other by a predetermined distance. The source and drain metal layers (32, 34) are formed.

At this time, the ohmic contact layer 41 exposed in the interval between the source and drain electrodes 32 and 34 is patterned to be divided into two sides, and exposed to the lower part of the ohmic contact layer 41 separated to both sides. And then uses this portion as a channel (ch).

Thus, the thin film transistor T including the gate electrode 25, the active and ohmic contact layers 40 and 41, and the source and drain electrodes 32 and 34 can be manufactured through the above-described process.

As shown in Figure 2e, the inorganic insulating material group including the data line and source and drain electrodes (32, 34) is a silicon nitride (SiNx) and silicon oxide (SiO ₂₎ to the formed substrate 10 is an upper front Or a group of organic insulating materials including an acryl resin and benzocyclobutene (BCB).

Next, when the protective film 55 corresponding to a part of the drain electrode 34 is patterned, a drain contact hole CH1 in which a part of the drain electrode 34 is exposed is formed.

As shown in FIG. 2F, a transparent conductive metal group including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) is formed on a protective film 55 including the drain contact hole CH1 A pixel electrode 70 is formed corresponding to the pixel region P in contact with the drain electrode 34. In this case,

Thus, the conventional array substrate for a liquid crystal display device can be manufactured through the above-described processes.

However, the thin film transistor T manufactured through the above-described process is applied to a high-resolution model because the interface characteristics between the ohmic contact layer 41 and the source and drain electrodes 32 and 34 are poor and the charge mobility is remarkably low. It's a different situation.

In particular, since the above-described charge mobility is directly related to the charging time, when the conventional thin film transistor is applied, it causes various side effects such as hindering the image quality as the resolution and the size become larger.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-described problems and aims to improve driving characteristics of a thin film transistor.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display, including: forming a gate wiring in one direction on a substrate; Forming a gate insulating film on the gate wiring; Forming a pure water and an impurity amorphous silicon layer on the gate insulating film; Performing a PH ₃ plasma treatment on the substrate on which the impurity amorphous silicon layer is formed; Forming active and ohmic contact layers, source and drain electrodes and a data line on the substrate on which the PH ₃ plasma process has been performed; Forming a protective film on the substrate on which the data line and the source and drain electrodes are formed; And forming a pixel electrode in contact with the drain electrode.

At this time, the step of forming the impurity amorphous silicon layer may include doping a mixed gas of SiH ₄ and PH ₃ on the pure amorphous silicon layer in a process chamber of a plasma chemical vapor deposition equipment; Performing an H ₂ plasma treatment; PH ₃ plasma treatment.

Wherein the source and drain electrodes are formed of a selected one of a group of conductive metal materials including aluminum and an aluminum alloy, and the overlapped interface between the ohmic contact layer and the source and drain electrodes is doped with a large amount of PH ₃ .

The pixel electrode is extended to the gate wiring of the previous stage, and the gate wiring of the previous stage is used as a first electrode, and the pixel electrode which overlaps with the first electrode is used as a second electrode, And a storage capacitor having the gate insulating film and the protective film interposed between the overlapped portions of the first and second electrodes as a dielectric layer.

In the present invention, first, the contact resistance between the ohmic contact layer and the source and drain electrodes can be reduced by doping a large amount of PH ₃ on the exposed surface of the ohmic contact layer.

Second, the improvement of the contact resistance described above can improve the driving characteristics of the thin film transistor.

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Hereinafter, a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

The present invention can improve the driving characteristics of the thin film transistor by increasing the doping effect at the interface between the ohmic contact layer and the source and drain electrodes by performing the PH ₃ plasma treatment on the exposed upper surface of the ohmic contact layer .

3 is a plan view showing a unit pixel of an array substrate for a liquid crystal display according to the present invention.

As shown in the drawing, the gate wiring 120 is formed in one direction on the substrate 100, and the data wiring 130 is formed in a direction perpendicular to the gate wiring 120. An area defined by the intersection of the gate wiring 120 and the data wiring 130 is referred to as a pixel area P. [

A thin film transistor T is formed at an intersection of the gate line 120 and the data line 130. The thin film transistor T includes a gate electrode 125 extending from the gate wiring 120 and a semiconductor layer (not shown) on the gate electrode 125. The thin film transistor T extends from the data wiring 130, And a drain electrode 134 spaced apart from the source electrode 132. The source electrode 132 and the drain electrode 134 are formed on the same substrate.

The semiconductor layer (not shown) includes an active layer 140 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) .

The first amorphous pattern 174 and the second amorphous pattern (not shown) extending in the active layer 140 and the ohmic contact layer extend to the bottom of the data line 130, respectively. In particular, the first amorphous pattern 174 protrudes outside the data line 130.

The pixel electrode 170 is formed to correspond to the pixel region P in contact with the drain electrode 134 through the drain contact hole CH2 exposing a part of the drain electrode 134. [ The pixel electrode 170 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

The pixel electrode 170 is extended to overlap with the gate line 120 at the previous stage so that the gate line 120 at the previous stage serves as a first electrode and the pixel electrode 170 overlapped with the first electrode, And a storage capacitor Cst constituted by a dielectric layer formed in the overlapping space between the first and second electrodes as a dielectric layer.

Hereinafter, a manufacturing method of an array substrate for a liquid crystal display according to the present invention will be described in detail.

4A to 4I are cross-sectional views showing the process of cutting along the line IV-IV in FIG. 3 according to a process sequence.

4A is a process sectional view showing a first mask process step.

The step of defining the switching region S, the pixel region P, the data region D and the gate region G is proceeded on the substrate 100 as shown in Fig. 4A. (Al), an aluminum alloy (AlNd), molybdenum (Mo), tungsten (W), chromium (Cr), or the like on the substrate 100 on which the plurality of regions S, P, D, A gate metal layer (not shown) is formed by depositing one or more selected metal groups and patterned to form a gate wiring 120 in one direction and a gate electrode 125 extending from the gate wiring 120 .

Next, a gate insulating layer 145 is formed on the entire surface of the substrate 100 on which the gate electrode 125 and the gate wiring 120 are formed, as one selected from the group of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) .

Figures 4B-4G are process cross-sectional views illustrating the second mask process step.

4B, a pure amorphous silicon layer 140a made of pure amorphous silicon (a-Si: H) is formed on the substrate 100 having the gate insulating layer 145 formed thereon. At this time, the pure amorphous silicon layer 140a is deposited in the SiH ₄ atmosphere in the process chamber of the plasma chemical vapor deposition apparatus, and is formed through the H ₂ plasma process as a subsequent process.

Subsequently, as shown in FIG. 4C, an impurity amorphous silicon layer 141a is formed on the substrate 100 on which the pure amorphous silicon layer 140a is formed. The impurity amorphous silicon layer 141a is formed in the process chamber of the plasma chemical vapor deposition apparatus through a doping process in a mixed gas atmosphere of SiH ₄ and PH ₃ and then through H ₂ plasma treatment.

4D, a plasma process using PH ₃ is further performed on the above-described H ₂ plasma-treated impurity amorphous silicon layer 141a.

In the present invention, a large amount of PH ₃ is doped at the exposed interface of the impurity amorphous silicon layer 141 a through the PH ₃ plasma treatment. That is, after the impurity amorphous silicon layer 141a is formed, the PH ₃ plasma process proceeds, and thus the doping efficiency can be increased without affecting the deposition thickness.

As shown in Figure 4e, a PH ₃ plasma treatment the impurity amorphous silicon layer (141a) the upper part of the aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo) and chromium (Cr) and of the conductive metal group is selected such One or more of these are deposited to form the source and drain metal layers 175.

A photoresist is coated on the substrate 100 on which the source and drain metal layers 175 are formed to form a photosensitive layer 180. The photosensitive layer 180 is formed on the upper portion of the photosensitive layer 180, A halftone mask HTM composed of a transmissive portion T2 and a blocking portion T3 is aligned.

The halftone mask HTM functions to form a semitransparent film on the transflective portion T2 to lower the intensity of light or to reduce the amount of light transmitted thereby allowing the photosensitive layer 180 to be incompletely exposed. In this case, a slit mask may be used to adjust the amount of light transmitted through the transflective portion T2 in addition to the halftone mask HTM.

The blocking portion T3 functions to completely block the light and the transmissive portion T1 transmits light and functions to allow the photosensitive layer 180 exposed to light to be chemically changed to be completely exposed do.

At this time, in the switching region S, the transflective portion T 2 is disposed between the blocking portions T 3 on both sides, the blocking portion T 3 is formed in the data region D, do.

As shown in FIG. 4F, when the process of exposing and developing the halftone mask (HTM in FIG. 4E) and the upper portion spaced apart from the halftone mask (HTM in FIG. 4E) The corresponding photosensitive layer (180 in FIG. 4E) has first and second photosensitive patterns 181 and 182 having no height change, and a photosensitive layer (180 in FIG. 4E) A third photosensitive pattern 183 whose height is reduced to about half is formed. 4E) corresponding to the data area D is formed, and the photosensitive layer (180 in FIG. 4E) of the entire region except for the fourth photosensitive pattern 184 And the source and drain metal layers 175 under the exposed portions are exposed.

Next, using the first to fourth photosensitive patterns 181, 182, 183, and 184 as a mask and patterning the exposed source and drain metal layers 175, The source and drain metal patterns 174 corresponding to the data region D, and the data line 130 corresponding to the data region D, respectively. The source and drain metal patterns 174 are electrically connected to the data lines 130.

Next, the exposed impurity amorphous silicon layer (141a in FIG. 4E) and the underlying pure amorphous silicon layer (140a in FIG. 4E) are moved in the process chamber and the impurity and pure amorphous silicon layer The active layer 140 and the ohmic contact layer 141 formed to have the same width as the source and drain metal patterns 174 and the data line D The semiconductor pattern 173 including the first and second amorphous patterns 171 and 172 is formed to have the same width as the first and second amorphous patterns 171 and 172.

At this time, pure and impurity amorphous silicon layers (140a and 141a in FIG. 4E) in the entire region excluding the active and ohmic contact layers 140 and 141 and the semiconductor pattern 173 are all removed.

The first and second amorphous patterns 171 and 172 extend to the lower portion of the data line 130 with the same material as the active and ohmic contact layers 140 and 141. Here, the semiconductor layer 142 including the active and ohmic contact layers 140 and 141 is referred to as a semiconductor layer.

Next, ashing of the first to fourth photosensitive patterns 181, 182, 183, and 184 is performed, the first, second, and fourth photosensitive patterns 181, 182, and 184 The thickness of the first and second photosensitive patterns 181 and 182 is reduced to about half and the third photosensitive pattern 183 of FIG. 4E is controlled to expose the source and drain metal patterns 172 between the first and second photosensitive patterns 181 and 182.

Second, and fourth photosensitive patterns 181, 182, and 184 covering the data lines 130 and both ends F of the source and drain metal patterns 174 in the course of the above-described ashing process, And portions of the first and second photosensitive patterns 181 and 182 on opposite sides G of the first and second photosensitive patterns 181 and 182 are removed together.

Next, using the source and drain electrodes 132 and 134 as masks, the ohmic contact layer 141 corresponding to the source and drain electrodes 132 and 134 is patterned and separated in both sides in the dry etching process , The active layer 140 exposed through the separated ohmic contact layer 141 is overexposed and utilized as a channel ch.

At this time, the ohmic contact layer 41 corresponding to the F and G portions is removed together, and the active layer 140 under the active layer 140 is protruded to the outside of the data line 130 and the source and drain electrodes 132 and 134. The gate electrode 125, the semiconductor layer 142, and the source and drain electrodes 132 and 134 constitute a thin film transistor T.

Particularly, since the thin film transistor T according to the present invention has a large amount of PH ₃ doped in the interface of the ohmic contact layer 141, the contact resistance between the ohmic contact layer 141 and the source and drain electrodes 132 and 134 And the driving characteristics of the thin film transistor T can be improved.

Thus, the second mask process step of the present invention is finally completed.

4H is a process sectional view showing a third mask process step.

An inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the data line 130 and the thin film transistor T are formed, A protective film 155 is formed of a selected one or an organic insulating material group including an acrylic resin and benzocyclobutene (BCB).

Next, a protective film 155 corresponding to a part of the drain electrode 134 is patterned to form a drain contact hole CH2 exposing the drain electrode 134. Next, as shown in FIG.

4I is a cross-sectional view illustrating a fourth mask process step.

As shown in FIG. 4I, one selected from a transparent conductive metal group such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is formed on the protective film 155 including the drain contact hole A pixel electrode 170 is formed to correspond to the pixel region P by forming a transparent metal layer (not shown) and patterning the pixel electrode 170 to contact the drain electrode 134.

The pixel electrode 170 is extended to overlap with the gate line 120 at the previous stage so that the gate line 120 at the previous stage serves as a first electrode and the pixel electrode 170 serves as a second electrode, A storage capacitor Cst having a gate insulating film 145 interposed between the first and second electrodes and a protective film 155 as a dielectric layer is formed.

Thus, the array substrate for a liquid crystal display according to the present invention can be manufactured by a four-mask process.

As described above, since the thin film transistor according to the present invention has a large amount of PH ₃ doped in the contact interface between the ohmic contact layer and the source and drain electrodes, it is possible to improve the driving characteristics of the thin film transistor .

Hereinafter, contact resistance between the ohmic contact layer and the source and drain electrodes according to the present invention will be described in detail through comparison and analysis of data.

FIG. 5A is a plan view showing a sample according to an evaluation condition according to the present invention, and FIG. 5B is a cross-sectional view showing one sample of the sample under each evaluation condition.

5A and 5B, samples TP1, TP2, TP3, TP4, TP5, TP6, and TP7 are prepared on the mother substrate 200 according to the first through seventh evaluation conditions. The samples TP1 to TP7 according to the first to seventh evaluation conditions are formed by stacking an ohmic contact layer 241 on the mother substrate 200 and a plurality of source patterns 232 located at the upper portion in contact with the ohmic contact layer 241 And a plurality of drain patterns 234 spaced apart from the plurality of source patterns 232.

The samples TP1 to TP7 according to the first through seventh evaluation conditions have L values of 5, 10, 15, 20, 25, 30, and 35 μm, respectively, which are distances between the source and drain patterns 232 and 234 It is designed with a differential.

Particularly, the interface between the ohmic contact layer 241 and the source and drain patterns 232 and 234 is a state in which the PH ₃ plasma treatment is performed, and the source and drain patterns 232 and 234 are made of an aluminum- .

At this time, as shown in Fig. 5C, the IV characteristics according to the L value of the samples (TP1 to TP7 in Fig. 5A) for the first to seventh evaluation conditions, in particular, the average resistance at V = -0.1 and 0.1 Value is converted into an average resistance regression formula to derive the value of the contact resistance (?) Between the ohmic contact layer and the source and drain patterns.

In this case, the average resistance according to the L value of the samples for each of the first to seventh evaluation points is represented by a regression equation. As the L value increases, the contact resistance (?) Increases.

Particularly, FIG. 6 is a graph comparing resistivity (rho c) values according to PH ₃ plasma non-treatment conditions and treatment conditions after completing the ohmic contact layer.

As shown, PH ₃ plasma when subjected to treatment it can be seen that appear evident difference in the specific resistance (ρc) value of not carried out and, PH ₃ plasma raw condition considerably the specific resistance (ρc) values in the contrast processing conditions . ≪ / RTI > As a result, the resistivity (ρc) was not significantly influenced by the different powers at 150 watt (W) and 450 watt (W) in the same process time (10 seconds).

That is, the resistivity (ρc) during untreated condition 12.02Ωcm ^2, resistivity (ρc) during the drying process is performed under the conditions when the specific resistance between the conducting bars, PH ₃ plasma treatment doeeotneun check 3.08Ωcm ² ohmic contact layer and the source and drain pattern (rho c) is reduced by about 1/4.

Based on the above-described experimental data, the contact resistance between the ohmic contact layer and the source and drain electrodes can be drastically reduced through the PH ₃ plasma treatment, thereby improving the driving characteristics of the thin film transistor.

However, it should be understood that the present invention is not limited to the above-described embodiment, and various changes and modifications may be made without departing from the spirit and scope of the present invention.

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display;

FIGS. 2A to 2E are cross-sectional views of the process, taken along the line II-II in FIG.

3 is a plan view showing a unit pixel of an array substrate for a liquid crystal display according to the present invention.

Figs. 4A to 4I are sectional views of the process, taken along the line IV-IV in Fig.

5A is a plan view showing a sample according to an evaluation condition according to the present invention.

FIG. 5B is a cross-sectional view showing a sample cut out according to the evaluation condition. FIG.

Fig. 5C shows the average resistance according to the L value of the sample for each evaluation condition. Fig.

FIG. 6 is a graph comparing resistance values according to PH ₃ plasma unprocessed conditions and processing conditions after completion of the ohmic contact layer. FIG.

Description of the Related Art [0002]

100: substrate 120: gate wiring

125: gate electrode 140a: pure amorphous silicon layer

141a: impurity amorphous silicon layer 145: gate insulating film

Claims (5)

Forming a gate wiring in one direction on the substrate; Forming a gate insulating film on the gate wiring; Forming a pure water and an impurity amorphous silicon layer on the gate insulating film; Performing a PH ₃ plasma treatment on the substrate on which the impurity amorphous silicon layer is formed; Forming active and ohmic contact layers, source and drain electrodes and a data line on the substrate on which the PH ₃ plasma process has been performed; Forming a protective film on the substrate on which the data line and the source and drain electrodes are formed; Forming a pixel electrode in contact with the drain electrode / RTI > Wherein forming the impurity amorphous silicon layer comprises: Doping a mixed gas of SiH ₄ and PH ₃ on the pure amorphous silicon layer in a process chamber of a plasma enhanced chemical vapor deposition apparatus; And performing H ₂ plasma treatment on the surface of the substrate. delete The method according to claim 1, Wherein the source and drain electrodes are formed of one selected from the group of conductive metal materials including aluminum and an aluminum alloy. The method according to claim 1, Wherein the superimposed interface between the ohmic contact layer and the source and drain electrodes is doped with a large amount of PH ₃ . The method according to claim 1, Wherein the pixel electrode is extended to the gate wiring of the previous stage to make the gate wiring of the front end serve as the first electrode and the pixel electrode which overlaps with the first electrode and serves as the second electrode, And a storage capacitor having the gate insulating film and the protective film interposed between the overlapped portions of the first electrode and the second electrode as a dielectric layer.

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