KR101481667B1 - Light emitting display and driving method thereof - Google Patents

Abstract

The present invention relates to a light emitting display device and a method of driving the same that can maximize a light emission period to prevent a flicker phenomenon.

The light emitting display according to the present invention includes a light emitting element formed in each pixel region defined by a data line to which a data voltage is supplied, first to nth gate lines to which a gate voltage is supplied, and a power supply line to which a driving voltage is supplied, A light emitting display panel having a pixel driver for driving the light emitting element; A gate driver for driving the gate line in a sequence of supplying a high logic gate voltage to the first to n-th gate lines in an odd frame period and an odd frame period; And a data driver for driving the data lines in the order of supplying the data voltages supplied to the first to the n-th horizontal lines in the odd frame period and the odd frame period, Supplies a high-potential voltage to the anode electrode of the light-emitting element in an address period in which a gate voltage of the light-emitting element is supplied, and the pixel driver forms a current path between the first node and the data line in response to the gate voltage of the high logic A first switching transistor; A first storage capacitor formed between the first node and the second node; A driving transistor for adjusting a current flowing between the light emitting element and the low potential voltage source in response to the second node voltage; A second switching transistor forming a current path between the second node and the third node in response to a control voltage supplied to the control line; And a second storage capacitor formed between the first node and the low potential voltage source.

Light emitting display, OLED, luminance, driving voltage, address period

Description

TECHNICAL FIELD [0001] The present invention relates to a light emitting display device and a method of driving the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, and more particularly, to a light emitting display device and a driving method thereof capable of preventing a flicker phenomenon by maximizing a light emitting period.

In an active matrix organic light emitting display device, a plurality of pixels are arranged in a matrix form to display an image. As shown in FIG. 1, each pixel of the organic light emitting display includes an organic light emitting diode (OLED) and a pixel driver 10 that independently drives the OLED. The OLED includes a cathode connected to the pixel driver 10 and a cathode connected to the power source line PL, and an organic layer formed between the anode and the cathode. The pixel driver 10 includes a gate line GL for supplying a scan signal, a data line DL for supplying a data signal, a power supply line PL for supplying a power supply signal, a gate line GL, A switching transistor T1 and a driving transistor T2 connected between a power supply line DL and a power supply line PL and a storage capacitor Cst to drive the light emitting device OLED.

Such an organic light emitting display device is driven by being divided into a non-emission period and a light emission period. The non-emission period is divided into a reset, an initialization, a sampling, and an address period. If such a light emitting period is shorter than the non-light emitting period, the image quality deteriorates. Particularly, when the ratio of the light emission period is 80% or less, a flicker phenomenon occurs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting display device and a method of driving the same that can maximize a light emitting period to prevent a flicker phenomenon.

According to an aspect of the present invention, there is provided a light emitting display including a data line to which a data voltage is supplied, first to nth gate lines to which a gate voltage is supplied, A light emitting display panel having a light emitting element formed at each pixel and a pixel driver for driving the light emitting element; A gate driver for driving the gate line in a sequence of supplying a high logic gate voltage to the first to n-th gate lines in an odd frame period and an odd frame period; And a data driver for driving the data lines in the order of supplying the data voltages supplied to the first to the n-th horizontal lines in the odd frame period and the odd frame period, Supplies a high-potential voltage to the anode electrode of the light-emitting element in an address period in which a gate voltage of the light-emitting element is supplied, and the pixel driver forms a current path between the first node and the data line in response to the gate voltage of the high logic A first switching transistor; A first storage capacitor formed between the first node and the second node; A driving transistor for adjusting a current flowing between the light emitting element and the low potential voltage source in response to the second node voltage; A second switching transistor forming a current path between the second node and the third node in response to a control voltage supplied to the control line; And a second storage capacitor formed between the first node and the low potential voltage source.

According to an aspect of the present invention, there is provided a method of driving a light emitting display including a data line to which a data voltage is supplied, first to nth gate lines to which a gate voltage is supplied, A driving method of a light emitting display device for driving a plurality of pixels having a pixel driving part for driving the light emitting device in a non-emitting period and a light emitting period, the driving method comprising: Driving the gate line by varying the supply order of the gate voltage of the high logic supplied to the first to nth gate lines to the odd frame period and the odd frame period, the supply order of the data voltages supplied to the n horizontal lines is set in the odd frame period and the even frame period Wherein the power supply line supplies a high potential voltage to an anode electrode of the light emitting element during a period in which a gate voltage of a high logic is supplied to the gate lines, A first switching transistor for forming a current path between the first node and the data line in response to a gate voltage of the logic; A first storage capacitor formed between the first node and the second node; A driving transistor for adjusting a current flowing between the light emitting element and the low potential voltage source in response to the second node voltage; A second switching transistor forming a current path between the second node and the third node in response to a control voltage supplied to the control line; And a second storage capacitor formed between the first node and the low potential voltage source.

In the light emitting display according to the present invention, the light emitting elements emit light in the address period and are addressed in the order of the first to nth gate lines GL1, GL2, ..., GLn in the odd frame period, (GLn, GLn-1, ..., GL1) in the reverse of the addressing order of the frame period. Therefore, in the light emitting display device according to the present invention, the average light emission time of each frame becomes equal. As described above, since the light emitting device emits light even during the address period of the light emitting display according to the present invention, the non-emission period is minimized and flicker can be prevented.

In addition, since the conventional switching transistor connected to the drain terminal of the conventional driving transistor can be removed from the power source line, the yield and the aperture ratio can be increased.

In addition, the light emitting display device and the driving method thereof according to the present invention can set the high logic period of the gate voltage of the high logic to improve the image quality.

2 is a block diagram showing a light emitting display device according to the present invention.

2 includes a light emitting display panel 102, a gate driver 106 for driving a gate line GL of the light emitting display panel 102, a data line (not shown) of the light emitting display panel 102 And a timing control unit 108 for controlling the gate driving unit 106 and the data driving unit 104. The timing control unit 108 controls the gate driving unit 106 and the data driving unit 104,

The timing control unit 108 includes a control signal generation unit 110 and a frame memory 112.

The control signal generator 110 drives the gate driver 106 and the data driver 104 using a plurality of synchronous signals H and V and a main clock signal MCLK input through a system And generates a plurality of control signals for controlling the timing. In particular, the control signal generator 110 generates a data transfer control signal DTC for controlling the frame memory 112 and first and second start control signals STR1 and STR2 for controlling the gate driver 106 do.

The frame memory 112 arranges pixel data (R, G, and B Data) input from a system (not shown) and supplies the aligned pixel data to the data driver 106. Specifically, the frame memory 112 aligns the pixel data in the order of the first to the n-th horizontal lines in the odd frame period in response to the data transfer control signal DTC of high logic, and supplies the pixel data to the data driver 106. In response to the low logic data transfer control signal DTC, the pixel data is arranged in order of the n-th to the first horizontal lines in the odd frame period and supplied to the data driver 106.

In response to the first start control signal STR1, the gate driver 106 sequentially supplies the gate voltages of the logic high to the first to nth gate lines GL1 to GLn in the odd frame period. The gate driver 106 sequentially drives the first switching transistors ST1 and ST2 connected to the first to nth gate lines GL1 to GLn in units of the gate lines GL. In response to the second start control signal STR, the gate driver 106 supplies the gate voltage of the high logic to the first to nth gate lines GL1 to GLn inversely during the even frame period. Accordingly, the gate driver 106 drives the first switching transistors ST1 and ST2 connected to the first to nth gate lines GL1 to GLn in units of the gate line GL.

The data driver 104 supplies a data voltage (Vdata) of one horizontal line to the data line DL in a data input period of one horizontal period. In particular, the data driver 104 sequentially supplies the data voltages to the data lines DL in the first to the n-th horizontal lines during the odd frame period, To the data line DL.

The light emitting display panel 102 includes a plurality of pixel cells PXL connected to data lines DL, gate lines GL, a control line CL, a power supply line PL, a low potential voltage (VSS) So that an image is displayed. Here, a driving voltage swinging between the high potential voltage (VDD) and the ground voltage (GND) is supplied to the power supply line. The high potential voltage VDD is supplied to each pixel cell PXL during the address and emission period and the base voltage GND is supplied to each pixel cell PXL during the reset period, the initialization period, and the sampling period.

Each pixel cell PXL includes a light emitting device OLED and a pixel driver 114 driving the light emitting device OLED, as shown in FIG.

The pixel driver 114 includes a plurality of transistors ST1, ST2, DT for controlling on / off timing of the light emitting device OLED, first and second transistors ST1, ST2, DT for maintaining the ON state of the light emitting device OLED for one frame, And second storage capacitors Cst1 and Cst2. The plurality of transistors ST1, ST2, and DT may be PMOS transistors or NMOS transistors. The plurality of transistors ST1, ST2, and DT shown in FIG. 2 are all NMOS transistors, Layer.

The plurality of transistors includes first and second switching transistors ST1 and ST2 and a driving transistor DT.

The first switching transistor ST1 supplies the data signal Vdata from the data line DL to the first node N1 in response to the gate voltage of the high logic from the gate line GL. To this end, the gate terminal of the first switching transistor ST1 is connected to the gate line GL, the source terminal to the data line DL, and the drain terminal to the first node N1.

The second switching transistor ST2 connects the gate electrode and the drain electrode of the driving transistor DT to each other in response to the control voltage Vc from the control line CL to connect the driving transistor DT in a diode form. To this end, the gate terminal of the second switching transistor ST2 is connected to the control line CL, the source terminal to the second node N2, and the drain terminal to the third node N3.

The driving transistor DT controls the amount of current flowing to the light emitting element OLED in response to the voltage on the second node N2. To this end, the gate terminal of the driving transistor DT is connected to the second node N2, the source terminal to the third node N3, and the drain terminal to the low potential voltage source VSS.

The first storage capacitor Cst1 is connected between the first and second nodes N1 and N2. The first storage capacitor Cst1 stably maintains the voltages of the second nodes N1 and N2 and prevents the voltages of the first and second nodes N1 and N2 from being mixed with each other.

The second storage capacitor Cst2 is connected between the low potential voltage (Vss) source and the first node N1. This second storage capacitor Cst2 prevents the voltage of the first node N1 from fluctuating when the first switching transistor ST1 is turned off and the first node N1 is brought into a floating state.

The light emitting device OLED includes an anode electrode connected to the power supply line PL, a cathode electrode connected to the pixel driver 114, and an organic light emitting layer formed between the anode electrode and the cathode electrode. The light emitting device OLED emits light by the current from the driving transistor DT of the pixel driver 114. [

4 is a waveform diagram for explaining a driving method of a light emitting display according to the present invention. 3 will be described with reference to FIG.

Each of the odd frame period and the extra frame period is divided into a reset period T1, an initialization period T2, a sampling period T3, an address period and a light emission period T4, as shown in FIG.

During the reset period T1, the initializing voltage Vini is supplied to the data line DL, the ground voltage GND is supplied to the power source line PL, and the ground voltage GND is supplied to the control line CL , And a gate voltage of low logic is supplied to the gate line GL.

The first and second switching transistors ST1 and ST2 and the driving transistor DT maintain a turn-off state in response to the gate voltage of the low logic and the base voltage. The initializing voltage Vini is precharged to the data line DL so that the initializing voltage Vini is sufficiently charged to the desired voltage level during the initializing period T2.

The third node N3 is turned on by a parasitic capacitor (not shown) of the light emitting device OLED formed between the power supply line PL for maintaining the base voltage and the third node N3 during the reset period T1. Maintains the base voltage.

The initialization voltage Vini is supplied to the data line DL and the gate voltage of the high logic is supplied to the gate line GL at the start point of the initialization period T2, The base voltage GND is supplied.

Accordingly, the first switching transistor ST1 is turned on in response to the gate voltage of the high logic, and the second switching transistor ST2 is turned off in response to the base voltage GND.

The initializing voltage Vini from the data line DL is supplied to the first node N1 through the first switching transistors ST1 turned on so that the first node N1 is charged with the initializing voltage Vini. At this time, since the voltage of the second node N2 is raised by the first storage capacitor Cst1 between the first and second nodes N1 and N2, the driving transistor DT connected to the second node N2, Lt; / RTI > The third node N3 is initialized by supplying the low potential voltage VSS to the third node N3 through the turned-on driving transistor DT.

The voltage charged in the first storage capacitor Cst1 connected to the drain electrode of the first switching transistor ST1 is set to be the same as the voltage charged in the data line DL since the voltage of the base voltage or OV is supplied to the data line DL at the end of the initialization period T2. And is discharged at 0V or a base low voltage on the line DL.

During the sampling period T3, the base voltage is supplied to the power supply line PL, the gate voltage of the high logic is supplied to the gate line GL, and the control voltage Vc is supplied to the control line CL.

Accordingly, the second switching transistor ST2 is turned on in response to the control voltage Vc, and the first switching transistor ST1 is turned on in response to the gate voltage of the high logic.

The gate terminal and the source terminal of the driving transistor DT are connected to each other through the turned-on second switching transistor ST2. That is, since the second and third nodes N2 and N3 are short-circuited by the turned-on second switching transistor ST2, the gate terminal and the source terminal of the driving transistor DT become equal potential, and the driving transistor DT is turned off do. The threshold voltage of the turned-on driving transistor DT is stored in the second and third nodes N2 and N3.

The high potential voltage VDD is supplied to the power supply line PL and the base voltage is supplied to the control line CL during the address and light emission period T4.

During the odd frame period, gate voltages of high logic are sequentially supplied to the first to nth gate lines GL1 to GLn, and the data voltages D1, D2, ..., , DN) are supplied. During the odd-numbered frame period, the gate voltages of high logic are supplied to the first to nth gate lines GL1 to GLn inversely, and the data voltages DN, DN-1,. ..., D1 are supplied.

On the other hand, when the voltage supplied to the power supply line PL swings from the base voltage GND to the high potential voltage VDD, before the gate voltage of the high logic is supplied to the first gate line GL1 in the odd frame period And before the gate voltage of the high logic is supplied to the nth gate line GLn in the even frame period.

Accordingly, the second switching transistor ST2 is turned off in response to the control voltage supplied to the control line CL, and the first switching transistor ST1 is turned on in response to the gate voltage of the high logic. The data voltage is charged to the first node N1 through the turned-on first switching transistor ST1. The voltage of the first node N1 charged with the data voltage and the voltage of the second node N2 connected through the first storage capacitor Cst1 rise by the voltage charged in the first node N1. That is, the data voltage supplied to the first node N1 is increased to the threshold voltage of the driving transistor DT charged during the sampling period in the second node N2. The driving transistors DT are sequentially turned on in the horizontal line unit by the voltage supplied to the second node N2. The turned-on driving transistor ST generates a driving current, and the light emitting element OLED emits light with a luminance corresponding to the magnitude of the driving current.

As described above, the light emitting display according to the present invention differs in the scan order of the odd frame period and the excellent frame period in order to prevent the light emitting device from emitting light even during the address period, . In other words, in the odd frame period, the first to nth gate lines GL1, GL2, ..., GLn are addressed, and in the even frame period, the addresses GLn, GLn-1,. ..., GL1), the average light emission time of each frame becomes equal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a circuit diagram showing a pixel of a conventional light emitting display device.

2 is a block diagram showing a light emitting display device according to the present invention.

3 is a circuit diagram showing one pixel shown in Fig.

4 is a waveform diagram for explaining a driving method of a light emitting display according to the present invention.

Description of the Related Art

102: light emitting display panel 104:

106: gate driver 108: timing controller

110: control signal generator 112: frame memory

114:

Claims (10)

A light emitting element formed in each pixel region defined by a data line to which a data voltage is supplied, first to nth gate lines to which a gate voltage is supplied, and a power supply line to which a driving voltage is supplied; A light emitting display panel; A gate driver for driving the gate line in a sequence of supplying a high logic gate voltage to the first to n-th gate lines in an odd frame period and an odd frame period; And a data driver for driving the data lines in the order of supplying the data voltages supplied to the first to the n-th horizontal lines in the odd frame period and the odd frame period, The power supply line supplies a high potential voltage to the anode electrode of the light emitting element in an address period in which a gate voltage of a high logic is supplied to the gate lines, The pixel driver A first switching transistor which forms a current path between the first node and the data line in response to the gate voltage of the high logic; A first storage capacitor formed between the first node and the second node; A driving transistor for adjusting a current flowing between the light emitting element and the low potential voltage source in response to the second node voltage; A second switching transistor forming a current path between the second node and the third node in response to a control voltage supplied to the control line; And a second storage capacitor formed between the first node and the low potential voltage source. The method according to claim 1, Wherein the gate driver sequentially supplies the gate voltages of the high logic to the first to n < th > gate lines during the odd frame period, The gate voltage is supplied, Wherein the data driver sequentially supplies the data voltages to the first to the n-th horizontal lines during the odd frame period and supplies the data voltages to the first to the n-th horizontal lines inversely during the odd frame period . 3. The method of claim 2, The power supply line swings from 0V or the base voltage to the high potential voltage before supplying the gate voltage of the high logic to the n-th gate line in the even frame period in the odd frame period Emitting display device. 3. The method of claim 2, A frame memory for storing data supplied to the data driver in frame units; And a control signal generator for generating a data transmission control signal for controlling the frame memory to transmit the data stored in the frame memory differently from the odd frame and the even frame period. delete A light emitting element formed in each pixel region defined by a data line to which a data voltage is supplied, first to nth gate lines to which a gate voltage is supplied, and a power supply line to which a driving voltage is supplied; Emitting period and a light-emitting period, the method comprising: The light- Driving the gate line by varying the supply order of the gate voltage of the high logic supplied to the first to the n-th gate lines to the odd frame period and the excellent frame period, Driving the data lines by varying the supply order of the data voltages supplied to the nth horizontal line in the odd frame period and the odd frame period, Wherein the power supply line supplies a high potential voltage to the anode electrode of the light emitting element during a period in which a gate voltage of high logic is supplied to the gate lines, The pixel driver A first switching transistor which forms a current path between the first node and the data line in response to the gate voltage of the high logic; A first storage capacitor formed between the first node and the second node; A driving transistor for adjusting a current flowing between the light emitting element and the low potential voltage source in response to the second node voltage; A second switching transistor forming a current path between the second node and the third node in response to a control voltage supplied to the control line; And a second storage capacitor formed between the first node and the low potential voltage source. The method according to claim 6, The step of driving the gate line and the data line Sequentially supplying the gate voltages of the high logic to the first to nth gate lines during the odd frame period and sequentially supplying the data voltages to the first to the nth horizontal lines during the odd frame period; Supplying the gate voltage of the high logic inversely to the first to nth gate lines during the odd frame period and supplying the data voltage inversely to the first to the nth horizontal lines during the odd frame period And a driving method of the light emitting display device. 8. The method of claim 7, The power supply line swings from 0V or the base voltage to the high potential voltage before supplying the gate voltage of the high logic to the n-th gate line in the even frame period in the odd frame period And a driving method of the light emitting display device. 8. The method of claim 7, Storing data supplied to the data driver in a frame memory in a frame unit; And generating a data transfer control signal for controlling the frame memory in a control signal generator to transfer the data stored in the frame memory differently in the odd frame and the even frame period. . The method according to claim 6, The non-emission period A reset period in which an initializing voltage is supplied to the data line, a ground voltage is supplied to the power line and the control line, and a gate voltage of low logic is supplied to the gate line, An initialization period in which the base voltage is supplied to the power supply line and the control line and the gate voltage of the high logic is supplied to the gate line; And a sampling period in which the control voltage is supplied to the control line, the base voltage is supplied to the power supply line, and the gate voltage of the high logic is supplied to the gate line.

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