KR101534683B1 - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method of forming the same. To this end, a cell bit line pattern and a peripheral gate pattern can be formed on a semiconductor substrate. The cell bit line pattern may be disposed on an inactive region around the cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. The peripheral contact plug may be disposed on the peripheral active region so as to be located on the side of the peripheral gate pattern. An insulating film may be disposed to expose the cell bit line pattern, the peripheral gate pattern, the upper surfaces of the cell and the peripheral contact plugs at substantially the same level.

Semiconductor device, bit line, gate, contact, plug

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a method of forming the same.

Embodiments relate to a semiconductor device and a method of forming the same.

In general, the high integration of the semiconductor device can be realized by simply reducing the numerical value of the design rule relating to the distance between the components in the cell array region and the peripheral circuit region. And, the acceleration of the semiconductor device can be implemented by rapidly charging the components corresponding to the reduced design rule or by passing the charge quickly between the components. Through this, the semiconductor device can contribute to constituting an electronic circuit for multi-purpose in an electronic product.

However, the semiconductor device can be manufactured under the harsh environment of the semiconductor manufacturing process. This is because the semiconductor device is not considered in relation to the shape of the components, for example, the thickness, the area, and the volume, and may have a structure that increases the species and aspect ratio of the contact structure. In addition, the semiconductor device may have a structure to increase electric short and parasitic capacitance between components corresponding to a reduced design rule.

A problem to be solved according to embodiments is to provide a semiconductor device which is manufactured in a good environment of a semiconductor manufacturing process even in a reduced design rule and has a structure capable of reducing electrical shorts and parasitic capacitance between components, ≪ / RTI >

As a solution to the above problem, the embodiments provide a semiconductor device including a cell bit line pattern made of the same material and a peripheral gate pattern in a cell array region and a peripheral circuit region, and a method for forming the same.

A first aspect of a semiconductor device according to embodiments may include an inactive region defining first and second active regions of a semiconductor substrate. The first upper wiring may be disposed on the inactive region around the first active region. A first contact plug contacting the first active region and the first upper interconnect may be disposed. The first contact plug may have a top surface at the same level as the top surface of the first upper wiring. And the second lower wiring may be disposed on the second active region. The second lower wiring may have a top surface at the same level as the top surface of the first contact plug. And a second upper wiring may be disposed on the second lower wiring. A second contact plug contacting the second active region and the second upper wiring may be disposed.

According to selected embodiments, the first and second upper wirings have different structures and may include bit lines.

According to selected embodiments, the semiconductor device may further include a first lower wiring line intersecting the second upper wiring line. The first lower wiring may protrude from the upper surface of the semiconductor substrate toward the upper side of the semiconductor substrate. The first lower wiring may extend from the upper surface of the semiconductor substrate toward the lower side of the semiconductor substrate.

According to selected embodiments, the first and second lower wirings have different structures and may include gates. The first lower wiring may include a selected one of a top surface having a step difference through the active region and the inactive region, and a top surface positioned at substantially the same level. The second lower wiring may have the same material as the first upper wiring.

According to selected embodiments, the first lower and upper wirings may electrically interact through the first active region and the first contact plug. And the second lower and upper wirings may electrically interact with each other through the second active region and the second contact plug.

According to selected embodiments, the first and second contact plugs may have a selected one of the same structure and different structures. The second contact plug may include a top surface on a selected one of the same level and another level of the upper surface of the second lower wiring.

According to selected embodiments, the first contact plug is inserted on the upper side of the first upper wiring via one end, and the first active area and the nonactive area around the first active area .

According to selected embodiments, the semiconductor device may further include first and second gate spacers which are sequentially stacked on each of both sidewalls of the second lower wiring.

According to other embodiments, the first upper interconnect may be disposed parallel to the first active region and at a right angle to the first lower interconnect.

According to other embodiments, the first upper interconnect may be arranged parallel to the first active region and inclined with respect to the first lower interconnect.

A second aspect of the semiconductor device according to the embodiments may include a cell array region of the semiconductor substrate and an inactive region disposed in the peripheral circuit region. Cells and peripheral active regions may be disposed in the cell array region and the peripheral circuit region. The cell and peripheral active regions may be defined as the inactive regions. And a first wiring, a second wiring, and a cell contact plug may be disposed in the cell array region. The first wiring may be located in the cell active region and in an inactive region around the cell active region. The second wiring may be located on the inactive region around the cell active region and intersect the first wiring. The cell contact plug may be in contact with the cell active region and the second wiring while having a top surface substantially at the same level as the top surface of the second wiring. The third wiring, the fourth wiring, and the peripheral contact plug may be disposed in the peripheral circuit region. The third interconnection may be located on the peripheral active region and may have the same material as the second interconnection and a top surface at the same level as the upper surface of the cell contact plug. The fourth wiring may be located on the third wiring. The peripheral contact plug may be in contact with the peripheral active region and the fourth wiring. The first wiring may be a shape selected from a part inserted into the second wiring and passing through the second wiring and a shape passing through the second wiring in contact with the second wiring under the second wiring.

According to selected embodiments, the first and third wirings may have gates of different structures located at different levels in the semiconductor substrate. The second and fourth wirings may have bit lines of different structures located at different levels in the semiconductor substrate. The second and third wirings may include the same material.

According to selected embodiments, the cell and peripheral contact plugs may have a selected one of the same structure and different structures. The peripheral contact plug may have a top surface on a selected one of the same level and different levels as the top surface of the third wiring.

According to other embodiments, the second wiring may be arranged parallel to the cell active region and at right angles to the first wiring.

According to other embodiments, the second wire may include two lines that define a point. The cell active region may be disposed parallel to each of the two lines. The first wiring may be arranged to be inclined with respect to the cell active region and the second wiring.

According to other embodiments, the second wire may include two lines that define a point of intersection. The cell active region may be centered at the cusp point between the two lines and parallel to the two lines. The first wiring may be arranged to be inclined with respect to the cell active region and the second wiring.

A method of forming a semiconductor device according to embodiments may include forming first and second active regions in a semiconductor substrate that are defined as inactive regions. The first upper wiring may be formed on the inactive region around the first active region. And a second lower wiring may be formed on the second active region. A first contact plug electrically connecting the first active region and the first upper wiring can be formed. And a second contact plug may be formed on the second active region so as to be positioned around the second lower wiring. And a second upper interconnect may be formed on the second contact plug.

According to selected embodiments, a method of forming a semiconductor device includes forming a first insulating layer on the first active region and the inactive region around the first active region, and a second insulating layer on the second active region Forming a first photoresist film on the third insulating film, and forming a first photoresist film on the first active region and a second insulating film on the first active region, Wherein the first and third insulating films, the first conductive film, the first active region, and the inactive region around the first active region are formed using a first photoresist film as an etch mask, To form a trench, and removing the first photoresist film from the semiconductor substrate.

According to selected embodiments, a method of forming a semiconductor device includes forming a second conductive film partially filling the trench, forming a fourth insulating film on the second conductive film and covering the third insulating film, and And etching the third and fourth insulating films to expose the first conductive film to form a first lower wiring in the trench. Wherein the first lower wiring includes the second conductive film and the etched fourth insulating film, the first lower wiring has a shape partially inserted into the first conductive film and a shape located under the first conductive film, And may have a selected one.

According to the selected embodiments, forming the first upper wiring and the second lower wiring may include forming a third conductive film and a fifth insulating film in order on the first conductive film, Wherein the first photoresist patterns are formed so as to correspond to the first upper wiring and the second lower wiring, and the first photoresist patterns are etched by an etching mask so as to expose the first and second insulating films Etching the first and third conductive films, and the fourth and fifth insulating films using the first and third conductive films, and removing the first photoresist patterns from the semiconductor substrate. In this case, the third conductive film may have at least one conductive material.

According to the selected embodiments, after the first upper wiring and the second lower wiring are formed, the first upper wiring has a shape parallel to the first active region and has a right angle to the first lower wiring And an inclined shape.

According to selected embodiments, a method of forming a semiconductor device includes forming a sixth insulating film on the first and second insulating films so as to conformally cover the first upper wiring and the second lower wiring, Forming first spacers on sidewalls of the first upper wiring and the second lower wiring by etching the second and sixth insulating films to expose the insulating film and the second active region, Forming second spacers on the spacers, forming the first insulating layer and the second active region to cover the first upper wiring, the second lower wiring, and the second spacers, and the seventh And 8 insulating films in this order, and etching the seventh and eighth insulating films to expose the first upper wiring and the second lower wiring. In this case, the second spacers may comprise an insulating material.

According to other embodiments, forming the first and second contact plugs may include forming a second photoresist film on the seventh and eighth insulating films, wherein the second photoresist film is formed on the first and second active areas And forming first and second contact holes by etching the first, seventh and eighth insulating films using the second photoresist film as an etching mask, the first and second contact holes being formed to have openings exposing the eighth insulating film while aligning, 1 contact hole exposes the first active region and the second contact hole is formed to expose a second active region, removing the second photoresist film from the semiconductor substrate, and forming the first and second contacts Filling the holes with the first and second contact plugs. The first and second contact plugs may be formed using the same material.

According to other embodiments, forming the second upper interconnections may include forming a fourth conductive film and a ninth insulating film in order on the seventh and eighth insulating films so as to cover the first and second contact plugs, The second photoresist pattern is formed so as to correspond to the second upper wiring, and the second photoresist pattern is etched to expose the seventh and eighth insulating films, To etch the fourth conductive film and the ninth insulating film, and to remove the second photoresist pattern from the semiconductor substrate.

Forming the first and second contact plugs may include forming a second photoresist film on the seventh and eighth insulating films, wherein the second photoresist film is aligned with the first active area, A first contact hole exposing the first active region is formed by etching the first, seventh and eighth insulating films using the second photoresist film as an etching mask so as to have an opening for exposing the eighth insulating film , Removing the second photoresist film from the semiconductor substrate, and filling the first contact hole with the first contact plug. The forming of the first and second contact plugs may include forming a ninth insulating film on the seventh and eighth insulating films so as to cover the first contact plug and forming a third photoresist film on the ninth insulating film, , The third photoresist film is formed to have an opening for exposing the ninth insulating film while being aligned with the second active region, and the seventh, eighth, and ninth insulating films are etched using the third photoresist film as an etching mask Thereby forming a second contact hole exposing the second active region, removing the third photoresist film from the semiconductor substrate, and filling the second contact hole with the second contact plug . The first and second contact plugs may have different structures with at least one conductive material.

According to another embodiment, the formation of the second upper interconnection may include forming a fourth conductive film and a tenth insulating film in order on the ninth insulating film so as to cover the second contact plug, Forming a second photoresist pattern on the second insulating layer, wherein the second photoresist pattern is formed so as to correspond to the second upper interconnection, and exposing the ninth insulating layer using the second photoresist pattern as an etching mask, Etching the film and the tenth insulating film, and removing the second photoresist pattern from the semiconductor substrate.

As described above, the embodiments can provide a semiconductor device through a semiconductor manufacturing process having a better environment compared to the prior art even in a reduced design rule by matching the same material to a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate .

Embodiments can provide a cell bit line pattern and a cell contact plug having a contact structure located at the same level, rather than a stacked contact structure. Accordingly, the semiconductor device can have a smaller parasitic capacitance between the cell bit line pattern and the cell contact plug, and between the cell bit line pattern and the surrounding components of the cell contact plug, compared to the prior art.

In addition, since the embodiment forms the peripheral bit line pattern on the cell bit line pattern and the peripheral gate pattern, the occupancy rate of the components is increased, so that the margin of the semiconductor manufacturing process can be increased compared to the prior art even in the reduced design rule.

In addition, since the embodiments disclose the cell bit line pattern and the cell contact plug contacting at the same level and the insulating material at the upper side of the cell contact plug, the cell bit line pattern, the cell contact plug, the cell bit line pattern, It is possible to further prevent an electrical short between the constituent displays near the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS The aspects of the above embodiments will now be described with reference to the accompanying drawings. It should be understood, however, that the above-described embodiments may be embodied in many different forms and should not be construed as limited to the aspects set forth herein. Rather, the aspects make the embodiments more thorough and complete, and will allow those skilled in the art to fully convey the scope of the embodiments. It is to be understood that, although the terms referring to first, second, etc. may be used herein to describe various components, the components are not intended to be limited to these terms. These terms are merely used to distinguish one component from another.

Here, as used, the terms 'pad, base and mask' may be used to describe the use of semiconductor films prior to forming semiconductor patterns. It will be further understood that the terms relative to one another, such as "relative to a certain element, a relative relationship with a certain element, or a relationship with other elements, such as" cell, bottom (side), top (side), bottom, And the use of terminology herein is for the purpose of describing particular aspects only and is not intended to limit the embodiments.

Now, the semiconductor device according to the embodiments will be described in more detail with reference to Figs.

1 to 3 are plan views showing semiconductor devices according to embodiments. 4 is a cross-sectional view illustrating a semiconductor device according to embodiments taken along the cutting lines I-I ', II-II', III-III ', and IV-IV' of FIG. In this case, the same reference numerals are used for the same members in Figs.

Referring to FIG. 1, a semiconductor device 233 according to embodiments may include a cell array region C1 and a peripheral circuit region (P). The cell array region C1 may include cell gate patterns 59 and cell bit line patterns 82 or 86 that are orthogonal to each other. Cell active regions 6 crossing at right angles to the cell gate patterns 59 can be arranged. The cell active regions 6 may be located between the cell bit line patterns 82 or 86 and disposed parallel to the cell bit line patterns 82 or 86. [

The cell contact holes 151 may partially overlap the cell active regions 6 and the cell bit line patterns 82 or 86. [ The cell contact holes 151 may be disposed in a central region of the cell active regions 6. The cell contact holes 151 may be disposed between the cell gate patterns 59. The node contact holes 204 and the storage nodes 225 may be disposed at the edges of the cell active regions 6 so as to be positioned around the cell contact holes 151. [

Meanwhile, the peripheral circuit region P may include a peripheral gate pattern 84 or 88 and peripheral bit line patterns 185 that are parallel to each other. The peripheral active region 8 passing through the peripheral gate pattern 84 or 88 and the peripheral bit line patterns 185 may be disposed. Peripheral contact holes 157 may be formed in the peripheral active region 8 so as to overlap with the peripheral bit line patterns 185.

2, a semiconductor device 236 according to embodiments may include a cell array region C2 and a peripheral circuit region P of FIG. The cell array region C2 may include cell active regions 6 and cell bit line patterns 89. The cell active regions 6 may be disposed between the cell bit line patterns 89. The cell bit line patterns 89 may have ELs defining Cusp (CP) or Inflection Points (CP). In this case, the cell active regions 6 may be arranged parallel to individual lines (EL), located between CPs or between inflection points (CP).

Cell gate patterns 59 that are inclined to the cell active regions 6 and the cell bit line patterns 89 may be disposed. Cell contact holes 151 overlapping the cell active regions 6 and the cell bit line patterns 89 may be disposed. Node contact holes 204 and storage nodes 225 may be disposed at the edges of the cell active regions 6. In this case, the cell contact holes 151, the node contact holes 204, and the storage nodes 225 are connected to the cell active regions 6, the cell gate patterns 59 and the cell bit line pattern 89, Can have the same arrangement structure as in Fig.

Referring to FIG. 3, a semiconductor device 239 according to embodiments may include a cell array region C3 and a peripheral circuit region P in FIG. The cell array region C3 may include cell active regions 6 and cell bit line patterns 89. [ The cell active regions 6 may be disposed between the cell bit line patterns 89. The cell bit line patterns 89 may have the same shape as that of FIG. In this case, the cell active regions 6 are arranged in a matrix of individual lines EL, centered below the tangent points (CP) or inflection points (CP) between individual lines (EL) As shown in FIG.

Cell gate patterns 59 that are inclined to the cell active regions 6 and the cell bit line patterns 89 may be disposed. The cell gate patterns 59 may have CPs or inflection points CP of the cell bit line patterns 89 between the patterns 59. Cell contact holes 151 overlapping the cell active regions 6 and the cell bit line patterns 89 may be disposed. The cell contact holes 151 may be formed on the CPs or the inflection points CP of the cell bit line patterns 89. Node contact holes 204 and storage nodes 225 may be disposed at the edges of the cell active regions 6.

The cell contact holes 151, the node contact holes 204 and the storage nodes 225 are also connected to the cell active regions 6, the cell gate patterns 59 and the cell bit line patterns 89 1 < / RTI >

Referring to Fig. 4, a semiconductor substrate 2 according to embodiments can be prepared. The semiconductor substrate 2 may have a cell array region C1 and a peripheral circuit region P shown in Fig. The cell bit line pattern 82 and the peripheral gate pattern 84 may be disposed in the cell array region C1 and the peripheral circuit region P, respectively. The cell bit line pattern 82 may be arranged along the cut line I-I 'on the inactive region 4 around the cell active region 6 in the cell array region C1. The cell bit line pattern 82 may include a cell lower bit line 24, a cell upper bit line 64 and a cell bit line capping pattern 74 which are stacked in sequence.

The cell lower bit line 24 and the cell upper bit line 64 may include a conductive material. The cell bit line capping pattern 74 may comprise an insulating material. The peripheral gate pattern 84 may be arranged on the peripheral active region 8 of the peripheral circuit region P as shown in the cutting line IV-IV '. The peripheral gate pattern 84 may include a peripheral bottom gate 28, a peripheral top gate 68, and a peripheral gate capping pattern 78 that are sequentially stacked. The peripheral bottom gate 28, the peripheral upper gate 68 and the peripheral gate capping pattern 78 are each connected to the cell lower bit line 24, the cell upper bit line 64 and the cell bit line capping pattern 74, May be the same substance.

The pad film 10 may be disposed on the inactive region 4 and the cell active region 6. The pad film 10 may include an insulating material. A peripheral gate insulation pattern 13 may be disposed between the peripheral gate pattern 84 and the peripheral active area 8. [ The peripheral gate insulating pattern 13 may include an insulating material. The bit line spacers 94 may be disposed on the sidewalls of the cell bit line pattern 82. The bit line spacers 94 may comprise an insulating material. The lower and upper gate spacers 98 and 128 may be sequentially disposed on the sidewalls of the peripheral gate pattern 84.

The lower and upper gate spacers 98, 128 may comprise an insulating material. The etching stopper film 138 and the lower interlayer insulating film 145 surrounding the cell bit line pattern 82 and the peripheral gate pattern 84 may be sequentially disposed on the semiconductor substrate 2. [ The etch stop layer 138 and the lower interlayer insulating layer 145 may be disposed on the peripheral active region 8, the pad film 10, and the upper gate spacers 128. The etch stop layer 138 and the lower interlayer insulating layer 145 may include an insulating material. The cell contact plug 153 and the peripheral contact plugs 159 may be disposed on the pad film 10, the etch stop layer 138, and the lower interlayer insulating layer 145. [ The cell contact plug 153 and the peripheral contact plugs 159 penetrate through the pad film 10, the etching stopper film 138 and the lower interlayer insulating film 145 to form the cell active region 6 and the peripheral active region 8, Respectively.

The cell contact plug 153 and the peripheral contact plugs 159 may include a conductive material. The cell contact plug 153 may be surrounded by the pad film 10, the etching stopper film 138, and the lower interlayer insulating film 145, as shown by the cutting lines II-II '. The cell contact plug 153 can contact the cell active region 6 and the cell bit line pattern 82 with the cutting lines I-I 'and III-III'. More specifically, the cell contact plugs 153 contact the cell active region 6 and extend along the sides of the cell bit line pattern 82 to form the cell bit line capping pattern 74 with the cutting lines I -I 'and III-III', respectively. In this case, the cell contact plug 153 may contact the cell upper bit line 64 through the cell bit line capping pattern 74.

The peripheral contact plugs 159 may be surrounded by an etch stop layer 138 and a lower interlayer insulating layer 145. The peripheral contact plugs 159 may be located at the sides of the peripheral gate pattern 84 and may contact the peripheral active area 8, such as along the cutting line IV-IV '. The peripheral contact plugs 159 may have substantially the same top surface as the cell bit line pattern 82, the peripheral gate pattern 84, and the cell contact plugs 153. Peripheral bit line patterns 185 may be disposed on the peripheral gate pattern 84. The peripheral bit line patterns 185 may contact the peripheral contact plugs 159.

The peripheral bit line pattern 185 may include a peripheral bit line 168 and a peripheral bit line capping pattern 178 which are stacked in turn. The peripheral bit line 168 may comprise a conductive material. The bit line capping pattern 178 may comprise an insulating material. The upper interlayer insulating film 195 may be disposed on the etch stop layer 138 and the lower interlayer insulating layer 145 so as to surround the peripheral bit line pattern 185. The upper interlayer insulating film 195 may include an insulating material. The upper interlayer insulating layer 195 may expose the upper surface of the peripheral bit line patterns 185. The node plugs 208 may be disposed in the lower and upper interlayer insulating films 145 and 195, the etching stopper film 138, and the pad film 10.

The node plugs 208 may comprise a conductive material. The node plugs 208 may contact the cell active region 6. The node plugs 208 and the peripheral bit line pattern 185 may have the same top surface. A protective film 215 may be disposed on the upper interlayer insulating film 195 so as to cover the peripheral bit line pattern 185 and the node plugs 208. The passivation layer 215 may include an insulating material. Storage nodes 225 that are located in the protective layer 215 and extend upward from the protective layer 215 may be disposed. The storage nodes 225 may include a conductive material.

The storage nodes 225 may be in contact with the node plugs 208 through the protective layer 215. On the other hand, the cell gate patterns 59 may be disposed below the cell bit line patterns 82 and the peripheral gate patterns 84. The cell gate patterns 59 may be disposed in the inactive region 4 and the cell active region 6 of the cell array region C1. More specifically, the cell gate patterns 59 may protrude from the upper surface of the semiconductor substrate 2 toward the upper side of the semiconductor substrate 2. [ The cell gate patterns 59 may extend from the upper surface of the semiconductor substrate 2 toward the lower side of the semiconductor substrate 2. [ In this case, each of the gate patterns 59 may have an upper surface passing through different levels, such as cutting lines I-I 'and II-II'.

The cell gate patterns 59 may have a step difference below the cell bit line pattern 82 and around the cell bit line pattern 82. The cell gate patterns 59 may extend horizontally through the inactive region 4 and the cell active region 6. The cell gate patterns 59 may be arranged in the cell active region 6 between the cell contact plug 156 and the node plugs 208 as shown in the cut line I-I '. The cell gate patterns 59 may include cell gates 53 and cell gate capping patterns 56. The cell gates 53 may comprise a conductive material. The cell gate capping patterns 56 may comprise an insulating material.

The cell gate capping patterns 56 of the cell gate patterns 59 are divided into a plurality of sub-bit lines 24 of the cell bit line pattern 82 in the inactive region 4 as shown by the broken line I-I ' . The cell gate insulating patterns 48 may be disposed between the cell active region 6 and the cell gate patterns 59. [ However, the cell gate insulating patterns 48 may have different thicknesses in the inactive region 4 and the cell active region 6 through the thermal oxidation process. The cell impurity regions 104 around the cell gate patterns 59 and the peripheral impurity regions 140 below the peripheral gate pattern 84 may be disposed.

The cell impurity regions 104 may be in contact with the cell contact plug 153 and the node plugs 208. The peripheral impurity regions 140 may overlap the peripheral gate pattern 84 and be in contact with the peripheral contact plugs 159. The cell impurity regions 104 and the peripheral impurity regions 140 may have different conductivities. The peripheral impurity regions 140 may have a lightly doped drain (LDD) structure. The cell gate patterns 59 and the cell impurity regions 104 may be included in the cell transistors. The peripheral gate pattern 84 and the peripheral impurity regions 140 may be included in peripheral transistors.

The cell transistors and the peripheral transistors can constitute the semiconductor device 233 according to FIG. 1 together with the cell bit line pattern 82, the peripheral bit line patterns 185, and the storage nodes 225 . Alternatively, the semiconductor device 233 may be replaced by the semiconductor device 236 or 239 of FIG. 2 or 3. FIG.

Next, a method of forming the semiconductor device according to the embodiments will be described with reference to FIGS.

5 to 8 are cross-sectional views illustrating a method of forming a semiconductor device according to embodiments taken along the cutting lines I-I ', II-II', III-III ', and IV-IV' of FIG. In this case, the same reference numerals are used for the same members as in Figs. 1 to 4 in Figs. 5 to 8.

Referring to FIG. 5, a semiconductor substrate 2 may be prepared according to embodiments. The semiconductor substrate 2 may have a cell array region C1 and a peripheral circuit region P shown in Fig. The cell array region C1 may have at least one cell active region 6. The peripheral circuit region (P) may have at least one peripheral active region (8). The cell active region 6 and the peripheral active region 8 may be defined as the inactive region 4 in the semiconductor substrate 2. The inactive region 4 may have a device isolation film. The device isolation film may have an insulating material.

The peripheral gate insulating film 11 may be formed on the pad film 10 and the peripheral active region 8 on the cell active region 6 and the inactive region 4 around the cell active region 6 . The pad film 10 may include an insulating material, for example, silicon nitride. The peripheral gate insulating film 11 may include an insulating material, for example, silicon oxide. The peripheral gate insulating film 11 may also be disposed on the inactive region 4 defining the peripheral active region 8. However, the peripheral gate insulating film 11 may be formed with different thicknesses in the inactive region 4 and the peripheral active region 8 when a thermal oxidation process is used.

The mask conductive layer 20 and the mask cap layer 30 may be sequentially formed on the pad film 10 and the peripheral gate insulating film 11. The mask conductive layer 20 may comprise a conductive material, for example polysilicon doped with impurity ions. The mask cap layer 30 may include an insulating material, for example, silicon nitride. A photoresist film may be formed on the mask cap film 30. [ The photoresist film may have openings that align with the cell active region 6 while exposing the mask cap film 30 in the cell array region C1.

The mask conductive film 20 and the pad film 10 are sequentially etched using the photoresist film as an etching mask to sequentially form the cell active region 6 and the inactive region 4 around the region 6 The trenches 44 may be formed. The trenches 44 may extend from the upper surfaces of the cell active region 6 and the inactive region 4 around the region 6 toward the lower side of the semiconductor substrate 2. [ After the trenches 44 are formed, the photoresist film may be removed from the semiconductor substrate 2. The cell gate insulation patterns 48 can be formed in the trenches 44 as shown in the cutting lines I-I 'and II-II'.

The cell gate insulating patterns 48 may comprise an insulating material, for example silicon oxide. The cell gate insulating patterns 48 may be formed with different thicknesses in the inactive region 4 and the cell active region 6 when a thermal oxidation process is used.

Referring to FIG. 6, cell gates 53 that partially fill the trenches 44 may be formed. The cell gates 53 may comprise a conductive material, for example, titanium nitride. A cell gate capping film covering the mask capping layer 30 may be formed on the cell gates 53. The cell gate capping film may comprise an insulating material, such as silicon nitride. The cell gate capping layer and the mask capping layer 30 may be sequentially etched to expose the mask conductive layer 20 of FIG. 5 to form the cell gate capping patterns 56 as shown by the broken line I-I '.

The cell gate capping patterns 56 may also be formed in the cutting line II-II 'in the same shape as the cutting line I-I'. In this case, the cell gate capping patterns 56 may be formed in the cell active region 6 to fill the trenches 44. The cell gate capping patterns 56 may be formed in the pad film 10 and the mask conductive film 20. The cell gate capping patterns 56 may form cell gate patterns 59 together with the cell gates 53. A base conductive layer (not shown in the figure) and a base capping layer (not shown in the drawing) may be formed on the mask conductive layer 20 in this order.

The underlying conductive film may comprise a conductive material, such as barrier metal and tungsten, which in turn are stacked. The barrier metal may include a metal and / or metal nitride to prevent the diffusion of tungsten atoms into the mask conductive layer 30. The underlying capping film may comprise an insulating material, for example, silicon nitride. Photoresist patterns may be formed on the base cap layer. The photoresist patterns may be formed in the cell array region C1 and the peripheral circuit region P. [ The photoresist pattern of the cell array region C1 may be formed on the inactive region 4 around the cell active region 6. [

A photoresist pattern of the peripheral circuit region P may be formed on the peripheral active region 8 and on the inactive region 4 around the peripheral active region 8. The cell bit line pattern 82 and the peripheral gate pattern 84 may be formed by successively etching the underlying capping layer, the underlying conductive layer, and the mask conductive layer 20 using the photoresist patterns as an etch mask. The cell bit line pattern 82 may be formed on the inactive region 4 around the cell active region 6. The cell bit line pattern 82 may be formed as shown in a cutting line II-II 'so as to expose the pad film 10.

In this case, the cell gate capping pattern 56 may be partially removed from the cell active region 6 exposed in the photoresist pattern while the mask conductive film 20 is being etched. The cell gate capping pattern 56 under and around the cell bit line pattern 82 may be formed as cutting lines I-I 'and II-II' so as to have top faces located at different levels. Therefore, the cell gate capping pattern 56 may have a step on the upper surface. The cell bit line pattern 82 may be replaced with the cell bit line pattern 89 of FIG. 2 or FIG. The peripheral gate pattern 84 may be formed on the peripheral active region 8 of the peripheral circuit region P and the inactive region 4 around the peripheral active region 8. [

The peripheral gate pattern 84 may be formed to expose the peripheral gate insulating film 11 of FIG. The cell bit line pattern 82 may include a cell lower bit line 24, a cell upper bit line 64 and a cell bit line capping pattern 74 which are stacked in sequence. The peripheral gate pattern 84 may include a peripheral bottom gate 28, a peripheral upper gate 68, and a peripheral gate capping pattern 78. After the cell bit line pattern 82 and the peripheral gate pattern 84 are formed, the photoresist patterns can be removed from the semiconductor substrate 2.

A lower spacer film may be formed on the pad film 10 and the peripheral gate insulating film 11 so as to cover the cell bit line pattern 82 and the peripheral gate pattern 84. [ The lower spacer film may comprise an insulating material, for example silicon nitride. The bottom spacer film may be etched to form bit line spacers 94 on the sidewalls of the cell bit line pattern 82 and bottom gate spacers 98 on the sidewalls of the peripheral gate pattern 84. The bit line spacers 94 may be formed to expose the pad film 10.

The bottom gate spacers 98 may be formed to expose the peripheral active region 8. Subsequently, the first peripheral impurity regions 108 may be formed in the cell impurity regions 104 and the peripheral active region 8 in the cell active region 6. The cell impurity regions 104 may be formed between the cell gate patterns 59 using impurity ions. The first peripheral impurity regions 108 may be formed to overlap the peripheral gate pattern 84 using impurity ions. The cell impurity regions 104 and the first peripheral impurity regions 108 may have the same conductivity or different conductivities.

The cell impurity regions 104 may have a conductivity different from that of the semiconductor substrate 2. The first peripheral impurity regions 108 may have the same conductivity as the semiconductor substrate 2 or may have different conductivity. The upper spacer film 124 may be formed in the cell array region C1 and the peripheral circuit region P so as to cover the cell bit line pattern 82 and the peripheral gate pattern 84. [ The upper spacer film 124 may be formed on the cell bit line patterns 82 and sufficiently filling between the cell bit line patterns 82 in the cell array region C1 of FIG.

Alternatively, the upper spacer film 124 may conformally cover the peripheral gate pattern 84 and the bottom gate spacers 98 in the peripheral circuit region P. The upper spacer film 124 may be etched to form upper gate spacers 128 on the lower gate spacers 98. The second peripheral impurity regions 135 may be formed in the peripheral active region 8 using the peripheral gate pattern 84 and the lower and upper gate spacers 98 and 128 as masks. The second peripheral impurity regions 135 may be formed to overlap the bottom gate spacers 98 and / or the top gate spacers 128 using impurity ions.

The first and second peripheral impurity regions 108 and 135 may constitute peripheral impurity regions 140. The peripheral impurity regions 140 may have an LDD structure. A photoresist film may be formed on the peripheral circuit region P so as to cover the peripheral gate pattern 84 and the lower and upper gate spacers 98 and 128. The photoresist film may be formed to expose the cell array region C1. The upper spacer film 124 is removed from the semiconductor substrate 2 by using the photoresist film as an etching mask and the cell bit line pattern 82, the bit line spacers 94 and the pad film 10 as etching buffer films. .

After the upper spacer film 124 is removed, the photoresist film may be removed from the semiconductor substrate 2. [

Referring to FIG. 7, the etching stopper film 138 and the peripheral circuit region P are formed in the cell array region C1 and the peripheral circuit region P so as to cover the cell bit line pattern 82 and the peripheral gate pattern 84, The interlayer insulating film 145 can be formed in order. The etch stop layer 138 may comprise an insulating material, for example, silicon nitride. The lower interlayer insulating film 145 may include an insulating material, for example, silicon oxide. The etching stopper film 138 and the lower interlayer insulating film 145 may be sequentially etched to expose the cell bit line pattern 82 and the peripheral gate pattern 84. [

A photoresist film may be formed on the etch stop film 138 and the lower interlayer insulating film 145. [ The photoresist film may have openings for exposing the lower interlayer insulating film 145. The openings may be formed to be located between the cell gate patterns 59 in the cell array region C1 and on the side portions of the peripheral gate pattern 84 in the peripheral circuit region P. [ The lower interlayer insulating film 145, the etching stopper film 138, the cell bit line capping pattern 74 and the pad film 10 are sequentially etched using the photoresist film as an etching mask to form the cell contact hole 151 and the peripheral contact Holes 157 can be formed.

The cell contact holes 151 are formed by cutting lines I-I ', I-I', I-I 'so as to expose the cell active region 6, the inactive region 4 around the cell active region 6, II 'and III-III', respectively. In this case, the cell contact hole 151 extends from the upper side of the cell bit line pattern 82 through the cell bit line capping pattern 74 to the upper cell bit line 64, the bit line spacer 94, May be formed to expose the membrane 138. The cell contact hole 151 may be formed to expose the etching stopper film 138 on the side of the cell bit line pattern 82.

The peripheral contact holes 157 may be formed to expose the peripheral active region 8. After the cell and the peripheral contact holes 151 and 157 are formed, the photoresist film may be removed from the semiconductor substrate 2. [ A contact plug film may be formed on the etching stopper film 138 and the lower interlayer insulating film 145 so as to fill the cell and the peripheral contact holes 151 and 157. The contact plug film may comprise a conductive material, e. G., A stack of barrier metal and tungsten. The barrier metal may be formed in the same manner as the barrier metal of the underlying conductive film of Fig.

The contact plug film is etched to expose the etch stop layer 138 and the lower interlayer insulating layer 145 to form a cell contact plug 153 in the cell contact hole 151 and peripheral contact plugs 159). The cell and peripheral contact plugs 153 and 159 may be formed to have substantially the same top surface as the cell bit line pattern 82 and the peripheral gate pattern 84. [ The wiring film 164 and the wiring capping film 174 can be formed on the etching stopper film 138 and the lower interlayer insulating film 145 to cover the cell and the peripheral contact plugs 153 and 159 .

The wiring film 164 may be formed in the same manner as the contact plug film. The wiring cap layer 174 may include an insulating material, for example, silicon nitride.

Referring to FIG. 8, photoresist patterns may be formed on the wiring cap layer 174 of FIG. 7 according to embodiments. The peripheral bit line patterns 185 may be formed in the peripheral circuit region P by sequentially etching the wiring cap layer 174 and the wiring film 164 using the photoresist patterns as an etching mask. The peripheral bit line patterns 185 may be formed to expose the etch stop layer 138 and the lower interlayer insulating layer 145. The peripheral bit line patterns 185 may include a peripheral bit line 168 and a peripheral bit line capping pattern 178.

After the peripheral bit line patterns 185 are formed, the photoresist patterns may be removed from the semiconductor substrate 2. An upper interlayer insulating film 195 may be formed on the etch stop layer 138 and the lower interlayer insulating layer 145 to expose the peripheral bit line patterns 185. [ The upper interlayer insulating film 195 may include an insulating material, for example, silicon oxide. A photoresist film may be formed on the upper interlayer insulating film 195. The photoresist film may be formed so as to have openings that align with the cell active region 6 in the cell array region C1.

The node contact holes 204 can be formed by sequentially etching the upper interlayer insulating film 195, the lower interlayer insulating film 145, the etching stopper film 138 and the pad film 10 using the photoresist film as an etching mask . The node contact holes 204 may be formed to expose the cell active region 6. After the node contact holes 204 are formed, the photoresist film can be removed from the semiconductor substrate 2. [ And note plugs 208 may be formed in the node contact holes 204. The node plugs 208 may comprise a conductive material, for example polysilicon.

A protective film 215 may be formed on the upper interlayer insulating film 195 so as to cover the peripheral bit line pattern 185 and the node plugs 208. The passivation layer 215 may include an insulating material such as silicon nitride. And may form storage nodes 225 that pass through the passivation layer 215 and contact the node plugs 208. The storage nodes 225 may comprise a conductive material, for example, titanium nitride. The storage nodes 225 are connected to the semiconductor device 100 according to the embodiments along with the cell gate pattern 59, the cell bit line pattern 82, the peripheral gate pattern 84, (233).

In addition, the semiconductor device 233 may be replaced with the semiconductor device 236 or 239 of FIG. 2 or 3 according to embodiments. The semiconductor device 233, 236 or 239 is capable of providing more parasitic capacitance between the cell bit line pattern 82, the cell contact plug 153 and the node plugs 153 and the storage nodes 225 It can have a small value. This is because the cell bit line pattern 82 and the cell contact plug 153 have top surfaces at the same level from the top surface of the semiconductor substrate 2. The semiconductor device 233, 236 or 239 can increase the occupancy of the components on the semiconductor substrate 2 compared to the prior art. This is because the cell bit line pattern 82 can be formed on the inactive region 4.

The semiconductor device 233, 236, or 239 may be reduced compared to the prior art for electrical short between the cell bit line pattern 82, the cell contact plug 153, and the node plugs 153. This is because the cell bit line pattern 82 and the cell contact plug 153 are not sequentially stacked on the semiconductor substrate 2, thereby reducing the probability of electrical short.

9 to 11 are cross-sectional views illustrating a method of forming a semiconductor device according to embodiments taken along the cutting lines I-I ', II-II', III-III ', and IV-IV' of FIG. In this case, the same reference numerals are used for the same members as in Figs. 5 to 8 in Figs. 9 to 11.

Referring to FIG. 9, a cell gate capping film covering the mask cap film 30 of FIG. 5 may be formed on the gate 53 of FIG. 6 according to the embodiments. The cell gate capping film 30 and the mask capping film 30 are sequentially etched so as to expose the mask conductive film 20 of FIG. 5 to expose the cell gate capping patterns 56 to the cutting lines I-I 'and II- As shown in FIG. The cell gate capping patterns 56 may be formed in the cell active region 6 to fill the trenches 44. The upper surface of the cell gate capping patterns 56 may be formed to be located at substantially the same level as the upper surface of the pad film 10. [

The cell gate capping patterns 56 may also be formed in the cutting line II-II 'in the same shape as the cutting line I-I'. The cell gate capping patterns 56 may form cell gate patterns 59 together with the cell gates 53. A lower base conductive layer (not shown in the figure), an upper base conductive film (not shown in the figure), and a base capping layer (not shown in the figure) are formed on the mask conductive layer 20 Can be formed in order. The lower underlying conductive film may be formed on the cell gate capping patterns 56 so as to cover the mask conductive film 20.

The lower underlying conductive film may include the same material as the mask conductive film 20. [ The upper underlying conductive film may comprise a conductive material, such as a barrier metal and tungsten, which in turn are stacked. The barrier metal may include a metal and / or metal nitride to prevent the diffusion of tungsten atoms into the mask conductive layer 30. The underlying capping film may comprise an insulating material, for example, silicon nitride. Photoresist patterns may be formed on the base cap layer. The photoresist patterns may be formed in the cell array region C1 and the peripheral circuit region P. [

 The photoresist pattern of the cell array region C1 may be formed on the inactive region 4 around the cell active region 6. [ A photoresist pattern of the peripheral circuit region P may be formed on the peripheral active region 8 and on the inactive region 4 around the peripheral active region 8. The photoresist patterns are used as an etching mask to sequentially etch the underlying cap layer, the upper base conductive layer, the lower underlying conductive layer, and the mask conductive layer 20 of FIG. 5 to form the cell bit line pattern 86 and the peripheral gate pattern 88 ) Can be formed. The cell bit line pattern 86 may be formed on the inactive region 4 around the cell active region 6.

The cell bit line pattern 86 may be formed as shown in a cutting line II-II 'so as to expose the pad film 10. The cell gate capping pattern 56 does not have a step on the upper surface as shown in FIG. The cell bit line pattern 86 may be replaced with the cell bit line pattern 89 of FIG. The peripheral gate pattern 88 may be formed on the peripheral active region 8 of the peripheral circuit region P and on the inactive region 4 around the peripheral active region 8. The peripheral gate pattern 88 may be formed to expose the peripheral gate insulating film 11 of FIG.

The cell bit line pattern 86 may include a cell lower bit line 24, a cell middle bit line 60, a cell upper bit line 64 and a cell bit line capping pattern 74 which are stacked in sequence. The peripheral gate pattern 88 may include a peripheral bottom gate 28, a peripheral center gate 62, a peripheral top gate 68, and a peripheral gate capping pattern 78. After the cell bit line pattern 86 and the peripheral gate pattern 88 are formed, the photoresist patterns can be removed from the semiconductor substrate 2.

A lower spacer film may be formed on the pad film 10 and the peripheral gate insulating film 11 so as to cover the cell bit line pattern 86 and the peripheral gate pattern 88. [ The bottom spacer film may be etched to form bit line spacers 94 on the sidewalls of the cell bit line pattern 86 and bottom gate spacers 98 on the sidewalls of the peripheral gate pattern 88. [ The bit line spacers 94 may be formed to expose the pad film 10.

The bottom gate spacers 98 may be formed to expose the peripheral active region 8. Subsequently, the first peripheral impurity regions 108 may be formed in the cell impurity regions 104 and the peripheral active region 8 in the cell active region 6. The cell impurity regions 104 may be formed between the cell gate patterns 59 using impurity ions. The first peripheral impurity regions 108 may be formed to overlap the peripheral gate pattern 88 using impurity ions.

The upper spacer film 124 may be formed in the cell array region C1 and the peripheral circuit region P so as to cover the cell bit line pattern 86 and the peripheral gate pattern 88. [ The upper spacer film 124 may be formed on the cell bit line patterns 86 sufficiently to fill the space between the cell bit line patterns 86 in the cell array region C1 of FIG. Alternatively, the upper spacer film 124 may conformally cover the peripheral gate pattern 88 and the lower gate spacers 98 in the peripheral circuit region P.

The upper spacer film 124 may be etched to form upper gate spacers 128 on the lower gate spacers 98. The second peripheral impurity regions 135 may be formed in the peripheral active region 8 using the peripheral gate pattern 88 and the lower and upper gate spacers 98 and 128 as masks. The second peripheral impurity regions 135 may be formed to overlap the bottom gate spacers 98 and / or the top gate spacers 128 using impurity ions.

The first and second peripheral impurity regions 108 and 135 may constitute peripheral impurity regions 140. A photoresist film may be formed on the peripheral circuit region P so as to cover the peripheral gate pattern 88 and the lower and upper gate spacers 98 and 128. The photoresist film may be formed to expose the cell array region C1. The upper spacer film 124 is removed from the semiconductor substrate 2 by using the photoresist film as an etching mask and the cell bit line pattern 86, the bit line spacers 94 and the pad film 10 as etching buffer films. .

After the upper spacer film 124 is removed, the photoresist film may be removed from the semiconductor substrate 2. [

Referring to FIG. 10, the etching stopper film 138 and the peripheral circuit region P are formed in the cell array region C1 and the peripheral circuit region P so as to cover the cell bit line pattern 86 and the peripheral gate pattern 88, The interlayer insulating film 145 can be formed in order. The etching stopper film 138 and the lower interlayer insulating film 145 may be sequentially etched to expose the cell bit line pattern 86 and the peripheral gate pattern 88. [ Subsequently, a photoresist film can be formed on the etching stopper film 138 and the lower interlayer insulating film 145. [

The photoresist film may have openings for exposing the lower interlayer insulating film 145 of the cell array region C1. The openings may be formed to be located between the cell gate patterns 59. The cell contact hole 151 is formed by successively etching the lower interlayer insulating film 145, the etching stopper film 138, the cell bit line capping pattern 74 and the pad film 10 using the photoresist film as an etching mask . The cell contact holes 151 are formed by cutting lines I-I ', I-I', I-I 'so as to expose the cell active region 6, the inactive region 4 around the cell active region 6, II 'and III-III', respectively.

In this case, the cell contact hole 151 extends from the upper side of the cell bit line pattern 86 through the cell bit line capping pattern 74 to the upper cell bit line 64, the bit line spacer 94, May be formed to expose the membrane 138. The cell contact hole 151 may be formed to expose the etching stopper film 138 at the side of the cell bit line pattern 86. After the cell contact hole 151 is formed, the photoresist film can be removed from the semiconductor substrate 2. [ The contact plug 153 filling the cell contact hole 151 and the capping plug 155 may be formed in order.

The contact plugs 153 may include a conductive material, such as, in turn, a barrier metal layer and tungsten. The barrier metal may be formed in the same manner as the barrier metal of the upper underlying conductive film of FIG. The capping plug 155 may comprise an insulating material, for example, silicon nitride. The capping plug 155 can prevent electrical contact between the contact plug 153 and components formed after the contact plug 153 in advance. The contact plug 153 and the capping plug 155 may constitute a cell contact plug 156.

Next, a photoresist film may be formed on the etching stopper film 138 and the lower interlayer insulating film 145 so as to cover the cell contact plugs 156. The photoresist film may be formed so as to have openings that align with the cell active region 6 in the cell array region C1. The node contact holes 204 can be formed by sequentially etching the lower interlayer insulating film 145, the etching stopper film 138, and the pad film 10 using the photoresist film as an etching mask. The node contact holes 204 may be formed as shown by the cutting lines II-II 'to expose the cell active region 6.

After the node contact holes 204 are formed, the photoresist film can be removed from the semiconductor substrate 2. [ And node plugs 208 may be formed in the node contact holes 204. The node plugs 208 may comprise a conductive material, for example, doped polysilicon. The node plugs 208 may have the same top surface as the cell bit line pattern 86, the peripheral gate pattern 88 and the cell contact plugs 156. An interlayer buffer film (not shown) is formed on the etching stopper film 138 and the lower interlayer insulating film 145 so as to cover the cell bit line pattern 86, the peripheral gate pattern 88, the cell contact plug 156 and the node plugs 208 162 can be formed.

The interlayer buffer film 162 may include an insulating material, for example, silicon oxide. The interlayer buffer film 162 may be formed in the cell array region C1 and the peripheral circuit region P. [ A photoresist film can be formed on the interlayer buffer film 162. The photoresist film may be formed so as to have openings exposing the interlayer buffer film 162 of the peripheral circuit region (P). The openings of the photoresist film may be formed to align with the sides of the peripheral gate patterns 88. The peripheral contact hole 157 can be formed by successively etching the interlayer buffer film 162, the lower interlayer insulating film 145, and the etching stopper film 138 using the photoresist film as an etching mask.

The peripheral contact holes 157 may be formed as shown in the section line IV-IV 'to expose the peripheral active region 8. After the peripheral contact holes 157 are formed, the photoresist film can be removed from the semiconductor substrate 2. Peripheral contact plugs 159 filling the peripheral contact holes 157 may be formed. The peripheral contact plugs 159 may comprise the same material as the contact plugs 153. The peripheral contact plugs 159 do not have the same top surface as the cell bit line pattern 86, the peripheral gate pattern 88, the cell contact plugs 156 and the node plugs 208.

A wiring film 164 and a wiring capping film 174 may be formed on the interlayer buffer film 162 so as to cover the peripheral contact plugs 159. [ The wiring film 164 may include the same material as the peripheral contact plug 159. The wiring cap layer 174 may include an insulating material, for example, silicon nitride.

Referring to FIG. 11, photoresist patterns may be formed on the wiring cap layer 174 of FIG. 10 according to the embodiments. The peripheral bit line patterns 185 may be formed in the peripheral circuit region P by sequentially etching the wiring cap layer 174 and the wiring film 164 using the photoresist patterns as an etching mask. The peripheral bit line patterns 185 may be formed to expose the interlayer buffer film 162. The peripheral bit line patterns 185 may include a peripheral bit line 168 and a peripheral bit line capping pattern 178. After the peripheral bit line patterns 185 are formed, the photoresist patterns may be removed from the semiconductor substrate 2.

The passivation layer 215 may be formed on the interlayer buffer layer 162 so as to cover the peripheral bit line patterns 185. The protective film 215 and the interlayer buffer film 162 may be sequentially penetrated to form the storage nodes 225 in contact with the node plugs 208. [ after that. The upper interlayer insulating film 195 of FIG. 8 may be formed on the upper side of the storage nodes 225 and / or the peripheral bit line patterns 185. The storage nodes 225 are connected to the semiconductor device 100 according to embodiments along with the cell gate patterns 59, the cell bit line pattern 86, the peripheral gate pattern 88 and the peripheral bit line patterns 185. [ (233). Further, the semiconductor device 233 may be replaced by the semiconductor device 236 or 239 of FIG. 2 or 3 according to the embodiments.

1 to 3 are plan views showing semiconductor devices according to embodiments.

4 is a cross-sectional view of a semiconductor device according to embodiments taken along the cutting lines I-I ', II-II', III-III ', and IV-IV' of FIG.

5 to 8 are cross-sectional views illustrating a method of forming a semiconductor device according to embodiments taken along the cutting lines I-I ', II-II', III-III ', and IV-IV' of FIG.

9 to 11 are cross-sectional views illustrating a method of forming a semiconductor device according to embodiments taken along the cutting lines I-I ', II-II', III-III ', and IV-IV' of FIG.

Claims (26)

An inactive region defining first and second active regions of the semiconductor substrate; A first upper wiring disposed on an inactive region around the first active region; A first contact plug having an upper surface at the same level as an upper surface of the first upper wiring and contacting the first active region and the first upper wiring; A second lower wiring disposed on the second active region and having an upper surface at the same level as the upper surface of the first contact plug; A second upper wiring disposed on the second lower wiring; And And a second contact plug in contact with the second upper wiring and the second active region. delete The method according to claim 1, And a first lower wiring crossing the second upper wiring, The first lower wiring protrudes from the upper surface of the semiconductor substrate toward the upper side of the semiconductor substrate and extends from the upper surface of the semiconductor substrate toward the lower side of the semiconductor substrate. The method of claim 3, The first and second lower wirings having different structures and including a gate, Wherein the first lower wiring comprises a selected one of an upper surface having a stepped portion passing through the active region and the inactive region and an upper surface positioned at substantially the same level, and the second lower wiring is made of the same material as the first upper wiring . 5. The method of claim 4, The first lower and upper wirings electrically interacting with the first active region and the first contact plug and the second lower and upper wirings through the second active region and the second contact plug electrically To the semiconductor device. delete 6. The method of claim 5, The first contact plug is inserted into the upper side of the first upper wiring via one end and contacts the non-active region around the first active region and the first active region through the other end. delete delete delete An inactive region disposed in a cell array region and a peripheral circuit region of a semiconductor substrate; Cells and peripheral active regions defined by the inactive regions in the cell array region and the peripheral circuit region; A first wiring located in the cell active area and in an inactive area around the cell active area, a second wiring located on the inactive area around the cell active area and intersecting the first wiring, A cell contact plug having a top surface at a level substantially equal to an upper surface of the second wiring and contacting the cell active region and the second wiring; And A third wiring located on the peripheral active region and having the same material as the second wiring and having an upper surface at the same level as the upper surface of the cell contact plug, And a peripheral contact plug in contact with the peripheral active region and the fourth wiring, The first wiring is selected from a shape partially inserted into the second wiring and passing through the second wiring and a shape passing through the second wiring in contact with the second wiring under the second wiring. 12. The method of claim 11, Wherein the first and third wirings have gates of different structures located at different levels in the semiconductor substrate and the second and fourth wirings are located at different levels in the semiconductor substrate, And said second and third wirings comprise the same material. delete delete 12. The method of claim 11, Wherein the second wiring comprises two lines defining a tipping point, the cell active region is arranged parallel to each of the two lines, and the first wiring is arranged in parallel with the cell active region and the And the second wiring is arranged to be inclined with respect to the second wiring. 12. The method of claim 11, Wherein the second wire comprises two lines defining a point of intersection, the cell active area is disposed parallel to and centered on the point of intersection between the two lines, Is arranged to be inclined with respect to the cell active region and the second wiring. Forming first and second active regions in the semiconductor substrate that are defined as inactive regions, Forming a first upper wiring on the inactive area around the first active area and a second lower wiring on the second active area, A first contact plug for electrically connecting the first active region and the first upper wiring and a second contact plug on the second active region to be positioned around the second lower wiring, And forming a second upper interconnect on the second contact plug. delete delete delete delete delete delete delete delete delete

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