KR101552687B1 - Light receiving apparatus - Google Patents

Abstract

The present invention relates to a light receiving apparatus. The present invention relates to a light emitting device including a light sensing unit for sensing light reflected from a target and converting the light into an input current signal, a preamplifier for converting the input current signal into an output voltage signal, And outputting a digital detection signal by delaying the output start time of the signal by a predetermined fixed delay time from the calculated output start time.

Description

[0001] LIGHT RECEIVING APPARATUS [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving apparatus, and more particularly, to a LADAR (Laser Detection and Ranging) receiving apparatus.

Recently, LADAR technology has been developed to obtain various information about terrain, The LADAR technique emits a pulsed laser toward the target, measures the flight time of the reflected pulsed laser from the target, and then uses the speed of light to derive the distance to the target.

The performance of this LADAR technology is evaluated by sensitivity, multi-target resolution, dynamic range, walk-error, and range accuracy. .

In general, the LADAR receiving apparatus includes a light receiving element such as a photodiode (PD) or an avalanche photodiode (APD), a trans-impedance amplifier (TIA) and a discriminator, .

Here, the TIA converts and amplifies the current signal input from the light receiving element into a voltage signal. The TIA is the analog signal processing configuration that has the greatest impact on the performance of the LADAR receiver. That is, the performance of the LADAR receiving apparatus can be determined according to the specifications such as the gain, noise, recovery time, and operating range of the TIA.

In general, the TIA can be divided into a resistive-feedback TIA (R-TIA) and a capacitive-feedback TIA (C-TIA) according to a method of converting a current signal into a voltage signal in a TIA. R-TIA uses a resistive negative feedback method that uses a resistor as a negative feedback element and converts the current signal into a voltage signal according to Ohm's law. The C-TIA uses a capacitor as a negative feedback element and converts the current signal into a voltage signal according to the charge amount formula.

The C-TIA charges most of the input pulse current into the negative feedback capacitor. Since the voltage charged in the negative feedback capacitor is not discharged automatically even if the current signal is not inputted, a separate circuit for discharging is required. In general, the discharge circuit uses a switching element connected in parallel to the input / output terminal of the C-TIA.

In this case, charge is injected by the parasitic capacitor component in controlling the turn-off operation of the switching element. Since the equivalent resistance value of the input terminal of the TIA is large, the RC time constant is increased and the stabilization time becomes long. Further, even when such a discharge circuit is used, the discharge speed is slower than the charging speed, and the output voltage signal appears as an asymmetric waveform.

On the other hand, due to the linear nature of the resistor, the R-TIA exhibits a similar rise time and fall time of the output voltage signal. That is, the output voltage signal has a substantially symmetrical waveform form. Therefore, it is mainly used in an optical communication system in which a high-speed pulse signal is inputted continuously.

On the other hand, in the LADAR receiving apparatus, the discrimination circuit mainly uses a leading-edge timing discriminator for detecting the rising edge of the output voltage signal of the R-TIA to discriminate the time. However, the magnitude of the pulse signal when the pulse laser signal is reflected from the target and re-incident is greatly changed according to the physical properties such as the distance to the target, the reflection coefficient of the target, and the surface condition.

Therefore, even in the case of the same target having the same distance, the LADAR receiving apparatus can receive reflected pulse signals of different sizes according to the target. In this case, as shown in FIG. 1, when the generation time of the reflected pulse signal is determined by only one fixed threshold voltage Vth, the optical signal A having a relatively large magnitude is converted into the reference voltage Vth, A difference occurs between the time t1 when the optical signal B becomes smaller than the reference voltage Vth and the time t2 when the optical signal B becomes smaller than the reference voltage Vth.

That is, even if the same target is the same distance, a work error may be caused to erroneously determine that the distance between the optical signal B input at a small size is different by the difference between the point of time t1 and the point of time t2.

To solve this problem, a method of controlling the size of the received pulse signal by using automatic gain control (AGC) or a method of controlling the shape of the pulse signal is being developed. However, even if the R-TIA method is applied, it is difficult to apply the present invention to a system requiring a detection distance of several km or more because the reception sensitivity is not sufficiently good and the detection distance is short. Also, the R-TIA method has a lot of noise due to the resistance. In this case, a separate high-performance device must be used to realize low-noise and high-sensitivity R-TIA, which can increase the price.

Therefore, the embodiment of the present invention can provide a light receiving device that can be applied to a system requiring a sensing distance of several km using a C-TIA with a relatively low noise and a low price, and can prevent a work error do.

An embodiment of the present invention relates to a light receiving apparatus, including a light sensing unit for sensing light reflected from a target and converting the light into an input current signal; A pre-amplifier for converting the input current signal into an output voltage signal; And a determination unit for calculating an output starting point of the output voltage signal using the first and second reference voltages and outputting a digital detection signal by delaying the calculated output delay time by a predetermined fixed delay time from the calculated output start point, The preamplifier compares the output voltage signal with a predetermined reset reference voltage during a discharge interval of the output voltage signal, and outputs the output voltage signal in accordance with a comparison result and an output sense signal that senses an output of the digital detection signal. And discharging the electric power to the battery.

Here, the light sensing unit may include a photodiode or an avalanche photodiode.

The preamplifier may include an inverting amplifier for integrating the input current signal to output the output voltage signal; A negative feedback capacitor connected between the input terminal and the output terminal of the inverting amplifier; A negative feedback resistor connected in parallel with the negative feedback capacitor; And a discharger for discharging the current charged to the input terminal of the inverting amplifier by a preset current value during a preset reset duration according to the reset reference voltage and the output sense signal.

Also, the inverting amplifier includes a CMOS inverter connected in at least three stages. The discharger may include a comparator including a non-inverting terminal to which the output voltage signal is input, an inverting terminal to which the reset reference voltage is input, and an output terminal to output a comparison signal; An AND gate for ANDing the comparison signal and the output sense signal; A current source for sinking a current corresponding to the preset current value from the input terminal; And a transistor for connecting the input terminal and the current source according to an output of the AND gate.

The preamplifier further includes a filter unit for filtering a high band of the output voltage signal. The filter unit may further include a high-pass filter for increasing the slope of the output voltage signal with respect to the rising edge.

The preamplifier further includes an amplifier for amplifying, buffering and outputting the output voltage signal. Here, the amplifying unit may include an active load for adjusting the magnitude of the output voltage signal; A common source amplifier for inverting and amplifying an output voltage signal whose magnitude is adjusted by the active load; And a source follower buffer for buffering the inverted amplified output voltage signal.

The determination unit may include a first comparator that compares the output voltage signal with the first and second reference voltages to output first and second comparison signals, respectively; A voltage-time conversion unit for generating a ramp voltage corresponding to a period from an output start time point of the output voltage signal to a time point at which the output voltage signal becomes equal to or greater than a second reference voltage according to the first and second comparison signals; And a second comparator for comparing the ramp voltage with a delay set voltage set to a magnitude corresponding to the fixed delay time and outputting the digital detection signal.

The first comparator may include a first comparator including a non-inverting terminal to which the output voltage signal is input, an inverting terminal to which the first reference voltage is input, and an output terminal to which the first comparison signal is output; And a second comparator including a non-inversion terminal to which the output voltage signal is input, an inversion terminal to which the second reference voltage is input, and an output terminal to which the second comparison signal is output.

The voltage-to-time conversion unit detects a rising edge of each of the output voltage signals in accordance with the first and second comparison signals. The voltage-to-time converter converts the rising edge of the first comparison signal to the rising edge of the second comparison signal, And outputs the ramp voltage rising from a falling edge of the second comparison signal to a second voltage level.

The voltage-time conversion unit may further include: a first current source for supplying a first current; A second current source for supplying a second current; A capacitor for outputting the lamp voltage corresponding to at least one of the first current and the second current; A first switching device selectively turned on according to the first comparison signal to connect the first current source and the capacitor; A second switching element which is selectively turned on in accordance with an inverted signal of the second comparison signal to connect the second current source and the capacitor; And a third switching element that is selectively turned on in response to the inverted signal of the first comparison signal to discharge the lamp voltage charged in the capacitor.

The second reference voltage is set to a voltage level twice as high as the first reference voltage, the first and second currents are set to the same magnitude, and the voltage-to- The voltage level is raised by twice the second voltage level.

The second comparator may include a comparator including a non-inverting terminal to which the ramp voltage is input, an inverting terminal to which the delay setting voltage is input, and an output terminal to which the digital detecting signal is output.

The determination unit may further include a digital signal processing unit for signal processing and discriminating the digital detection signal and calculating a distance to the target.

The optical receiver according to the embodiment of the present invention can be applied to a system requiring a sensing distance of several kilometers using a C-TIA having a relatively low noise and a low price and can prevent a work error to provide.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view for explaining a general optical receiving apparatus; Fig.
2 is a block diagram illustrating an optical receiver according to an embodiment of the present invention.
3 is a detailed circuit diagram showing the light sensing unit 100 and the preamplifier unit 200 shown in FIG.
4 is a detailed circuit diagram showing the discharge unit 214 shown in FIG.
5 is a waveform diagram for explaining the operation of the preamplifier unit 200 according to the embodiment of the present invention.
6 is a detailed block diagram of the determination unit 300 shown in FIG.
7 is a detailed circuit diagram of the first comparing unit 310 shown in FIG.
FIG. 8 is a detailed circuit diagram showing the voltage-time conversion unit 320 and the second comparison unit 330 shown in FIG. 6;
9 to 11 are diagrams for explaining the operation of the determination unit 300 according to the embodiment of the present invention.
12 is a diagram showing an input current signal Iapd, an output voltage signal Vo and a digital detection signal Dout with respect to time;
13 shows I / O delay time according to the magnitude of the input current signal Iapd;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention in the drawings, parts not related to the description are omitted. Like numbers refer to like parts throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between. Also, when a part is referred to as "including " an element, it does not exclude other elements unless specifically stated otherwise.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

2 is a block diagram illustrating an optical receiver according to an embodiment of the present invention.

2, an optical receiver 1 according to an embodiment of the present invention includes a light sensing unit 100, a preamplifier unit 200, and a determination unit 300. Here, the light sensing unit 100 senses input light and converts it into an input current signal Iapd. The input current signal Iapd converted through the light sensing unit 100 preferably includes at least one pulse signal. In the following description, it is assumed that the pulse signal has a square wave form.

To this end, the light sensing unit 100 includes a photodiode PD or an avalanche photodiode APD. An embodiment of the present invention will be described with reference to the case where an avalanche photodiode (APD) having high sensitivity is used for application to a LADAR system for long distance measurement.

The preamplifier 200 receives the input current signal Iapd from the light sensing unit 100 and converts the input current signal Iapd into an output voltage signal Vo. The preamplifier unit 200 corrects the pulse waveform distortion of the converted output voltage signal Vo and amplifies and buffers the output voltage signal Vo to a size that can be discriminated by the determining unit 300 and outputs the amplified output voltage signal Vo.

The determination unit 300 calculates the input time point of the input current signal Iapd using the first and second reference voltages VTH1 and VTH2, that is, the point in time at which the output voltage signal Vo starts to be output, And outputs the digital detection signal Dout by delaying it by a preset fixed delay time. Here, the fixed delay time is a time set corresponding to the delay setting voltage Vdelay.

3 is a detailed circuit diagram showing the light sensing unit 100 and the preamplifier unit 200 shown in FIG.

3, the preamplifier 200 according to an embodiment of the present invention includes a first amplifier 210, a filter 220, and a second amplifier 230. Here, the light sensing unit 100 represents an avalanche photodiode (APD) as an equivalent circuit and includes a current source IS1 for generating an input current signal Iapd output from the avalanche photodiode APD, And a parasitic capacitor Cp connected in parallel with the parasitic capacitor Cp.

The first amplification unit 210 receives the input current signal Iapd from the light sensing unit 100 and converts the input current signal Iapd into an output voltage signal Vo. Here, the first amplifying unit 210 acts as an integrator for integrating and amplifying the input current signal Iapd and outputting the output voltage signal Vo.

The first amplifying unit 210 returns the output voltage signal Vo to the DC bias voltage level through the negative feedback resistor Rf during the discharge period in which the input current signal Iapd is not inputted.

The first amplifying unit 210 according to the embodiment of the present invention amplifies the output voltage signal Vo from the input terminal Nin when the voltage level of the output voltage signal Vo is lower than a predetermined reset reference voltage Vreset And the output voltage signal Vo is returned by a predetermined size. Here, the first amplifying unit 210 may forcibly discharge the output voltage signal Vo after the digital detecting signal Dout is output from the determining unit 300.

Specifically, the first amplifying unit 210 includes an inverting amplifier 212, a negative feedback capacitor Cf, a negative feedback resistor Rf, and a discharging unit 214. The inverting amplifier 212 includes an input terminal Nin that is connected in parallel with the parasitic capacitor Cp and receives the input current signal Iapd and an output terminal Nout that outputs the output voltage signal Vo.

Here, the charge-voltage conversion gain of the inverting amplifier 212 is defined by the following equation (1).

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Here, C is the size of the negative feedback capacitor (Cf), and Q is the amount of charge charged in the negative feedback capacitor (Cf). The size of the parasitic capacitor Cp can be designed to be within a few pF so that current leakage to the parasitic capacitor Cp can be ignored.

In order to calculate the charge-voltage conversion gain as in Equation (1), the inverting amplifier 212 must always maintain a high gain over the frequency band in inverse proportion to the pulse duration of the input current signal Iapd at the operating temperature do.

To this end, the embodiment of the present invention can be constituted by connecting the inverting amplifier 212 to three stages of CMOS inverters having a larger transconductance (Gm) than a common source amplifier or a cascode amplifier.

The negative feedback capacitor Cf charges the electric charge corresponding to the input current signal Iapd. Here, the negative feedback capacitor Cf includes one end connected to the input terminal Nin of the inverting amplifier 212 and the other end connected to the output terminal Nout. The negative feedback capacitor Cf is desirably set to a size of several tens of fF in order to increase the charge-voltage conversion gain.

The negative feedback resistance Rf stabilizes the output voltage signal Vo to the DC bias voltage level. Here, the negative feedback resistance Rf is connected in parallel to the negative feedback capacitor Cf. The auxiliary feedback resistor Rf is a diode (for example, an avalanche photodiode APD) of the light sensing part 100 which is large enough not to affect the noise characteristic of the inverting amplifier 212 and increases as the temperature rises. It is preferable that the resistance value is set to a value that is small enough to compensate the dark current of the light emitting diode. It is also preferable that the negative feedback resistance Rf is set to a resistance value larger than the impedance of the negative feedback capacitor Cf at the maximum operating frequency.

The discharge unit 214 compares the output voltage signal Vo with the reset reference voltage Vreset and outputs a reset signal Sreset when the voltage level of the output voltage signal Vo is lower than the reset reference voltage Vreset as a result of the comparison. And outputs it.

The discharging unit 214 charges the input terminal Nin of the inverting amplifier 212 at a time point when the reset signal Sreset and the output sense signal Sdet are activated simultaneously with a predetermined reset duration Treset, A predetermined current value. Here, the output detection signal Sdet is activated at the time when the output of the digital detection signal Dout from the determination unit 300 is started.

Specifically, the discharger 214 includes a comparator 216, a AND gate AND1, a transistor M1 and a current source IS3, as shown in Fig. The comparator 216 compares the output voltage signal Vo with the reset reference voltage Vreset and outputs a reset signal Sreset.

The comparator 216 includes a non-inverting terminal (+) to which the output voltage signal Vo is input, an inverting terminal (-) to which the reset reference voltage Vreset is inputted, and an output terminal to which the reset signal Sreset is output do.

The AND gate AND1 ANDs the reset signal Sreset with the output sense signal Sdet and outputs the logical product. The transistor M1 is selectively turned on in accordance with the output of the logic sum gate AND1 to connect the input terminal Nin to the current source IS3.

The current source IS3 is connected to the input terminal Nin through the transistor M1 to sink current from the input terminal Nin. Here, it is preferable that the current source IS3 is designed so that the product of the reset duration Treset and the reset duration Treset is capable of canceling the amount of change? Vo of the output voltage signal Vo in the above equation (1) .

That is, the first amplifier 200 according to the embodiment of the present invention amplifies the charge charged in the negative feedback capacitor Cf by using the negative feedback resistance Rf when the size of the received optical signal is small, When the size of the optical signal is large, the charge stored in the negative feedback capacitor Cf is rapidly discharged through the discharge unit 214 to a level close to the DC bias voltage level. Therefore, the stabilization time is shorter than when the switching element is used.

Further, since the forced discharge is performed only when the digital detection signal Dout is output, that is, when the pulse of the input current signal Iapd is sensed, the dead zone, which may occur during the operation of the discharge unit 214, ) Can be minimized. Accordingly, it is possible to easily detect a continuously inputted optical signal and improve the resolution for a plurality of targets.

However, even if the magnitude of the input current signal Iapd is small, the discharge speed of the negative feedback resistor Rf is slow and the input current signal Iapd is again input The discharging unit 214 can operate when the output voltage signal Vo becomes lower than the reset reference voltage Vreset as the charged charges accumulate.

Referring again to FIG. 3, the filter unit 220 corrects the pulse waveform distortion of the output voltage signal Vo and outputs it. Specifically, the filter unit 220 filters the high band of the output voltage signal Vo to reduce the RC time constant for the rising edge of the output voltage signal Vo. That is, the filter unit 220 increases the slope with respect to the rising edge of the output voltage signal Vo to control the rising edge and the falling edge of the output voltage signal Vo to approach a more symmetrical form.

To this end, the filter unit 220 includes a capacitor C1 and a resistor R1. Here, the capacitor C1 includes one end connected to the output terminal Nout and the other end connected to one end of the resistor R1.

The second amplifying unit 230 amplifies and buffers the output voltage signal Vo output from the filter unit 220 and outputs the amplified and buffered output voltage signal Vo. Here, the second amplifying unit 230 may set the gain to be a signal large enough to reduce the discrimination error due to the internal offset voltage when the discriminating unit 300 discriminates the output voltage signal Vo have.

To this end, the second amplifying unit 230 includes a current source IS2, capacitors C2 and C3, a resistor R2, and transistors T1 to T4. Here, the current source IS2 and the capacitor C2 determine the operation currents of the transistor T1 for signal amplification and the transistor T2 for buffering. The transistor T3 constitutes a common source amplifier which inverts and amplifies the output voltage signal Vo whose amplitude is adjusted by the resistor R2 and the transistor T4 buffers the inverted amplified output voltage signal Vo A source follower buffer.

Specifically, the current source IS2 supplies a current of a predetermined magnitude to the drain terminal of the transistor T1. The capacitor C2 includes one end connected to the drain terminal of the transistor T1 and the other end connected between the ground terminal and sets the ground potential for the AC power source AC. The capacitor C3 includes one end connected to the source terminal of the transistor T4 and the other end connected to the output terminal OUT. The resistor R2 includes one end connected to the power supply terminal VDD and the other end connected to the gate terminal of the transistor T3.

The drain terminal and the gate terminal of the transistor T1 are connected to each other, and the gate terminal is connected to the other end of the resistor R1. The source terminal of the transistor T1 is connected to the ground terminal. The gate terminal of the transistor T2 is connected to the other end of the resistor R1, and the drain terminal is connected to the source terminal of the transistor T4. The source terminal of the transistor T2 is connected to the ground terminal.

The drain terminal of the transistor T3 is connected to one end of the resistor R2, and the gate terminal is connected to the other end of the resistor R2. The source terminal of the transistor T3 is connected to the ground terminal. The gate terminal of the transistor T4 is connected to the other end of the resistor R2, and the drain terminal is connected to the power supply terminal VDD. The source terminal of the transistor T4 is connected to one end of the capacitor C3.

5 is a waveform diagram illustrating an operation of the preamplifier unit 200 according to an embodiment of the present invention. 5A is a diagram showing the output voltage signal Vo output from the output terminal Nout of the first amplifier 210 and FIG. 5B is a diagram showing the digital detection signal Dout .

Referring to FIG. 5, when a small-sized input current signal Iapd is input at time point P1, charge is charged in the negative feedback capacitor Cf. Then, the output voltage signal Vo becomes lower by V1 level at the DC bias voltage level. At this time, since the output voltage signal Vo is at a level higher than the reset reference voltage Vreset, the discharger 214 does not operate.

Then, if the input current signal Iapd is no longer inputted, the charge charged in the negative feedback capacitor Cf starts to discharge by the negative feedback resistance Rf from the point P2. Then, the output voltage signal Vo slowly rises to the DC bias voltage level.

On the other hand, when the input current signal Iapd having a large magnitude is input at the time point P4, the output voltage signal Vo is outputted at a level V2 lower than the reset reference voltage Vreset. Then, the reset signal Sreset is activated through the comparator 216.

At this time, since the output of the digital detection signal Dout is completed at the time point P3, the output sense signal Sdet is activated. Then, the transistor M1 is turned on at time point P5, and the charge charged in the feedback capacitor Cf is discharged at a predetermined current value for a preset reset time Treset. Then, the charge remaining in the negative feedback capacitor Cf is almost discharged by the negative feedback resistance Rf, and the output voltage signal Vo rises to the DC bias voltage level.

That is, the preamplifier unit 200 according to the embodiment of the present invention selectively discharges the input current signal Iapd according to the magnitude of the input current signal Iapd by using the negative feedback resistance Rf and the discharge unit 214, thereby minimizing the number of discharges .

6 is a detailed block diagram of the determination unit 300 shown in FIG.

6, the determining unit 300 includes a first comparing unit 310, a voltage-time converting unit 320, a second comparing unit 330, a digital signal processing unit 340, . The first comparing unit 310 compares the output voltage signal Vo output from the preamplifier unit 200 with the first reference voltage VTH1 and the second reference voltage VTH2, (COUT1, COUT2).

According to the first and second comparison signals COUT1 and COUT2, the voltage-to-time conversion unit 320 outputs the output voltage signal Vo equal to or greater than the second reference voltage VTH1 from the start of outputting the output voltage signal Vo And generates a ramp voltage Vramp corresponding to the section from the start of the ramp-up.

Specifically, the voltage-to-time conversion unit 320 detects the rising edge of the output voltage signal Vo according to the first and second comparison signals COUT1 and COUT2 and outputs the rising edge of the first comparison signal COUT1 Rising at the slope of the first voltage level until the rising edge of the second comparison signal COUT2 and rising at the slope of the second voltage level from the rising edge of the second comparison signal COUT2.

The second comparator 330 compares the magnitude of the ramp voltage Vramp and the delay set voltage Vdelay and outputs a digital detection signal Vdelay at a time point when the ramp voltage Vramp becomes equal to or greater than the delay set voltage Vdelay Dout. The digital signal processing unit 340 processes and discriminates the digital detection signal Dout and calculates the distance to the target.

FIG. 7 is a detailed circuit diagram of the first comparing unit 310 shown in FIG.

Referring to FIG. 7, the first comparator 310 includes a first comparator 312 and a second comparator 314. The first comparator 312 compares the output voltage signal Vo with the first reference voltage VTH1 and outputs a first comparison signal COUT1.

To this end, the first comparator 312 compares the non-inverting terminal (+) to which the output voltage signal Vo is input, the inverting terminal (-) to which the first reference voltage VTH1 is input and the first comparison signal COUT1 And output terminals to be output.

The second comparator 314 compares the output voltage signal Vo with the second reference voltage VTH2 and outputs a second comparison signal COUT2. To this end, the second comparator 314 receives a non-inverting terminal (+) to which the output voltage signal Vo is input, an inverting terminal (-) to which the second reference voltage VTH2 is input, and a second comparison signal COUT2 And output terminals to be output.

FIG. 8 is a detailed circuit diagram showing the voltage-time conversion unit 320 and the second comparison unit 330 shown in FIG.

Referring to FIG. 8, the voltage-time conversion unit 320 includes current sources IS4 and IS5, switching devices SW1 to SW3, and a capacitor C4. The current source IS4 is controlled by the switching element SW1 to supply the current I1 to the capacitor C4. The current source IS5 is controlled by the switching element SW2 to supply the current I2 to the capacitor C4. Here, it is preferable that the current I1 and the current I2 have current values of the same magnitude.

The switching element SW1 is connected between the current source IS4 and the capacitor C4 and selectively turned on according to the first comparison signal COUT1. The switching element SW2 is connected between the current source IS5 and the capacitor C4 and is selectively turned on according to the inverted signal / COUT2 of the second comparison signal COUT2.

The capacitor C4 includes one end connected in common to the switching element SW1 and the switching element SW2 and the other end connected between the ground terminal. The ramp voltage Vramp is output corresponding to the charge charged in the capacitor C4 by the current sources IS4 and IS5.

The switching element SW3 is connected in parallel between one end and the other end of the capacitor C4 and is selectively turned on in accordance with the inverted signal / COUT1 of the first comparison signal COUT1. The charge charged in the capacitor C4 is discharged by the switching element SW3.

The second comparing unit 330 includes a comparator 332. [ The comparator 332 includes an inversion terminal (+) to which the ramp voltage Vramp is input, an inversion terminal (-) to which the delay setting voltage Vdelay is input, and an output terminal to which the digital detection signal Dout is output.

9 to 11 are diagrams for explaining the operation of the determination unit 300 according to the embodiment of the present invention. 9 to 11, the solid line corresponds to the output voltage signal Vo_L, and the dotted line corresponds to the output voltage signal Vo_S.

First, the output voltage signal Vo input to the determining unit 300 is inverted by the second amplifying unit 230. When the rising edge of the output voltage signal Vo is the time when the input current signal Iapd is inputted and the falling edge is charged to the negative feedback capacitor Cf by the negative feedback resistance Rf and the discharging part 214, It is the time when the charge is discharged.

That is, in order to grasp the input time point of the input current signal Iapd, the rising edge of the output voltage signal Vo must be detected. Since the preamplifier unit 200 integrates the input current signal Iapd and outputs the output voltage signal Vo, the determination unit 300 outputs the output voltage signal Vo in order to sense the output voltage signal Vo. A delay time occurs until the voltage level of the power source becomes equal to or greater than a certain level.

Therefore, the determination unit 300 according to the embodiment of the present invention uses the output voltage signal Vo to invert the input time point of the input current signal Iapd. Also, the determining unit 300 outputs the digital detection signal Dout after a fixed delay time from the input time point of the input current signal Iapd. In this case, the relative output times of the digital detection signals Dout with respect to a plurality of targets can be made identical regardless of the magnitude of the input current signal Iapd. As a result, the work error can be minimized.

More specifically, as shown in FIGS. 9 and 10, the first comparator 312 compares the first reference voltage VTH1 with the output voltage signal Vo and outputs a first comparison signal COUT1 . At this time, in the case of the output voltage signal Vo_L corresponding to the input current signal Iapd input with a relatively large pulse, the first comparison signal COUT1 has a constant time t1L from the pulse input start time ts Activated at the last minute.

On the other hand, in the case of the output voltage signal Vo_S corresponding to the input current signal Iapd input with a pulse having a relatively small size, the first comparison signal COUT1 has a constant time t1S from the pulse input start time ts Activated at the last minute.

Similarly, the second comparator 314 compares the second reference voltage VTH2 with the output voltage signal Vo and outputs a second comparison signal COUT2. At this time, in the case of the output voltage signal Vo_L, the second comparison signal COUT2 is activated after a predetermined time t2L from the pulse input start time ts. On the other hand, in the case of the output voltage signal Vo_S, the second comparison signal COUT2 is activated after a predetermined time t2S from the pulse input start time ts.

Here, assuming that the second reference voltage VTH2 is set to be twice the first reference voltage VTH1, a relational expression as shown in the following equation (2) holds.

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It can be seen that the pulse input start time ts corresponds to the difference between the time t1n and the time t2n. That is, assuming that the time passes by twice the time difference (t2n-t1n), the pulse input start time ts can be estimated.

To implement this, the voltage-time converter 322 charges the capacitor C4 with twice the current value from the time t1n to the time t2n, as shown in Fig. That is, the switching elements SW1 and SW2 are simultaneously turned on from the time t1n to the time t2n to charge the capacitor C4 with the charge corresponding to the current I1 and the current I2.

At this time, after the time tn2, the voltage-time converter 322 turns off the switching element SW2, and charges corresponding to the current I1 are charged in the capacitor C4. The digital detection signal Dout is output through the delay unit 324 at the time td when the ramp voltage Vramp charged in the capacitor C4 becomes equal to or greater than the delay set voltage Vdelay.

That is, since the difference between the fixed delay time tout and the pulse input time ts set by the delay setting voltage Vdelay is constant regardless of the magnitude of the input current signal Iapd, a work error can be prevented.

12 shows an input current signal Iapd, an output voltage signal Vo and a digital detection signal Dout with respect to time. FIG. 13 shows an I / O delay time according to the magnitude of the input current signal Iapd Fig.

Referring to FIG. 12, it is possible to determine a work error with respect to the waveform of the input current signal Iapd by the time between the output time of the digital detection signal Dout from the actual input time, that is, the I / O delay time.
As shown in FIG. 13, when the magnitude of the input current signal Iapd is MDS (minimum detectable signal), the I / O delay time when the embodiment of the present invention is applied is greatly reduced as compared with the conventional comparative example. The difference between the I / O delay time corresponding to the MDS and the I / O delay time corresponding to 400MDS in the I / O delay time according to the embodiment is 2.8 ns, which is a very short time compared to about 7.3 ns in the conventional comparative example.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

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Claims (16)

A light sensing unit for sensing light reflected from the target and converting the light into an input current signal;
A pre-amplifier for converting the input current signal into an output voltage signal; And
The output start time of the output voltage signal is calculated using the time point at which the output voltage signal reaches the first reference voltage and the second reference voltage and the output start time of the output voltage signal is delayed by a predetermined fixed delay time from the calculated output start time And a determination section for outputting a digital detection signal,
The pre-
And comparing the output voltage signal with a predetermined reset reference voltage during a discharge interval of the output voltage signal, and discharging the output voltage signal according to an output detection signal that senses an output of the digital detection signal, And a light source for emitting the light. The method according to claim 1,
The light sensing unit
And a photodiode or an avalanche photodiode. The method according to claim 1,
The pre-
An inverting amplifier for integrating the input current signal to output the output voltage signal;
A negative feedback capacitor connected between the input terminal and the output terminal of the inverting amplifier;
A negative feedback resistor connected in parallel with the negative feedback capacitor; And
And a discharging unit for discharging the current charged in the input terminal of the inverting amplifier by a preset current value during a predetermined reset duration according to the reset reference voltage and the output detection signal,
And a light receiving device for receiving the light. The method of claim 3,
The inverting amplifier
And a CMOS inverter connected in at least three stages. The method of claim 3,
The discharge unit
A comparator including a non-inversion terminal to which the output voltage signal is input, an inversion terminal to which the reset reference voltage is input, and an output terminal to output a comparison signal;
An AND gate for ANDing the comparison signal and the output sense signal;
A current source for sinking a current corresponding to the preset current value from the input terminal; And
And a transistor connected between the input terminal and the current source in accordance with an output of the AND gate,
And a light receiving device for receiving the light. The method of claim 3,
The pre-
Further comprising a filter unit for filtering a high band of the output voltage signal. The method according to claim 6,
Wherein the filter section comprises a high-pass filter for increasing the slope with respect to the rising edge of the output voltage signal. The method of claim 3,
The pre-
And an amplifier for amplifying, buffering and outputting the output voltage signal. 9. The method of claim 8,
The amplifying unit
A load regulating a magnitude of the output voltage signal;
A common source amplifier for inverting and amplifying the output voltage signal scaled by the load; And
A source follower buffer for buffering the inverted amplified output voltage signal;
And a light receiving device for receiving the light. The method according to claim 1,
The determination unit
A first comparator comparing the output voltage signal with the first and second reference voltages to output first and second comparison signals;
A voltage-time conversion unit for generating a ramp voltage corresponding to a period from an output start time point of the output voltage signal to a time point at which the output voltage signal becomes equal to or greater than a second reference voltage according to the first and second comparison signals; And
A second comparison unit for comparing the ramp voltage with a delay set voltage set to a magnitude corresponding to the fixed delay time and outputting the digital detection signal,
And a light receiving device for receiving the light. 11. The method of claim 10,
The first comparing unit
A first comparator including a non-inversion terminal to which the output voltage signal is input, an inversion terminal to which the first reference voltage is input, and an output terminal to which the first comparison signal is output;
A second comparator including a non-inverting terminal to which the output voltage signal is input, an inverting terminal to which the second reference voltage is input, and an output terminal to which the second comparison signal is output,
And a light receiving device for receiving the light. 11. The method of claim 10,
The voltage-time conversion unit
The rising edge of each of the output voltage signals is detected in accordance with the first and second comparison signals and is increased to a first voltage level from a rising edge of the first comparison signal to a rising edge of the second comparison signal, And outputs the ramp voltage rising from the falling edge of the second comparison signal to the second voltage level. 13. The method of claim 12,
The voltage-time conversion unit
A first current source for supplying a first current;
A second current source for supplying a second current;
A capacitor for outputting the lamp voltage corresponding to at least one of the first current and the second current;
A first switching device selectively turned on according to the first comparison signal to connect the first current source and the capacitor;
A second switching element which is selectively turned on in accordance with an inverted signal of the second comparison signal to connect the second current source and the capacitor; And
A third switching element for selectively turning on according to an inverted signal of the first comparison signal to discharge the ramp voltage charged in the capacitor,
And a light receiving device for receiving the light. 14. The method of claim 13,
The second reference voltage is set to a voltage level twice as high as the first reference voltage, the first and second currents are set to the same magnitude,
The voltage-time conversion unit
And raises the first voltage level of the lamp voltage by two times the second voltage level. 11. The method of claim 10,
The second comparing unit
And a comparator including a non-inverting terminal to which the ramp voltage is input, an inverting terminal to which the delay setting voltage is input, and an output terminal to which the digital detection signal is output. 11. The method of claim 10,
The determination unit
Further comprising a digital signal processing unit for signal processing and discriminating the digital detection signal and calculating a distance to the target.

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