KR101565795B1 - Semiconductor apparatus having optical connections between central processing unit and memory module - Google Patents

Abstract

A semiconductor device having an optical connection between a central processing unit (CPU) and a memory module is disclosed. The disclosed semiconductor device includes a photoelectric module connected to a memory controller, one of which is connected to the photoelectric module and the other of which is a light channel extending through a socket on which the memory module is mounted, Module or an optical connector.

Description

Technical Field [0001] The present invention relates to a semiconductor device having an optical connection between a central processing unit and a memory module,

To a semiconductor device having an optical connection between at least two components.

As the connection speed between the central processing unit and the main memory module increases, the number of memory modules, for example, DIMMs (Dual Inline Memory Modules), which can be connected to one CPU is decreasing. When the memory module is DDR3 class, the number of DIMMs that can be connected to one CPU by current electrical connection is about two.

This limitation arises because the signal integrity state is degraded by impedance mismatch that occurs when an electrical signal is sent to various modules.

The present invention provides a semiconductor device having an optical connection capable of high-speed data transfer without affecting transmission data and capable of increasing the number of memory modules capable of stable connection.

A semiconductor device having an optical connection according to an embodiment of the present invention includes a memory controller, a memory module connected to the memory controller, a socket on which the memory module is mounted, a first photoelectric module connected to the memory controller, And a second photoelectric module connected between the optical channel and the memory module, wherein the second photoelectric module is connected to the optical channel, And the second photoelectric module provides the semiconductor device provided in the socket.

The second photoelectric module may be provided on a bottom surface of the socket to face the optical channel.

And a plurality of optical splitters may be further provided between the memory controller and the socket.

A semiconductor device according to another embodiment of the present invention includes a memory controller, a memory module connected to the memory controller, and a socket to which the memory module is mounted, the semiconductor device comprising: a first photoelectric module connected to the memory controller; A system board on which at least some of the components are mounted, a branching and coupling unit for optical signals between the optical channel and the memory module, And a first optical connector for transmitting an optical signal of either the optical coupler or the memory module to the other side, wherein the optical connector is provided in the socket.

And an optical connector may be further provided between the first photoelectric module and the socket.

And a second optical connector for transmitting the optical signal of either one of the first optical connector and the memory module to the other.

And a second photoelectric module for converting signals of either the second optical connector or the memory chip between the second optical connector and a plurality of memory chips mounted on the memory module and transferring the signal to the other.

The second optical connector is provided in the memory module so as to be coupled to the first connector, and the memory module and the socket may be provided with means for fixing the memory module.

A plurality of optical splitters may be provided between the first photoelectric module and the socket. At this time, at least two memory module groups are connected to the optical distributor, and each memory module group may include a plurality of memory modules.

A semiconductor device according to another embodiment of the present invention includes a memory controller, a memory module connected to the memory controller, and a socket to which the memory module is mounted, the semiconductor device comprising: a first photoelectric module connected to the memory controller, A system board on which at least some of the components are mounted, a branching and coupling of optical signals between the optical channel and the memory module, And a second photoelectric module optically connected to the photo coupler and provided between the memory chip included in the memory module and the photo coupler, and the second photoelectric module is connected to the memory module, And a semiconductor device provided at a lower end of a portion to be inserted into the socket.

The socket is provided with a hole through which the second photoelectric module passes, and the second photoelectric module side of the socket can be opened.

A plurality of optical splitters may be provided between the first photoelectric module and the socket.

At least two memory module groups are connected to the optical distributor, and each memory module group may include a plurality of memory modules.

And a buffer chip may be provided in the memory module as one group with the second photoelectric module.

A semiconductor device according to another embodiment of the present invention includes a memory controller, a memory module connected to the memory controller, and a socket to which the memory module is mounted, the semiconductor device comprising: a first photoelectric module connected to the memory controller, A system board on which at least some of the components are mounted; a light source for splitting a part of the optical signal of the optical channel into the memory module; An optical system for transmitting an optical signal divided from the optical splitter to a memory chip included in the memory module, and a second photoelectric module for converting a signal between the optical system and the memory chip and transmitting the signal to the other side, A semiconductor device is provided.

The light splitter may be a light reflector that reflects a portion of the incident light and the remainder.

Wherein the optical system includes a first optical system including a first micro-ball lens through which light is incident from the light splitter, a second micro-ball lens through which light is incident from the first optical system, and a second optical system including a reflection surface, And a third micro-ball lens through which the light reflected from the third micro-ball lens is incident.

The first optical system may be provided on the inner side of the socket so as to align the optical axis with the optical splitter.

The second optical system is provided in the memory module so as to be optically aligned with the first optical system, and the memory module can be mounted on the first optical system inside the socket.

The third optical system may be configured as a package with the memory chip so that optical axis alignment with the second optical system is performed.

The second photoelectric module may be included in the memory chip.

The photoelectric module may include a modulator using silicon photonics technology, a photodiode, and an external light source.

A plurality of optical splitters may be provided between the first photoelectric module and the optical splitter.

In the semiconductor device according to the above-described embodiment, the memory controller and the first photoelectric module may form a CPU package, and the memory controller and the first photoelectric module may be provided on the same board or on different boards . The optical connector may further include an optical connector that is optically connected to the first photoelectric module between the CPU package and the socket. Further, an electric wiring may be further provided between the memory controller and the socket.

Data can be transferred at high speed without data corruption or loss, and the number of memory modules connectable per CPU can be increased.

Hereinafter, a semiconductor memory device having an optical connection between a central processing unit and a memory module according to an embodiment of the present invention will be described in detail. In this process, the thicknesses of the layers or regions shown in the figures are exaggerated for clarity of the description.

Referring to FIG. 1, a semiconductor memory device having an optical connection according to an embodiment of the present invention includes a memory controller 10 mounted on a system board 8, a first photoelectric module an optional module 12 and a plurality of sockets 16 (1) -16 (n), n being 1, 2, 3,. The memory controller 10 may include a CPU. The CPU may be separately provided to be connected to the memory controller 10. The first photoelectric module 12 may include a light emitting element, a light receiving element, and a photoelectric conversion circuit. The memory controller 10 and the first photoelectric module 12 are connected by a plurality of wires 20 (1) -20 (n), n being 1, 2, 3,. The first photoelectric module 12 and the memory controller 10 may form the CPU package 11. [ The first photoelectric module 12 and the plurality of sockets 16 (1) -16 (n) are connected to a plurality of transmission paths 22 (1) -22 (n), n is 1, 2, 3 ...) Can be connected. The memory modules 16 (1) M-16 (n) M) can be mounted on each of the plurality of sockets 16 (1) to 16 (n). The plurality of transmission paths 22 (1) to 22 (n) may be optical links, for example, optical fibers or optical waveguides. As described above, since information transfer between the memory controller 10 and the memory modules 16 (1) M-16 (n) M is made of optical signals instead of electrical signals, a large amount of information can be transferred at high speed. Some of the plurality of transmission paths 22 (1) to 22 (n) may be electrical wiring. Power can be supplied to the memory modules 16 (1) M-16 (n) M) via the electric wiring, and electric power can be supplied to the memory modules 16 (1) M- (n) M) can be supplied with electric power necessary for operation. The second photoelectric module will be described later. Four guide pins 26 for aligning the memory modules 16 (1) M-16 (n) M) are provided in the respective sockets 16 (1) to 16 (n). This guide pin 26 allows optical alignment with electrical and mechanical alignment between the memory modules 16 (1) M-16 (n) M and the sockets 16 (1) -16 (n) . Sockets 16 (1) -16 (n) may have a different form from that shown in FIG. The position of the guide pin 26 may also be different from that shown in FIG. The memory modules 16 (1) M-16 (n) M) may be a dual in-memory module (DIMM) or a single in-memory module (SIMM).

FIG. 2 shows a cross section of FIG. 1 taken along line 2-2 '.

Referring to Fig. 2, the second photoelectric module 30 is mounted integrally with the socket 16 (1). The second photoelectric module 30 is mounted on the bottom surface of the socket 16 (1). The second photoelectric module 30 is spaced apart from the system board 8. The socket 16 (1) is downwardly extended to both sides of the second photoelectric module 30 and mounted on the system board 8. [ The optical signal of the optical transmission path 22 (2) is branched to the second photoelectric module 30 and the optical signal of the second photoelectric module 30 is transmitted between the second photoelectric module 30 and the system board 8 And an optical coupler (not shown) for coupling the optical path 22 (2) to the optical path 22 (2). The first contact member C1 is provided on both sides of a portion of the memory module 16 (1) M to be inserted into the socket 16 (1). A second contact member C2 is provided on an inner surface of an area where the memory module 16 (1) M of the socket 16 (1) is inserted in. The second contact member C2 is connected to the second photoelectric module 30, The first contact C1 is in contact with the second contact C2 when the memory module 16 (1) M is fitted in the socket 16 (1). The first memory chip M1 is mounted on one side of the memory module 16 (1) and the second memory chip M2 is mounted on the opposite side of the memory module 16 (1) A plurality of memory chips such as the memory chip M1 may be mounted on the opposite side of the memory module 16 (1).

A part of the optical signal 34 transmitted from the memory controller 10 through the optical transmission line 22 (2) is divided by the optical divider 23 located on the optical transmission line 22 (2) And passes through the light splitter 23. The light splitter 23 may be, for example, a prism. The traveling path of the light divided by the light splitter 23 is shifted upward and is incident on the second photoelectric module 30. The optical signal incident on the second photoelectric module 30 is converted into an electric signal and is transferred to the first memory chip M1 or the second memory chip M2 of the memory module 16 (1) M. At this time, the optical signal 34 may be high-speed data such as a data write signal or a clock signal. The optical signal 34 may be low speed data such as an instruction or an address. On the other hand, the electric signal generated from the memory module 16 (1) M is converted into an optical signal by the second photoelectric module 30. The thus changed optical signal 34 is transmitted to the second photoelectric module 12 through the optical path 22 (2), converted into an electric signal by the first photoelectric module 12, and transmitted to the memory controller 10 do. The optical signal 34 at this time may be a read signal and may be information including the state of the first memory chip M1 or the second memory chip M2.

3 shows a semiconductor memory device having an optical connection according to another embodiment of the present invention.

Referring to FIG. 3, the memory controller 10 mounted on the system board 8 (or main board) includes a CPU 10b and a first photoelectric module 10C. The first photoelectric module 10C may include a light source, for example, a laser diode therein. The first photoelectric module 10C may include the light source LS outside the first photoelectric module 10C but inside the memory controller 10. [ The CPU and the first photoelectric module 10C are connected by a plurality of electric wiring lines 10d. A first optical connector 13 and a plurality of sockets 40 (1) -40 (n) are mounted on the system board 8. The first optical connector 13 and the first photoelectric module 12 are connected by a plurality of optical channels OPL. The memory modules 40 (1) M-40 (n) M) are mounted on each of the plurality of sockets 40 (1) -40 (n). The first optical connector 13 and the first socket 40 (1) are connected by a plurality of optical channels L1-Ln. Optical couplers 42 (1) to 42 (n) are connected before each of the sockets 40 (1) to 40 (n) of the optical channels L1 to Ln. Ln may be a polymer waveguide or an optical fiber. The optical channels L1-Ln may be provided on the system board 8 or in the system board 8. Such optical channels L1-Ln Are connected to the last socket 40 (n). By the optical couplers 42 (1) -42 (n), the optical signals are separated into two sockets and the optical signals from the two sockets are combined The optical couplers 42 (1) to 42 (n) are not provided in the last socket 40 (n) and the optical couplers 42 (1) to 42 (n) .

FIG. 4 shows a cross section of FIG. 3 taken along line 4-4 '.

Referring to FIG. 4, a first socket 40 (1) is mounted on the system board 8. A second optical connector OC2 is provided in the first socket 40 (1). A second optical connector (OC2) is provided in the first socket 40 (1) OC2 are embedded in the trench T1 of the first socket 40. The second optical connector OC2 is provided on the upper surface of the first socket 40 The third optical connector OC3 is connected to the second optical connector OC2 The third optical connector OC3 is connected to the memory module 40 OC3 is provided at the lower end of the memory module 40 (1) M. The lower end of the memory module 40 (1) M faces the second optical connector OC2. The first and second memory chips M 1 and M 2 (M2) are provided on both sides of the memory module 40 (1) M, respectively. ), For example, a DRAM is mounted. A memory (not shown) between the first memory chip M1 and the third optical connector OC3 The second photoelectric module 48a is mounted on the re-module 40 (1) M and the memory module 40 (1) M between the second memory chip M2 and the third optical connector OC3 The third optical connector 48 is connected to the third optical connector OC3 and the second and third photoelectric modules 48a and 48b through the optical channel L 11. The first optical connector 13, The optical channel Ln connected to the optical coupler 42 (n) in the optical coupler 42 (n) is branched into two optical channels Ln1 and Ln2 by the optical coupler 42 (n) Is connected to the second optical connector OC2 and the remaining one channel Ln1 is connected to the next socket.

Fig. 5 shows a front view of the memory module 40 (1) M of Fig. 4, that is, a surface on which the photoelectric module is mounted.

Referring to FIG. 5, a third optical connector OC3 is mounted on a lower end of the memory module 40 (1) M, that is, a portion mounted on the socket 40 (1). And the second photoelectric module 48a is mounted on the memory module 40 (1) M above the third optical connector OC3. It can be seen that the third optical connector OC3 and the second photoelectric module 48a are connected by a plurality of optical channels L11. A plurality of first memory chips M1 are mounted on the memory module 40 (1) M above the second photoelectric module 48a. The second photoelectric module 48a and the plurality of first memory chips M1 are connected to each other by an electric wiring 62. [ First and second contact portions 64 and 66 are present at both ends of the lower end of the memory module 40 (1) M. The first and second contact portions 64 and 66 are portions for power supply voltage connection and ground, respectively. The operating power is supplied to the second photoelectric module 48a and the plurality of first memory chips M1 through the first contact portion 64. [ The same configuration as described above may exist on the surface of the memory module 40 (1) M on which the second memory chip M2 is mounted.

6 schematically shows a configuration of a semiconductor device having an optical connection according to another embodiment of the present invention.

Referring to FIG. 6, the memory controller 70 and the first photoelectric module 72 are integrated to form a CPU package. The first photoelectric module 72 is connected to a plurality of sockets 80 (1) -80 (n) through a light channel 76. The plurality of sockets 80 (1) -80 (n) are connected to the optical channel 76 through the second photoelectric module 82 provided in each of the sockets 80 (1) -80 (n). 7 shows a cross section of the CPU package in which the memory controller 70 and the first photoelectric module 72 are integrated.

Referring to FIG. 7, there is a CPU package 68 on the system board 8. The package 68 includes a memory controller 70 and a first photoelectric module 72 including a CPU on a CPU board 68B. The memory controller 70 and the first photoelectric module 72 are connected by an electric wiring 68C. The memory controller 70, the first photoelectric module 72, and the electric wiring 68C are covered with a protection layer 68D. A light channel 76 is formed in the board 8. The optical channel 76 may be in the form of a groove in the board 8, but may also be a polymer optical waveguide or optical fiber present on the surface of the board 8. The optical signal 78 emitted from the first photoelectric module 72 is transmitted to the memory module 80 (1) M-80 (n) M through the optical board 76 through the CPU board 68B. The optical signal 78 transmitted from the memory module 80 (1) M-80 (n) M passes through the CPU board 68B and is incident on the first photoelectric module 72, And transferred to the memory controller 70.

8, although the memory controller 70 and the first photoelectric module 72 are on the same CPU board 68B, the first photoelectric module 72 is separated from the CPU package 68 . At this time, the memory controller 70 and the first photoelectric module 72 are connected by the electric wiring 68C and operate in the same manner as in Fig.

On the other hand, in the CPU package 68 of FIG. 7, the first photoelectric module 72 may be provided outside the CPU package 68, and may be mounted on a board other than the CPU board 68B. Fig. 9 shows an example of this.

Referring to Fig. 9, a CPU package 68 including a memory controller 70 is mounted on a system board 8. A first photoelectric module 72 is mounted on the system board 8. The CPU package 68 and the first photoelectric module 72 are spaced apart from each other and are connected by an electric wiring 68C. To transfer the optical signal (78) converted from the electric signal transferred from the CPU package (68) to the first photoelectric module (72) to the memory module or to transfer the optical signal transferred from the memory module to the first photoelectric module And an optical channel 80 for transmission is connected. The optical channel 80 is provided on the system board 8.

The configuration relationship between the memory controller 70 and the first photoelectric module 72 shown in Figs. 7 to 8 can be applied to other embodiments as well.

10 is a plan view showing an example of the memory module 80 (1) of Fig.

10, a plurality of transmission lines 74, 76, 77 pass under the optical coupler 86 and the socket 80 (1). The plurality of transmission lines 74, 76, and 77 may include electrical wirings 74 and 77 and may include optical channels 76 or 80. Reference numeral 80 (1) M denotes a memory module mounted on the socket 80 (1). And reference numeral 79 may be a guiding means for mechanically, electrically and optically aligning the memory module 80 (1) M.

FIG. 11 shows a cross section of FIG. 10 taken along the line 11-11 '.

11, there is an optical coupler 86, a memory module 80 (1) M, and a socket 80 (1) over the optical channel 76 provided in the system board 8. [ The memory module 80 (1) M is brought into contact with the board 8 through the through hole 94 formed in the socket 80 (1). A second photoelectric module 88 is mounted on the first lower surface of the memory module 80 (1) M. A buffer chip (90) is present on the first surface integrally or in a package with the second photoelectric module (88). The first surface may be a surface facing the optical coupler 86. The optical coupler 86 and the second photoelectric module 88 are optically connected. 12 is a plan view of only the socket 80 (1). 12, the through hole 94 of the socket 80 (1) has a first through hole 94a through which the body of the memory module 80 (1) M passes and a first through hole 94a through which the body of the memory module 80 (1) And a second through hole 94b through which the buffer chip 90 passes. The second through hole 94b may be smaller than the first through hole 94a and a part of the first through hole 94a may protrude outward.

13 shows a semiconductor memory device having an optical connection according to another embodiment of the present invention. In Fig. 13, the memory controller or the CPU package may be as shown in Figs. 1, 3, or 7-9. Therefore, the description of the memory controller or the CPU package is omitted.

Referring to FIG. 13, a system board 8 is provided with a light channel 96. A light reflector 98 is provided on the optical channel 96 path. The reflector 98 may be a reflector that allows some of the incoming light 78 to pass through and the remainder to the memory module 100M. The reflector 98 may be a prism, a light splitter, or the like. The socket 100, the optical alignment medium 102, and the memory module 100M are present on the optical channel 96. The optical alignment medium 102 is provided inside the socket 100. The optical alignment medium 102 may be a first optical system. The optical alignment medium 102 includes a first vertical optical waveguide 108. The first vertical optical waveguide 108 may be a waveguide. A first micro-ball lens 104 is provided on the first vertical optical waveguide 108. The first micro-ball lens 104 collimates the light reflected from the light reflector 98 with a collimating lens. Accordingly, the optical alignment medium 102 can be provided such that the optical axis of the first micro-ball lens 104 can meet on the reflection surface of the optical reflector 98 with the optical axis. The memory module 100M is mounted on the optical alignment medium 102 inside the socket 100. [ The socket 100 and the memory module 100M may have guiding means (not shown) for optical alignment on both sides. The memory module 100M includes a second vertical optical waveguide 116 therein. The second vertical waveguide 116 may be a waveguide. The second vertical optical waveguide 116 may be provided to have continuity with the first vertical optical waveguide 108. The second micro-ball lens 106 is provided on the second vertical optical waveguide 116. The second micro-ball lens 106 focuses the light incident on the first micro-ball lens 104 to focus on the upper reflection surface S1 of the second optical waveguide. The light reflected by the reflective surface S1 is incident on the photoelectric module 112 built in the memory chip M11 through the window 120. [ The second vertical optical waveguide 116, the second micro-ball lens 106, and the reflecting surface S1 may form a second optical system. A window 120 may be included in the second optical system. The memory module 100M may be optically aligned so that the second micro-ball lens 106 is located on the same optical axis as the first micro-ball lens 104. [ A memory chip M11 is mounted on the first surface of the memory module 100M. The memory chip M11 may include a memory die 114, a photoelectric module 112, and a third micro-ball lens 110. The third micro-ball lens 110 may be a third optical system. The outside of the memory die 114, the photoelectric module 112, and the third micro-ball lens 110 is covered with a protective layer 119. A plurality of memory elements (not shown) are present in the memory die 114. A photoelectric module 112 may be provided on the memory die 114 together with a plurality of memory devices. The photoelectric module 112 may include a silicon III-V compound semiconductor laser and a light receiving element, but may instead comprise a modulator made of silicon photonics, an external light source (III-V compound Semiconductor laser). The third micro-ball lens 110 reflects from the reflection surface S1 of the second modification optical waveguide 116 and makes incident light incident on the photoelectric module 112. [ And converges the light incident from the photoelectric module 112 onto the reflecting surface S1 of the second vertical optical waveguide 116. [ The memory chip M11 can be mounted after being optically aligned so that the optical axes of the second and third micro-ball lenses 106 and 110 can meet at the reflecting surface S1. The third micro-ball lens 110 may form a package with the memory chip M11.

14 and 15 show an example of distributing an optical signal to a plurality of memory modules in a semiconductor memory device according to embodiments of the present invention.

Reference numeral 2 (n) (n = 1, 2, 3...) In FIG. 14 represents an optical distributor for distributing light from the first photoelectric module 12 connected to the memory controller to each memory module. The first optical splitter 2 (1) is connected to the first photoelectric module 12 through a first optical channel 2L1. The n-th optical distributor 2 (n) is connected to the first photoelectric module 12 and the n-th optical channel 2Ln. Accordingly, the number of optical distributors may be equal to the number of optical channels connected to the first photoelectric module 12. The first optical splitter 2-1 divides the optical signal transmitted through the first optical channel 2L1 into the same number as the number of the memory modules 3 (1) M-3 (n) M, 3 (1) M-3 (n) M). The optical signal transmitted from the first optical splitter 2 (1) is transmitted to each of the memory modules 3 (1) (1) M-3 (n) M via the first channel 52L1, 52Ln of the memory module 3 (1). Similarly, the n-th optical distributor 2 (n), which is the last optical distributor, divides the optical signal transmitted through the n-th optical channel 2Ln into the same number as that of the memory module 3 (1) M-3 3 (1) M-3 (n) M through the last channels 50L1, 50Ln of the respective memory modules 3 (1) M-3 (n) Reference numerals 3 (1) -3 (n) denote a socket to which each memory module is mounted.

Fig. 15 shows a case where Fig. 3 and Fig. 14 are combined.

15, the optical distributor 2 (1) 1-2 (1) n divides the optical signal transmitted from the optical channels 2L1-2Ln of the first photoelectric module 12 into two Signal to the first memory module group G1 and the other signal to the second memory module group G2. Therefore, one of the two optical signals divided by the first optical splitter 2 (1) 1 is transmitted to the first channel Ch1 of the first memory module group G1. The optical signals are transmitted to the first through n-th memory modules 3 (1) M-3 (n) M through the first channel Ch1. Each of the memory modules 3 (1) M- ) Is branched to each memory module 3 (1) M-3 (n) M by the optical coupler 42 (1). The other one of the two optical signals divided by the first optical splitter 2 (1) 1 is connected to the first through the n-th memory modules 5 (1 (1) 1) through the first channel Ch11 of the second memory module group G2 (1) M-5 (1) nM by the optical coupler 45 (1) before each memory module 5 (1) M- 5 (1) nM).

Similarly to the first optical distributor 2 (1) 1, the optical signals divided into two by the n-th optical distributor 2 (1) n are supplied to the first and second memory module groups G1 and G2, (Chn, Chnn) of the memory modules 3 (1) M3 (n) M and 5 (1) M5 (n) M included) 1) n, 45 (1) n). In this way, more memory modules can be connected to one CPU without lowering the transfer speed, which can increase the memory capacity.

The above-described optical distributors can be applied to all the semiconductor devices having the optical connection described above.

16 shows an example of an optical connector.

Referring to FIG. 16, the optical connector includes a lower connector 140 and an upper connector 160. The lower connector 140 may be provided on the socket side, and the upper connector may be provided on the memory module side. Or vice versa. The upper connector 160 is provided with a support 144 for fixing the optical channel 146 on the surface of the substrate 150 facing the lower connector 140. The upper and lower connectors 160 and 140 A rubber seal 142 is provided to prevent penetration of moisture or dust after bonding. A guide pin 148 for optical alignment of the upper and lower connectors 160 and 140 is provided on the bottom edge of the substrate 150. There may be a groove (not shown) in which the guide pin 148 is received in the lower connector 140.

Although a number of matters have been specifically described in the above description, they should be construed as examples of preferred embodiments rather than limiting the scope of the illustrated memory devices. For example, a person skilled in the art will be able to modify the optical connector or the optical coupler in various forms. In addition, the optical channel branching method may be variously modified. Therefore, the scope of the semiconductor device having the illustrated optical connection is not to be determined by the described embodiment but should be determined by the technical idea described in the claims.

1 is a plan view of a semiconductor device having an optical connection according to an embodiment.

FIG. 2 is a cross-sectional view of FIG. 1 taken along line 2-2 '.

3 is a plan view of a semiconductor device having an optical connection according to another embodiment of the present invention.

4 is a cross-sectional view of a portion cut along the line 4-4 'of FIG.

Fig. 5 is a front view of a surface of the memory module of Fig. 4 on which the second photoelectric module is mounted.

Fig. 6 is a schematic diagram showing a configuration of a semiconductor device having an optical connection according to another embodiment of the present invention.

Figs. 7 to 9 are cross-sectional views illustrating various connection relationships between the memory controller and the first photoelectric module.

10 is a plan view of the socket, memory module and optical channel portion of the semiconductor device shown in Fig.

11 is a cross-sectional view taken along the line 11-11 'of FIG.

12 is a plan view of a socket on which the memory module of Fig. 11 is mounted.

13 is a cross-sectional view of a semiconductor device having an optical connection according to another embodiment of the present invention.

14 and 15 are plan views showing various connections between the optical distributor and the memory module.

16 shows an example of an optical connector according to an embodiment of the present invention.

Description of the Related Art [0002]

2 (1) -2 (n), 2 (1) 1-2 (1) n:

40 (n), 40 (n), 80 (1) -80 (n), 100: Socket

5 (1) M-5 (1) Nm, 3 (1) M-3 (n) M, 16 (1) M- 1) M-80 (n) M: First to nth memory modules

2L1-2Ln, 76, 50L1-50Ln, 52L1-52Ln, 76, 80, 96, 146, L1-Ln, L11, Ln1,

8: System board 10,70: Memory controller

10B: CPU 10C, 12, 72: first photoelectric module

10D, 62, 68C, 74, 77: electric wiring 13: optical connector

20 (1) -20 (n): Wiring 22 (1) -22 (n)

23: optical splitter 26, 148: guide pin

30, 48a: second photoelectric module 34, 78: optical signal

42 (1) -42 (1) n, 45 (1) -45 (n)

48b: third photoelectric module 64, 66: first and second photoelectric modules

68: CPU package 68B: CPU board

68D, 119: protective layer 79: guide means

82,88: second photoelectric module 90: buffer chip

94: Through holes 94a, 94b: First and second through holes

98: light reflector 100M: memory module

102: optical alignment medium 108, 116: first and second vertical optical waveguides

104, 106, 110: first to third microball lenses

120: Window 112: Photoelectric module

114: memory die 140: lower connector

142: rubber seal 144: support

150: substrate 160: upper connector

C1, C2: first and second contact bodies Ch1-Chn, Ch11-Chnn: first to n-th channels

G1, G2: first and second memory module groups

LS: light source M1, M2: first and second memory chips

M11: memory chips OC2, OC3: first to third optical connectors

S1: upper reflecting surface T1: trench

Claims (15)

Memory controller; A memory module connected to the memory controller; A socket on which the memory module is mounted; A first photoelectric module connected to the memory controller; An optical channel having one end connected to the first photoelectric module and the other end extending through the socket; And And a second photoelectric module provided between the optical channel and the memory module, The second photoelectric module is provided in the socket, A plurality of optical distributors are further provided between the memory controller and the at least one socket, the number of optical distributors being equal to the number of the optical channels, and a signal distributed by each of the optical distributors being distributed . The method according to claim 1, Wherein the memory controller and the first photoelectric module are mounted on the same board or mounted on another board to form a CPU package. 3. The method of claim 2, Further comprising an optical connector that is optically connected to the first photoelectric module between the CPU package and the socket. The method according to claim 1, And the second photoelectric module is provided on a bottom surface of the socket so as to face the optical channel. The method according to claim 1, Wherein the optical channel is any one of optical fibers and optical waveguides. The method according to claim 1, And an electric wiring is further provided between the memory controller and the socket. delete A semiconductor device comprising a memory controller, a memory module connected to the memory controller, and a socket on which the memory module is mounted, A first photoelectric module connected to the memory controller; An optical channel having one end connected to the first photoelectric module and the other end extending through the socket; An optical coupler for branching and coupling an optical signal between the optical channel and the memory module; And And a first optical connector for transferring the optical signal of either the optical coupler or the memory module to the other, The optical connector is provided in the socket, A plurality of optical distributors are further provided between the memory controller and the at least one socket, the number of optical distributors being equal to the number of the optical channels, and a signal distributed by each of the optical distributors being distributed . 9. The method of claim 8, And an optical connector is further provided between the first photoelectric module and the socket. 9. The method of claim 8, And a second optical connector for transferring the optical signal of either the first optical connector or the memory module to the other side. 11. The method of claim 10, And a second photoelectric module for converting signals of either the second optical connector or the memory chip between the second optical connector and a plurality of memory chips mounted on the memory module to transfer the signal to the other. 11. The method of claim 10, Wherein the second optical connector is provided in the memory module so that the second optical connector can be coupled to the first optical connector, and the memory module and the socket are provided with means for fixing the memory module. 9. The method of claim 8, And an electric wiring is further provided between the memory controller and the socket. delete 9. The method of claim 8, Wherein at least two memory module groups are connected to the optical distributor, and each memory module group includes a plurality of memory modules.

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