KR101598951B1 - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a display device comprising first and second substrates facing each other and defining a display area and a non-display area surrounding the display area, respectively; A gate wiring and a data wiring formed in a display region of the first substrate and defining a pixel region crossing each other; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor; A plurality of first signal lines formed in a non-display region of the first substrate; A plurality of second signal lines crossing the plurality of first signal lines; A plurality of first dummy patterns formed on the plurality of first signal lines and spaced apart from the plurality of second signal lines; A circuit block connected to the plurality of second signal lines and the gate line; A black matrix, a color filter layer, and a common electrode sequentially formed below the second substrate; A seal pattern formed in a non-display area between the first and second substrates; And a liquid crystal layer formed between the pixel electrode and the common electrode.

Liquid crystal display, GIP, dummy pattern

Description

[0001] The present invention relates to a liquid crystal display device, and more particularly,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly to a gate-in-panel (GIP) type liquid crystal display in which gate drivers are formed on an array substrate and a method of manufacturing the liquid crystal display.

Recently, as the information society has advanced rapidly, there has been a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among these, a liquid crystal display device , Color display, and picture quality, and is widely used in notebook computers, desktop monitors, and the like.

2. Description of the Related Art In general, a liquid crystal display device is a liquid crystal display device in which two substrates, each having electrodes formed thereon, are arranged so that two electrodes face each other, liquid crystal is injected between the two electrodes, And is a device for displaying an image by the transmittance of light which changes according to the movement.

Such a liquid crystal display device includes a liquid crystal panel including two bonded substrates and a liquid crystal layer therebetween, a backlight unit disposed under the liquid crystal panel to supply light, and a plurality of signals And a driving unit for supplying power.

Generally, the driving unit is implemented in a printed circuit board (PCB). The driving unit is divided into a gate driving unit connected to the gate wiring of the liquid crystal panel, and a data driving unit connected to the data wiring. The printed circuit board for data and the printed circuit board for data may be implemented as a printed circuit board (data PCB). The printed circuit board and the data printed circuit board for data use include a gate pad formed on one side of the liquid crystal panel and connected to the gate wiring, And may be mounted on the data pads connected to the data lines in the form of a tape carrier package (TCP).

However, when a printed circuit board for a gate and a printed circuit board for a data are mounted on a gate pad and a data pad, respectively, the volume and weight increase.

Accordingly, some of the gate drivers, such as a shift register, formed on the gate driver printed circuit board are directly formed on the array substrate of the liquid crystal panel, and the remaining circuits of the gate driver and the data driver are connected to one A gate-in-panel (GIP) type liquid crystal display device which is implemented as a printed circuit board and connected to only one side of the liquid crystal panel has been proposed.

FIG. 1 is a plan view of a conventional GIP type liquid crystal display, and FIG. 2 is a cross-sectional view taken along line II-II in FIG.

1 and 2, the GIP type liquid crystal display device 10 includes a lower array substrate 20, an upper color filter substrate 50, and an upper substrate 50 formed between the two substrates 20, And a liquid crystal layer 70.

 At this time, the GIP type liquid crystal display device 10 comprises a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.

A gate wiring 13 and a data wiring 28 which define the pixel region P and are connected to the gate wiring and the data wirings 13 and 28 are formed in the display region DA above the array substrate 20 A thin film transistor Tr as a switching element and a pixel electrode 43 connected to the thin film transistor Tr are formed.

That is, the gate electrode 15 is formed on the array substrate 20, the gate insulating layer 21 is formed on the gate electrode 15, and the gate insulating layer 21 corresponding to the gate electrode 15 A semiconductor layer 23 composed of an active layer 23a and an ohmic contact layer 23b is formed on the semiconductor layer 23 and source and drain electrodes 30 and 32 are formed on the semiconductor layer 23, And a drain contact hole 41 for exposing the drain electrode 32 is formed on the upper portion of the thin film transistor Tr and a drain contact hole 41 is formed on the protection layer 38, The pixel electrode 43 is formed to be in contact with the drain electrode 32. [

In FIG. 2, a thin film transistor Tr is formed only in one pixel region P, which is caused by a difference according to a cut surface. In fact, the thin film transistor Tr is formed in every pixel region P do.

The display region DA of the color filter substrate 50 facing the array substrate 20 is provided with a plurality of pixel electrodes corresponding to the gate wiring 13, the data wiring 28 and the thin film transistor Tr of the array substrate 20 A color filter layer 58 is formed under the color filter substrate 50 exposed through the first black matrix 53a under the first black matrix 53a and the first black matrix 53a, And a common electrode 60 of a transparent conductive material is formed on the lower surface of the lower electrode 58.

The color filter layer 58 includes red, green, and blue color filter patterns 58a, 58b, and 58c that are sequentially and repeatedly formed for each pixel region P. [

On the other hand, in the non-display area NDA above the array substrate 20, a plurality of circuit blocks 48, a plurality of first signal wirings 18, a plurality of second signal wirings 35, A data pad 46, and a plurality of gate pads 47 are formed.

Each of the plurality of circuit blocks 48 may be a combination of a plurality of switching elements and capacitors or the like constituting one stage of a shift register and each of the plurality of second signal lines 35 and display And is connected to the gate wiring 13 of the area DA.

A plurality of data pads 46 and a plurality of gate pads 47 are formed on one edge of the non-display area NDA. The plurality of data pads 46 are connected to the data lines 28 of the display area DA And a plurality of gate pads 47 are connected to the plurality of first signal lines 18 of the non-display area NDA to be connected to the external A clock signal, and the like.

A plurality of first signal lines 18 and a plurality of second signal lines 35 are connected to each other through a connection pattern 44. To this end, A plurality of first signal wirings 18 and a plurality of first signal wirings 18 are formed on the gate insulating layer 21. The plurality of first signal wirings 18 are formed on the gate insulating layer 21, And a protective layer 38 is formed on the plurality of second signal wirings 38. The second signal wirings 35 are formed on the second signal wirings 38,

A first connection contact hole 42a is formed in the gate insulation layer 21 and the protection layer 38 to expose a plurality of first signal lines 18 and a plurality of second signal lines A second connection contact hole 42b is formed to expose the second connection contact hole 42a.

The connection pattern 44 is formed on the first connection contact hole 42a and the connection pattern 44 corresponding to the second connection contact hole 42b on the protection layer 38, And contacts the plurality of second signal wirings 35 through the second connection contact holes 42b so that the first signal wirings 18 and the second signal wirings 35 are connected to each other.

In the non-display area NDA of the color filter substrate 50, a second black matrix 53b for preventing light leakage and a common electrode 60 made of a transparent conductive material are formed in order.

After the array substrate 20 and the color filter substrate 50 are completed, the GIP type liquid crystal display 10 is completed by bonding the two substrates by pressing and heating and forming a liquid crystal layer 70 between the two substrates The seal pattern 80 is formed in the non-display area NDA between the array substrate 20 and the color filter substrate 50 for this purpose.

The seal pattern 80 is formed so as to overlap a plurality of first signal lines 18 and a plurality of second signal lines 35 in the non-display area NDA of the array substrate 20, A plurality of first signal wirings 18, a gate insulating layer 21, a plurality of second signal wirings 35, or a protective layer 38 may be deteriorated in the process, which will be described with reference to the drawings.

Fig. 3 is an enlarged plan view of the portion A in Fig. 1, and Fig. 4 is a cross-sectional view taken along the line IV-IV in Fig.

3 and 4, a plurality of first signal wirings 18 are formed in the non-display area NDA above the array substrate 20, and a plurality of first signal wirings 18 are formed on the entire upper surface of the plurality of first signal wirings 18. [ A plurality of second signal lines 35 are formed on the gate insulating layer 21 and a protective layer 38 is formed on the entire upper surface of the plurality of second signal lines 35 And a connection pattern 44 for connecting a plurality of first signal lines 18 and a plurality of second signal lines 35 is formed on the protection layer 38.

At this time, the plurality of first signal lines 18 and the plurality of second signal lines 35 intersect each other to form a plurality of overlapping portions OP. In each of the plurality of overlapping portions OP, .

That is, when the plurality of first signal lines 18 and the plurality of second signal lines 35 have the first thickness t1 and the second thickness t2, respectively, the top surfaces of the plurality of overlapping portions OP are And becomes higher by the sum of the first thickness t1 and the second thickness t2 than the other portions.

Therefore, when the seal pattern 80 is formed and pressed in the non-display area NDA between the array substrate 20 and the color filter substrate 50, the plurality of overlapped portions OP are pressed with a relatively large pressure .

That is, the first pressure P1 acting on a plurality of overlapping portions OP having a high height is larger than the second pressure P2 acting on another portion having a low height. (P1 > P2)

This concentration of pressure is caused by a plurality of openings of the plurality of second signal lines 35 of the plurality of overlapping portions OP or a plurality of openings of the plurality of first overlapping portions OP by destruction of the gate insulating layer 21. [ Resulting in a defect such as a shortage of the signal wiring 18 and the plurality of second signal wirings 35.

Since the second signal lines 35 or the gate insulating layer 21 are deteriorated even if they are not immediately destroyed during the adhesion process, And the like.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a GIP type liquid crystal display device in which a dummy pattern is formed on a plurality of signal lines to reduce steps of overlapping portions, It is an object of the present invention to prevent defects such as disconnection and short circuit of a plurality of signal lines of a liquid crystal display device.

Another object of the present invention is to repair defects of a plurality of signal lines of a GIP type liquid crystal display device by utilizing a dummy pattern formed on a plurality of signal lines as a repair line in a GIP type liquid crystal display device .

According to an aspect of the present invention, there is provided a display device comprising: first and second substrates spaced apart from each other and defining a display area and a non-display area surrounding the display area; A gate wiring and a data wiring formed in a display region of the first substrate and defining a pixel region crossing each other; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor; A plurality of first signal lines formed in a non-display region of the first substrate; A plurality of second signal lines crossing the plurality of first signal lines; A plurality of first dummy patterns formed on the plurality of first signal lines and spaced apart from the plurality of second signal lines; A circuit block connected to the plurality of second signal lines and the gate line; A black matrix, a color filter layer, and a common electrode sequentially formed below the second substrate; A seal pattern formed in a non-display area between the first and second substrates; And a liquid crystal layer formed between the pixel electrode and the common electrode.

The seal pattern overlaps the plurality of first signal lines and the plurality of second signal lines.

The GIP type liquid crystal display may further include a gate insulating layer between the gate wiring and the data wiring and a protective layer between the data wiring and the pixel electrode, The plurality of second signal lines and the plurality of first dummy patterns may be formed of the same layer and the same material as the data lines.

The GIP type liquid crystal display further includes a plurality of connection patterns formed on the protection layer and connecting the plurality of first signal lines and the plurality of second signal lines at a ratio of 1: And a plurality of second dummy patterns formed on the upper layer and spaced apart from the plurality of connection patterns.

The plurality of connection patterns and the plurality of second dummy patterns may be formed of the same material and the same material as the pixel electrodes.

According to another aspect of the present invention, there is provided a method of manufacturing a display device, comprising: forming a gate wiring and a data wiring crossing each other to define a pixel region in a display region above a first substrate; Forming a thin film transistor connected to the gate wiring and the data wiring; Forming a pixel electrode connected to the thin film transistor; Forming a plurality of first signal lines in a non-display area surrounding the display area of the first substrate; Forming a plurality of second signal lines crossing the plurality of first signal lines and a plurality of first dummy patterns spaced apart from the plurality of second signal lines; Forming a plurality of second signal lines and circuit blocks connected to the gate lines; Sequentially forming a black matrix, a color filter layer, and a common electrode on a lower portion of a second substrate on which the display region and the non-display region are defined; Forming a seal pattern in a non-display area between the first and second substrates; Attaching the first and second substrates such that the pixel electrode and the common electrode face each other; And forming a liquid crystal layer between the pixel electrode and the common electrode. The present invention also provides a method of manufacturing a GIP (gate-in-panel) type liquid crystal display device.

Here, the first and second substrates may be bonded together by pressurization, and the manufacturing method of the GIP type liquid crystal display device may further include connecting the plurality of first signal wirings and the plurality of second signal wirings in a 1: And forming a plurality of second dummy patterns spaced apart from the plurality of connection patterns.

As described above, in the GIP type liquid crystal display device according to the present invention, the dummy pattern is formed on the plurality of signal lines superimposed on the seal pattern, so that the level difference is reduced and the pressure concentration in the sticking process is relaxed, There is an advantage that defects are prevented.

In addition, in the GIP type liquid crystal display device according to the present invention, there is an advantage that a defect of a large number of signal lines can be repaired by utilizing a dummy pattern formed on a plurality of signal lines as a repair line.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a plan view of a GIP type liquid crystal display according to a first embodiment of the present invention, and FIG. 6 is a sectional view taken along a line VI-VI in FIG.

5 and 6, the GIP type liquid crystal display device 110 includes a lower first substrate 120, an upper second substrate 150, first and second substrates 120 and 150 (Not shown).

 At this time, the GIP type liquid crystal display device 110 includes a display area DA for displaying an image and a non-display area NDA surrounding the display area DA.

A gate wiring 113 and a data wiring 128 which define the pixel region P and gate wirings and data wirings 113 and 128 which intersect each other and which define the pixel region P are formed in the display region DA above the first substrate 120 A thin film transistor Tr which is a switching element to be connected and a pixel electrode 143 which is connected to the thin film transistor Tr are formed.

That is, a gate electrode 115 is formed on the first substrate 120, a gate insulating layer 121 is formed on the gate electrode 115, a gate insulating layer 121 is formed on the gate electrode 115, A semiconductor layer 123 composed of an active layer 123a and an ohmic contact layer 123b is formed on the semiconductor layer 123 and source and drain electrodes 130 and 132 are formed on the semiconductor layer 123, And a drain contact hole 141 for exposing the drain electrode 32 is formed on the upper portion of the thin film transistor Tr and a drain contact hole 41 The pixel electrode 143 is formed to be in contact with the drain electrode 32.

In FIG. 2, a thin film transistor Tr is formed only in one pixel region P, but this is due to a difference according to a cut surface. Actually, a thin film transistor Tr is formed in every pixel region P .

The gate line 113, the data line 128 and the thin film transistor 1 Tr of the first substrate 120 are formed in the display area DA of the second substrate 150 facing the first substrate 120, A corresponding first black matrix 153a is formed and a color filter layer 158 is formed under the second substrate 150 exposed through the first black matrix 153a and the first black matrix 153a, A common electrode 160 of a transparent conductive material is formed on the lower surface of the lower surface of the color filter layer 158.

The color filter layer 158 includes red, green, and blue color filter patterns 158a, 158b, and 158c that are sequentially and repeatedly formed for each pixel region P.

On the other hand, in the non-display area NDA on the first substrate 120, a plurality of circuit blocks 148, a plurality of first signal lines 118, a plurality of second signal lines 135, A plurality of data pads 146, and a plurality of gate pads 147 are formed.

Each of the plurality of circuit blocks 148 may be a combination of a plurality of switching elements and capacitors or the like constituting one stage of a shift register and each of the plurality of second signal lines 135 and display And is connected to the gate wiring 113 of the area DA to supply a gate signal.

A plurality of data pads 146 and a plurality of gate pads 147 are formed on one edge of the non-display area NDA, and the plurality of data pads 146 are connected to the data lines 128 of the display area DA And a plurality of gate pads 147 are connected to a plurality of first signal lines 118 of the non-display area NDA to be connected to external Such as a start signal and a clock signal, input from a drive circuit such as a printed circuit board of a display device.

A plurality of first signal lines 118 intersecting with the plurality of second signal lines 135 are connected to a plurality of data pads 146 and a plurality of gate pads 147 and a plurality of second signal lines 135 And transmits a plurality of driving signals to the plurality of circuit blocks 148.

A plurality of first signal lines 118 and a plurality of second signal lines 135 are connected to each other in a non-display area NDA of the array substrate 120 through a connection pattern 144 at a ratio of 1: A plurality of first signal wirings 118 are formed and a gate insulating layer 121 is formed on the plurality of first signal wirings 118. A plurality of first signal wirings 18 And a plurality of dummy patterns 137 corresponding to the plurality of first signal wirings and spaced apart from the plurality of second signal wirings are formed, and a plurality of second signal wirings 138 and the plurality of dummy patterns 137 are formed.

A first connection contact hole 142a is formed in the gate insulation layer 121 and the protection layer 138 to expose a plurality of first signal lines 118. A plurality of second signal lines The second connection contact hole 142b exposing the second connection contact hole 142 is formed.

When the connection pattern 144 corresponding to the first connection contact hole 142a and the second connection contact hole 142b is formed on the protection layer 138, the connection pattern 144 is electrically connected to the first connection contact hole 142a, And contacts the plurality of second signal wirings 135 through the second connection contact holes 142b so that the first signal wirings 118 and the second signal wirings 135 are electrically connected to each other.

In the non-display area NDA of the color filter substrate 150, a second black matrix 153b for preventing light leakage and a common electrode 160 made of a transparent conductive material are formed in order.

After the first substrate 120 and the second substrate 150 are completed, the first and second substrates 120 and 150 are bonded together by pressing and heating, and the first and second substrates 120 and 150 are bonded The GIP type liquid crystal display device 110 is completed by forming the liquid crystal layer 170. To this end, the seal pattern 180 is formed in the non-display area NDA between the first and second substrates 120 and 150 .

The seal pattern 180 is formed so as to overlap with the plurality of first signal lines 118, the plurality of second signal lines 135 and the plurality of dummy patterns 137 in the non-display area NDA of the first substrate 120 In the GIP type liquid crystal display device 110 according to the first embodiment of the present invention, a plurality of second signal wirings (not shown) are formed in portions corresponding to the plurality of first signal wirings 118 on the gate insulating layer 121 The steps of the plurality of second signal lines 135 are alleviated by the plurality of dummy patterns 137 spaced apart from the first signal lines 135, thereby preventing defects such as disconnection and short circuit.

FIG. 7 is an enlarged plan view of the portion B in FIG. 5, and FIG. 8 is a sectional view taken along the cutting line VIII-VIII in FIG.

7 and 8, a plurality of first signal wirings 118 are formed in the non-display area NDA above the first substrate 120, and a plurality of first signal wirings 118 are formed on the upper front A plurality of second signal wirings 135 and a plurality of dummy patterns 137 are formed on the gate insulating layer 121 and a plurality of second signal wirings 135 and A protective layer 138 is formed on the entire upper surface of the plurality of dummy patterns 137 and a connection for connecting the plurality of first signal lines 118 and the plurality of second signal lines 135 is formed on the protective layer 138. [ A pattern 144 is formed.

At this time, the plurality of first signal lines 118 and the plurality of second signal lines 135 intersect to form a plurality of overlapping portions OP, and a plurality of second signal lines By forming a plurality of dummy patterns 137 spaced apart from the plurality of second signal wirings 135 at a portion adjacent to the plurality of second signal wirings 135, .

That is, when a plurality of first signal lines 118 and a plurality of second signal lines 135 have a first thickness t1 and a second thickness t2, respectively, The number of the dummy patterns 137 is increased by the sum of the first thickness t1 and the second thickness t2 as compared with the other portions. However, since the plurality of dummy patterns 137 also have the second thickness t2, The uppermost surface of the dummy pattern 137 is also higher by the sum of the first thickness t1 and the second thickness t2 than the remaining portion and eventually the steps of the plurality of second signal lines 135 and the plurality of dummy patterns 137 are removed.

Accordingly, when the seal pattern 180 is formed and pressed on the non-display area NDA between the first and second substrates 120 and 150, the pressure concentrated on the plurality of overlapping portions OP is dispersed.

That is, the first pressure P1 acting on the second signal line 135 of the plurality of overlapping portions OP is the second pressure P2 acting on the plurality of dummy patterns 137 having a similar height, As shown in FIG. (P1 to P2)

Due to the dispersion of the pressure, a plurality of openings of the plurality of second signal wirings 135 of the plurality of overlapping portions OP, or a plurality of openings of the plurality of overlapping portions OP due to destruction of the gate insulating layer 121 Defects such as a shortage of the first signal line 118 and the plurality of second signal lines 135 are prevented.

In the GIP type liquid crystal display device 110 of Figs. 7 and 8, the first signal line 118 of the non-display portion NDA is formed in the same layer as the gate wiring 113 and the gate electrode 115 of the display portion DA, The second signal wiring 135 and the dummy pattern 137 of the non-display portion NDA are formed of the same material as the data wiring 128, the source electrode 130, and the drain electrode 132 of the display portion DA And the connection pattern 144 of the non-display portion NDA is formed of the same layer and the same material as the pixel electrode 143 of the display portion DA, Type liquid crystal display device, the first signal wiring may be formed of the same layer and the same material as the data wiring, and the second signal wiring and the dummy pattern may be formed of the same layer and the same material as the gate wiring.

A plurality of dummy patterns 137 are formed on the plurality of first signal lines 118 with the gate insulating layer 121 interposed therebetween. A contact hole is formed in the gate insulating layer 121, 1 signal line 118 and may be used for transferring a plurality of driving signals or may be maintained in an electrically floating state without forming any contact hole in the gate insulating layer 121. [

The plurality of dummy patterns 137 may be used as a repair line when a plurality of first signal lines 118 are open. For example, as shown in FIG. 7, A plurality of dummy patterns 137 and a plurality of first signal wirings 118 are formed through the gate insulating layer 121 by irradiating a laser beam or the like to the points C and D when the first signal wiring 118 is open. The number of the first signal lines 118 can be repaired.

On the other hand, in another embodiment, the plurality of dummy patterns may be formed to be higher than the plurality of second signal lines of the overlapped portion so that the pressure of the laminating process is concentrated on the plurality of dummy patterns. do.

FIG. 9 is an enlarged plan view of a non-display region of a GIP type liquid crystal display device according to a second embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along the line X-X of FIG.

The GIP type liquid crystal display devices of FIGS. 9 and 10 are the same as those of the GIP type liquid crystal display devices of FIGS. 5 and 6, except for the second dummy pattern.

9 and 10, a plurality of first signal wirings 218 are formed in the non-display area NDA on the first substrate 220, and a plurality of first signal wirings 218 are formed on the upper front A plurality of second signal lines 235 and a plurality of first dummy patterns 237 are formed on the gate insulating layer 221 and a plurality of second signal lines 235 A plurality of first signal wirings 218 and a plurality of second signal wirings 235 are formed on the protective layer 238. The first signal wirings 218 and the plurality of second signal wirings 235 are formed on the protective layer 238, A connecting pattern 244 for connecting and a plurality of second dummy patterns 245 are formed.

At this time, a plurality of first signal lines 218 and a plurality of second signal lines 235 intersect each other to form a plurality of overlapping portions OP. In the plurality of overlapping portions OP, A plurality of first dummy patterns 237 spaced apart from the plurality of second signal lines 235 are formed in a portion adjacent to the first signal lines 235.

A plurality of second dummy patterns 245 spaced apart from the plurality of connection patterns 244 are formed on portions of the protective layer 238 corresponding to the plurality of first dummy patterns 237 except a plurality of overlapping portions OP. Is formed.

That is, the plurality of second dummy patterns 245 and the plurality of first dummy patterns 237 may overlap and have the same shape.

Therefore, the steps of the plurality of overlapping parts OP by the plurality of second signal wirings 235 are reversed by the plurality of first dummy patterns 237 and the plurality of second dummy patterns 245, The pressure concentrated on the second signal line 235 of the first dummy pattern 237 is concentrated on the first dummy patterns 237 and the second dummy patterns 245.

That is, when the plurality of first signal lines 218 and the plurality of second signal lines 235 have the first thickness t1 and the second thickness t2, respectively, the top surfaces of the plurality of overlapping portions OP are A plurality of first dummy patterns 237 may have a second thickness t2 and a plurality of second dummy patterns 245 may be formed to have a larger thickness than the other portions by a sum of the first thickness t1 and the second thickness t2. The uppermost surface of the portion where the plurality of first dummy patterns 237 and the plurality of second dummy patterns 245 are formed has the first thickness t1 and the second thickness t2, The number of the first dummy patterns 237 and the number of the second dummy patterns 245 become higher than the number of the second signal wirings 235. As a result,

Accordingly, when the seal pattern 280 is formed on the non-display area NDA between the first and second substrates 220 and 250 and the pressure is applied, the pressure concentrated on the plurality of overlapping parts OP is rather large, 1 dummy pattern 237 and a plurality of second dummy patterns 245. [

In other words, the first pressure P1 acting on the second signal line 235 of the plurality of overlapping portions OP can be divided into a plurality of first dummy patterns 237 and a plurality of second dummy patterns 245 of the second pressure P2. (P1 < P2)

Due to the dispersion and inversion of the pressure, the openings of the plurality of second signal lines 235 of the plurality of overlapping portions OP or the breakage of the gate insulating layer 221 of the plurality of overlapping portions OP Defects such as a shortage of the plurality of first signal lines 218 and the plurality of second signal lines 235 are prevented.

In the GIP type liquid crystal display device 210 of Figs. 9 and 10, the first signal wiring 218 of the non-display portion NDA is formed of the same layer and the same material as the gate wiring of the display portion and the gate electrode, NDA) and the first dummy pattern 237 are formed on the same layer and the same material as the source electrode and the drain electrode and the connection pattern 244 of the non-display portion NDA And the second dummy pattern 245 are formed of the same layer and the same material as that of the pixel electrode of the display portion DA. However, in the GIP type liquid crystal display device according to another embodiment, It is also possible to form the second signal wiring and the first dummy pattern with the same layer and the same material as the gate wiring.

The plurality of first dummy patterns 237 are formed on the plurality of first signal lines 218 with the gate insulating layer 221 interposed therebetween and the plurality of second dummy patterns 245 are formed on the gate insulating layer 221. [ A plurality of contact holes are formed in the gate insulating layer 221 and the protective layer 238 to form a plurality of first signal wirings 218. In this case, It may be electrically connected to the signal wiring 218 to transfer a plurality of driving signals or may be held in an electrically floating state without forming any contact holes in the gate insulating layer 121 and the protective layer 238.

The plurality of first dummy patterns 237 and the plurality of second dummy patterns 245 may be used as a repair line when openings are formed in the plurality of first signal lines 218 .

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

1 is a plan view of a conventional GIP type liquid crystal display device.

Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1; Fig.

3 is an enlarged plan view of a portion A in Fig.

4 is a cross-sectional view taken along the line IV-IV in Fig. 3;

5 is a plan view of a GIP type liquid crystal display device according to the first embodiment of the present invention.

6 is a cross-sectional view taken along the section line VI-VI of Fig. 5;

7 is an enlarged plan view of a portion B in Fig. 5; Fig.

8 is a cross-sectional view taken along line VIII-VIII in Fig. 7;

9 is an enlarged plan view of a non-display area of a GIP type liquid crystal display device according to a second embodiment of the present invention;

10 is a cross-sectional view taken along the line X-X in Fig. 9

Claims (10)

A first substrate and a second substrate spaced apart from each other and defining a display area and a non-display area surrounding the display area, respectively; A gate wiring and a data wiring formed in a display region of the first substrate and defining a pixel region crossing each other; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor; A plurality of first signal lines formed in a non-display region of the first substrate; A plurality of second signal lines crossing the plurality of first signal lines; And a plurality of second signal lines, which are disposed on the plurality of first signal lines and overlap the plurality of first signal lines, and which are spaced apart from the plurality of second signal lines, A first dummy pattern; A circuit block connected to the plurality of second signal lines and the gate line; A black matrix, a color filter layer, and a common electrode sequentially formed below the second substrate; A seal pattern formed in a non-display area between the first and second substrates; A liquid crystal layer formed between the pixel electrode and the common electrode, (GIP) type liquid crystal display device. The method according to claim 1, Wherein the seal pattern overlaps the plurality of first signal lines and the plurality of second signal lines. The method according to claim 1, A gate insulating layer between the gate wiring and the data wiring, and a protective layer between the data wiring and the pixel electrode. The method of claim 3, Wherein the plurality of first signal wirings are formed of the same layer and the same material as the gate wirings, and the plurality of second signal wirings and the plurality of first dummy patterns are formed of a GIP type Liquid crystal display device. 5. The method of claim 4, And a plurality of connection patterns formed on the protection layer and connecting the plurality of first signal lines and the plurality of second signal lines at a ratio of 1: 1. 6. The method of claim 5, And a plurality of second dummy patterns formed on the protection layer and spaced apart from the plurality of connection patterns. The method according to claim 6, Wherein the plurality of connection patterns and the plurality of second dummy patterns are formed of the same material and the same material as the pixel electrodes. Forming a gate wiring and a data wiring crossing each other and defining a pixel region in a display region above the first substrate; Forming a thin film transistor connected to the gate wiring and the data wiring; Forming a pixel electrode connected to the thin film transistor; Forming a plurality of first signal lines in a non-display area surrounding the display area of the first substrate; A plurality of second signal wirings crossing the plurality of first signal wirings; a second signal wirings arranged to overlap the plurality of first signal wirings and spaced apart from the plurality of second signal wirings, Forming a plurality of first dummy patterns made of the same material; Forming a plurality of second signal lines and circuit blocks connected to the gate lines; Sequentially forming a black matrix, a color filter layer, and a common electrode on a lower portion of a second substrate on which the display region and the non-display region are defined; Forming a seal pattern in a non-display area between the first and second substrates; Attaching the first and second substrates such that the pixel electrode and the common electrode face each other; Forming a liquid crystal layer between the pixel electrode and the common electrode (GIP) type liquid crystal display device. 9. The method of claim 8, Wherein the first and second substrates are bonded together by pressurization. 10. The method of claim 9, Forming a plurality of connection patterns connecting the plurality of first signal lines and the plurality of second signal lines at a ratio of 1: 1 and a plurality of second dummy patterns spaced apart from the plurality of connection patterns, A manufacturing method of a GIP type liquid crystal display device.

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