KR101592778B1 - Circuit for detecting a resolver fault - Google Patents

Abstract

The present invention relates to a resolver failure detection circuit for a motor, and more particularly, to a resolver failure detection circuit for a motor, which comprises a resolver output signal coupling circuit for converting a sinusoidal output signal generated by coupling a resolver output signal, And judging the resolver output terminal to be in a failure state when the threshold value is exceeded.
An embodiment of a resolver failure detection circuit of a motor according to the present invention comprises: a signal coupling portion coupling a resolver output signal; A sinusoidal signal output unit for converting the coupled signal to generate a sinusoidal output signal; And a failure detector for determining whether the sine wave output signal exceeds a predetermined threshold value based on a predetermined offset voltage. . ≪ / RTI >
The signal coupling unit includes: a first signal coupling unit coupling the first stage output signal (V_S1) of the resolver and the third stage output signal (V_S3); And a second signal coupling unit coupling the resolver's second-stage output signal (V_S2) and the fourth-stage output signal (V_S4); . ≪ / RTI >
The sinusoidal signal output unit includes a first sinusoidal output signal V_S1 + S3 for converting a signal obtained by coupling the first stage output signal V_S1 of the resolver and the third stage output signal V_S3 to generate a first sinusoidal output signal V_S1 + A sinusoidal signal output unit; And a second sinusoidal signal output unit for converting a signal obtained by coupling the second stage output signal (V_S2) of the resolver and the fourth stage output signal (V_S4) to generate a second sinusoidal output signal (V_S2 + S4); . ≪ / RTI >
When the first sinusoidal output signal (V_S1 + S3) exceeds a predetermined threshold value on the basis of a predetermined offset voltage, the failure detecting unit determines that the first and third ends of the resolver are in a failure state or a predetermined offset voltage When the second sinusoidal output signal (V_S2 + S4) exceeds a predetermined threshold value, the second and fourth stages of the resolver are determined to be in a failure state.

Description

RESOLOR FAULT DETECTION CIRCUIT FOR DETECTING A RESOLVER FAULT

The present invention relates to a resolver failure detection circuit for a motor, and more particularly, to a resolver failure detection circuit for a motor, which comprises a resolver output signal coupling circuit for converting a sinusoidal output signal generated by coupling a resolver output signal, And judging the resolver output terminal to be in a failure state when the threshold value is exceeded.

The inverter 40 for a motor for driving an environmental vehicle performs a role of converting a DC voltage into an AC voltage and supplying the AC voltage to the motor by switching six switching devices (IGBTs). In order for the inverter 40 to convert the DC voltage to the AC voltage to control the motor, the position information of the motor rotor is indispensably required. At this time, the position information of the motor rotor can be obtained from the position sensor created in the motor, and the resolver 50 is mainly used as the position sensor of the motor for the vehicle. The resolver 50 has six input / output signal lines, two input signal lines, and four output signal lines. The input / output signal line of the resolver 50 may be disconnected or short-circuited due to various causes. If such a fault occurs, the inverter 40 can not acquire accurate position information of the motor rotor , The inverter 40 can not normally control the motor, and thus a dangerous situation may occur to the driver.

The resolver failure detection circuit according to the related art includes four resolver output signals S1, S2, S3, and S4 of the motor as one operational amplifier (OP AMP) and one analog-to- Digital converter (ADC), a signal is extracted at a peak point of the carrier signal and sampled, and the sum of the sampled signals is calculated to determine the fault state (open or short) of the resolver. That is, by using four operational amplifiers (OP AMP) and four analog-to-digital converters (ADC) per motor, when two motors are used in environmental vehicles, the resolver failure detection circuit has eight operational amplifiers AMP) and a total of eight analog-to-digital converters (ADCs). However, the conventional technique has a problem in that the cost is increased by using a plurality of elements, and the area occupied by the resolver failure detection circuit is excessively consumed.

In the present invention, a resolver failure detection circuit can be implemented using two operational amplifiers (OP AMP) and two analog-to-digital converters (ADC) per motor.

KR 1039676 B1

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems, and it is an object of the present invention to solve the above-mentioned problems, and it is an object of the present invention to provide a non- And judging the resolver output terminal to be in a failure state when the threshold value is exceeded, thereby diagnosing the failure of the resolver by using a smaller number of electronic elements.

In order to achieve the above object, an embodiment of a resolver failure detection circuit of a motor according to the present invention includes: a signal coupling section for coupling a resolver output signal; A sinusoidal signal output unit for converting the coupled signal to generate a sinusoidal output signal; And a failure detector for determining whether the sine wave output signal exceeds a predetermined threshold value based on a predetermined offset voltage. . ≪ / RTI >

The signal coupling unit includes: a first signal coupling unit coupling the first stage output signal (V_S1) of the resolver and the third stage output signal (V_S3); And a second signal coupling unit coupling the resolver's second-stage output signal (V_S2) and the fourth-stage output signal (V_S4); . ≪ / RTI >

Here, the first signal coupling unit may include a first resolver output signal input (Q1) having one capacitor (C) and one resistor (R1) serially connected and receiving the first stage output signal (V_S1) ; A third resolver output signal input terminal having one capacitor and one resistor connected in series and receiving the third-stage output signal V_S3 of the resolver; A first voltage input terminal having a resistor R2 connected in parallel with the first resolver output signal input terminal and the third resolver output signal input terminal and having a predetermined voltage V1 applied to the resistor R2; . ≪ / RTI >

The second signal coupling unit may include a second resolver output signal input terminal having one capacitor and one resistor connected in series and receiving the second output signal V_S2 of the resolver; A fourth resolver output signal input terminal having one capacitor and one resistor connected in series and receiving the fourth-stage output signal V_S4 of the resolver; And a second voltage input terminal having a resistor connected in parallel to the second resolver output signal input terminal and the fourth resolver output signal input terminal and to which a predetermined voltage is applied; . ≪ / RTI >

In particular, the capacitors and resistors of the first resolver output signal input terminal to the fourth resolver output signal input terminal have the same capacitor value (C) and resistance value (R1), and the first voltage input terminal and the second voltage input terminal The resistor and the applied voltage may all have the same resistance value R2 and the same voltage value V1.

The sinusoidal signal output unit includes a first sinusoidal output signal V_S1 + S3 for converting a signal obtained by coupling the first stage output signal V_S1 of the resolver and the third stage output signal V_S3 to generate a first sinusoidal output signal V_S1 + A sinusoidal signal output unit; And a second sinusoidal signal output unit for converting a signal obtained by coupling the second stage output signal (V_S2) of the resolver and the fourth stage output signal (V_S4) to generate a second sinusoidal output signal (V_S2 + S4); . ≪ / RTI >

The first sinusoidal signal output unit includes an operational amplifier OP AMP, a resistor R3 connected in series to the operational amplifier OP AMP and a resistor R4 connected in parallel to the operational amplifier OP amp, And a signal obtained by coupling the first stage output signal (V_S1) of the resolver and the third stage output signal (V_S3) is received from the signal coupling section,

The second sinusoidal signal output unit may include one operational amplifier OP AMP, a resistor connected in series to the operational amplifier OP AMP, and a resistor connected in parallel to the operational amplifier OP amp, And a signal coupled to the resolver's second-stage output signal (V_S2) and the fourth-stage output signal (V_S4) from the ring portion.

In particular, a resistor R3 connected in series to the operational amplifier OP AMP in the second sinusoidal signal output unit and a resistor R4 connected in parallel to the operational amplifier OP AMP are connected to the first sinusoidal signal output A resistor R3 connected in series to the operational amplifier OP AMP and a resistor R4 connected in parallel to the operational amplifier OP AMP have the same resistance values R3 and R4, can do.

Here, the first sinusoidal output signal (V_S1 + S3) may be calculated by the following equation.

Here, the second sinusoidal output signal (V_S2 + S4) is calculated by the following equation.

When the first sinusoidal output signal (V_S1 + S3) exceeds a predetermined threshold value on the basis of a predetermined offset voltage, the failure detecting unit determines that the first and third ends of the resolver are in a failure state or a predetermined offset voltage When the second sinusoidal output signal (V_S2 + S4) exceeds a predetermined threshold value, the second and fourth stages of the resolver are determined to be in a failure state.

Here, the predetermined offset voltage (V_offset) may be calculated by the following equation.

Here, the predetermined threshold may be + 0.6V or -0.6V.

According to the resolver failure detection circuit of the motor according to the present invention, a resolver failure detection circuit using four operational amplifiers (OP AMP) and four analog-to-digital converters (ADC) Since it can be implemented using two analog-to-digital converters (ADC), the cost of the motor control circuit can be reduced, the control board size can be reduced, and the load factor for motor control can be improved.

1 is a block diagram showing a resolver failure detection circuit and major components in an environmental vehicle according to the prior art;
2 is a block diagram showing a resolver failure detection circuit according to the present invention;
3 is a diagram showing a mode in which a first sine wave output signal is determined to be in a steady state by a failure detecting unit of a resolver failure detection circuit according to the present invention.
4 is a diagram showing a mode in which a second sine wave output signal is determined to be in a failure state by a failure detection unit of a resolver failure detection circuit according to the present invention.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the invention. Also, the technical terms used herein should be interpreted in a sense that is generally understood by those skilled in the art to which the present disclosure relates, unless otherwise specifically defined in the present specification, Or shall not be construed to mean excessively reduced. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. But is to be understood as including all modifications, equivalents, and alternatives falling within the scope of the appended claims.

Hereinafter, an embodiment of a resolver failure detection circuit of a motor according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing a resolver failure detection circuit according to the present invention. FIG. 3 is a diagram showing a state in which a first sinusoidal output signal is determined as a normal state by a failure detection unit of a resolver failure detection circuit according to the present invention, 4 is a diagram showing a mode in which a second sine wave output signal is determined to be in a failure state by a failure detecting unit of a resolver failure detection circuit according to the present invention.

2 and 4, an embodiment of the resolver failure detection circuit of the motor according to the present invention may include a signal coupling unit 100, a sinusoidal signal output unit 200, and a failure detection unit 300 have.

The signal coupling section 100 couples the resolver output signals 2, 3, 4, and 5. That is, the signal coupling unit 100 combines the resolver output signals 2, 3, 4, and 5, respectively. More specifically, the signal coupling section 100 may include a first signal coupling section 110 and a second signal coupling section 120.

The first signal coupling unit 110 couples the first stage output signal V_S1 (2) of the resolver and the third stage output signal V_S3 (4). That is, the first signal coupling unit 110 combines the first stage output signal V_S1 (2) of the resolver and the third stage output signal V_S3 (4). More specifically, the first signal coupling unit 110 may include a first resolver output signal input 111, a third resolver output signal input 112, and a first voltage input 113 .

The first resolver output signal input terminal 111 is connected to one capacitor C 10 and one resistor R 1 14 in series and the first stage output signal V_S 1 of the resolver 2).

The third resolver output signal input terminal 112 is connected to one capacitor 11 and one resistor 15 in series and receives the third stage output signal V_S3 and 4 of the resolver. The one capacitor 11 and the one resistor 15 are connected to one capacitor C 10 and one resistor R 14 14 of the first resolver output signal input terminal 111, And may have the same capacitor value C and resistance value R1. This is because the sinusoidal output signal part 200 must have the same resistance value R1 as that of the signal coupling part 100 in order to calculate the first sinusoidal output signal 8. However, the capacitor value (C) 10 and the resistance value (R1) 14 of the first resolver output signal input terminal 111, the capacitor value 11 of the third resolver output signal input terminal 112, The value 15 may vary if the first resolver output signal 2 and the third resolver output signal 4 are different.

The first voltage input terminal 113 has one resistor R2 and 18 connected in parallel to the first resolver output signal input terminal 111 and the third resolver output signal input terminal 112, A predetermined voltage V1 (20) is applied to the resistor R2 (18). Here, the resistor R2 (18) of the first voltage input terminal 113 is for coupling the first resolver output signal 2 and the third resolver output signal 4, (11) and the resistance value (14) (15) of the resolver output signal input terminal (111) and the third resolver output signal input terminal (112). That is, a plurality of resistors and capacitors in the first signal coupling unit 110 may have different values or mutually different values for determining the magnitude of the first sinusoidal output signal V_S1 + S3 (8) They can be placed in different shapes with different numbers.

The second signal coupling unit 120 couples the second stage output signal V_S2 (3) of the resolver and the fourth stage output signal V_S4 (5). That is, the second signal coupling unit 120 combines the second stage output signal V_S2 (3) of the resolver and the fourth stage output signal V_S4 (5). More specifically, the second signal coupling unit 120 may include a second resolver output signal input 121, a fourth resolver output signal input 122, and a second voltage input 123 .

The second resolver output signal input terminal 121 is connected to one capacitor 12 and one resistor 16 in series and outputs the second output signal V_S2, Receive.

The fourth resolver output signal input terminal 122 is connected in series with one capacitor 13 and one resistor 17 and receives the fourth stage output signal V_S4 and 5 of the resolver. The one capacitor 13 and one resistor 17 are connected to one capacitor 12 and one resistor 16 of the second resolver output signal input terminal 121 and have the same capacitor value C, And a resistance value R1. This is because the sinusoidal output signal section 200 must have the same resistance value R1 as that of the signal coupling section 100 in order to calculate the second sinusoidal output signal 9. The capacitor value 12 and the resistance value 16 of the second resolver output signal input terminal 121 and the capacitor value 13 and the resistance value 17 of the fourth resolver output signal input terminal 122 are The second resolver output signal 3 and the fourth resolver output signal 5 are different from each other.

The second voltage input terminal 123 includes a resistor 11 connected in parallel to the second resolver output signal input terminal 121 and the fourth resolver output signal input terminal 122, (21) is applied. Here, the resistor 19 of the second voltage input terminal 123 is for coupling the second resolver output signal 3 and the fourth resolver output signal 5, and the second resolver output (13) and the resistance value (16) (17) of the signal input terminal (121) and the fourth resolver output signal input terminal (122). That is, the plurality of resistors and capacitors in the second signal coupling unit 120 may have different values or different values for interacting with the external electric elements, or determining the magnitude of the second sinusoidal output signal V_S2 + They can be placed in different shapes with different numbers.

The sinusoidal signal output unit 200 converts the coupled signal to generate sinusoidal output signals 8 and 9. More specifically, the sinusoidal signal output unit 200 may include a first sinusoidal signal output unit 210 and a second sinusoidal signal output unit 220.

The first sinusoidal signal output unit 210 converts a signal obtained by coupling the first stage output signal V_S1 (2) of the resolver and the third stage output signal V_S3 (4) And generates an output signal V_S1 + S3 (8). More specifically, the first sinusoidal signal output unit 210 includes an operational amplifier (OP AMP) 26, a resistor R3 connected in series to the operational amplifier (OP AMP) 26, (V_S1) (2) of the resolver and a resistor (R4) (24) connected in parallel to the operational amplifier (OPAMP) The output signal V_S3 (3) of the third stage can receive the coupled signal (6).

At this time, the first sinusoidal output signal V_S1 + S3 (8) can be calculated by the following equation.

Here, R1 is the resistance 14 of the first resolver output signal input 111, R2 is the resistance 18 of the first voltage input, R3 is the resistance of the first sinusoidal signal output 210, Wherein R4 is a history contact resistance (24) of the first sinusoidal signal output section (210), V_s1 is a first stage output signal (2) of the resolver, V_s3 is a resolver The output signal 4 of the third stage.

The second sinusoidal signal output unit 220 converts a signal obtained by coupling the second-stage output signal V_S2 (3) of the resolver and the fourth-stage output signal V_S4 (5) And generates an output signal V_S2 + S4 (9). More specifically, the second sinusoidal signal output unit 220 includes an operational amplifier (OP AMP) 27, a resistor 23 connected in series to the operational amplifier (OP AMP) 27, And a resistor 25 connected in parallel to an amplifier (OP AMP) 27. The second output signal V_S2 (3) of the resolver from the signal coupling section 100 and the output signal (V_S4) 5 can receive a coupled signal. A resistor 23 connected in series to the operational amplifier OP AMP 27 in the second sinusoidal signal output unit 220 and a resistor 25 connected in parallel to the operational amplifier OP AMP 27, ) Includes a resistor R3 (22) connected in series to the operational amplifier (OP AMP) 26 in the first sinusoidal signal output unit 210 and a resistor R22 22 connected in parallel to the operational amplifier And may have the same resistance values R3 and R4 as the connected resistors R4 and 24, respectively.

At this time, the second sinusoidal output signal (V_S2 + S4) (9) can be calculated by the following equation.

Here, R1 is the resistance 14 of the first resolver output signal input 111, R2 is the resistance 18 of the first voltage input, R3 is the resistance of the first sinusoidal signal output 210, Wherein R4 is the history contact resistance (24) of the first sinusoidal signal output section (210), V_s2 is the second stage output signal (3) of the resolver, V_s4 is the resistance value Output signal 5 of the fourth stage.

The failure detecting unit 300 determines whether the sine wave output signal 8 or 9 exceeds a predetermined threshold value 29 based on a predetermined offset voltage 28. That is, the failure detecting unit 300 detects the maximum value 30 or the minimum value 31 and the second sinusoidal output signal 9 of the first sinusoidal output signal 8 based on the predetermined offset voltage 28, (30) or the minimum value (31) of the resolver exceeds a predetermined threshold value (29), and when the predetermined threshold value (29) is exceeded, the state of the first and third ends of the resolver And the state of the second stage and the fourth stage is judged as a failure state (disconnection or short circuit). Here, the predetermined threshold value 29 may be +0.6V or -0.6V. However, the predetermined threshold value 29 may vary depending on the configuration, number and value of the passive element or the active element inside or outside the failure detection circuit according to the present invention.

At this time, the predetermined offset voltage (V_offset) 28 can be calculated by the following equation.

V1 is the resistance of the first or second voltage input terminal and the resistor R3 is connected to the series contact resistors 22 and 23 of the first or second sine wave signal output part 210 or 220, And R4 is the history contact resistance 24 (25) of the first or second sinusoidal signal output unit 210 (220).

More specifically, when the first sinusoidal output signal (V_S1 + S3) (8) exceeds a predetermined threshold value (29) on the basis of a predetermined offset voltage (28), the failure detecting section (300) It can be determined that the first stage and the third stage of the failure are in a failure state. If the first sinusoidal output signal V_S1 + S3 (8) does not exceed the predetermined threshold value (29) based on the predetermined offset voltage (28), the fault detector (300) The first stage and the third stage can be judged as a normal state.

When the second sinusoidal output signal V_S2 + S4 (9) exceeds a predetermined threshold value (29) on the basis of the predetermined offset voltage (28), the failure detecting section (300) It is possible to determine that the stage and the fourth stage are in a failure state. If the second sinusoidal output signal V_S2 + S4 (9) does not exceed the predetermined threshold value (29) based on the predetermined offset voltage (28), the fault detector (300) The second stage and the fourth stage can be judged as a normal state.

Hereinafter, the operation mechanism of the resolver failure detection circuit 1 according to the present invention will be described in more detail.

3, when the first stage output signal 2 and the third stage output signal 4 of the resolver are normally input to the first signal coupling unit 110, the first sinusoidal output signal 8 It can be confirmed that a sinusoidal waveform is shown on the basis of the predetermined offset voltage 28. That is, the maximum value 30 or the minimum value 31 of the first sinusoidal output signal 8 in FIG. 3 is within + 0.6V or -0.6V which is the predetermined threshold value 29 from the predetermined offset voltage 28 It exists. Therefore, the failure detecting unit 300 determines that the first sinusoidal output signal 8 is not in a state where the first sinusoidal output signal 8 does not exceed the predetermined threshold value 29 based on the predetermined offset voltage 28, The connection state between the first stage and the third stage is determined as a normal state. This is because when the first stage output signal 2 and the third stage output signal 4 of the resolver are normally input, the first stage output signal 2 of the resolver and the third stage output signal 4 The difference between the maximum value and the minimum value of the first sinusoidal output signal 8 is close to the predetermined offset voltage 28. [ That is, only the component of the sensing error level appears close to the predetermined offset voltage 28.

4, the second stage output signal 3 of the resolver is normally input to the second signal coupling section 120, while the fourth stage output signal 5 of the resolver is input to the second signal coupling section 120. However, It can be confirmed that the second sinusoidal output signal 9 is formed higher than the predetermined offset voltage 28 when it is not normally inputted into the output terminal 120. [ That is, FIG. 4 shows that the maximum value 30 of the second sinusoidal output signal 9 exists from the predetermined offset voltage 28 to exceed the predetermined threshold value 29 + 0.6V. Therefore, the failure detecting unit 300 determines that the second sinusoidal output signal 9 corresponds to a case where the second sinusoidal output signal 9 exceeds the predetermined threshold value 29 based on the predetermined offset voltage 29, And judges the connection state of the second stage and the fourth stage as a failure state (disconnection or short circuit). This is because, when any one of the second stage output signal (3) or the fourth stage output signal (5) of the resolver is short-circuited with the excitation signal, the second sinusoidal output signal (9) The maximum value or the minimum value of the second sinusoidal output signal 9 exceeds the predetermined threshold value 29 because the second sinusoidal output signal 9 is excessively large beyond the steady state range.

The operating mechanism of the resolver failure detection circuit 1 according to the present invention is such that the first stage output signal 2 and the third stage output signal 4 of the resolver are normally input and the second stage output signal 3 3, 4 and 5 (5) are short-circuited or disconnection, and the first, second, third and fourth output signals 2, 3, 4 and 5 It will be understood that the same mechanism as the above-described mechanism works in accordance with the short-circuiting and disconnection.

The resolver failure detection circuit of the motor according to the present invention relates to a resolver failure detection circuit for one motor, and a plurality of the present invention can be used when the number of motors used increases.

It will be apparent to those skilled in the art that many other modifications and variations are possible in light of the above teachings and the scope of the present invention should be construed on the basis of the appended claims something to do.

1: Resolver failure detection circuit according to the present invention
2: Resolver's first-stage output signal (V_S1)
3: Resolver's second-stage output signal (V_S2)
4: Resolver's third-stage output signal (V_S3)
5: Resolver's fourth-stage output signal (V_S4)
6: a signal in which the first-stage output signal of the resolver and the third-stage output coral are coupled
7: A signal in which the second stage output signal of the resolver and the fourth stage output coral are coupled
8: first sine wave output signal 9: second sine wave output signal
10: first capacitor (C) 11: second capacitor
12: third capacitor 13: fourth capacitor
14: first resistor (R1) 15: second resistor
16: third resistor 17: fourth resistor
18; Fifth resistor (R2) 19: sixth resistor
20: first applied voltage 21: second applied voltage
22: seventh resistor (R3) 23: eighth resistor
24: resistor 9 (R4) 25: resistor 10
26: first operational amplifier (OP AMP) 27: second operational amplifier (OP AMP)
28: Offset voltage 29: Threshold
30: maximum value of the first or second sinusoidal output signal
31: minimum value of the first or second sinusoidal output signal
40: inverter microcomputer 50: resolver
60: Resolver Fault Detection Circuit
100: Signal coupling section
110: first signal coupling section
111: first resolver output signal input terminal
112: third resolver output signal input terminal 113: first voltage input terminal
120: second signal coupling section
121; The second resolver output signal input
122: fourth resolver output signal input terminal 123: second voltage input terminal
200: Sinusoidal wave signal output section
210: first sinusoidal signal output unit 220: second sinusoidal signal output unit
300:

Claims (16)

A circuit for detecting a fault of a resolver,
A signal coupling portion coupling the resolver output signal;
A sinusoidal signal output unit for converting the coupled signal to generate a sinusoidal output signal; And
And a fault detector for determining whether the sine wave output signal exceeds a predetermined threshold value based on a predetermined offset voltage,
Wherein the signal coupling unit comprises:
A first signal coupling unit coupling the first stage output signal (V_S1) of the resolver and the third stage output signal (V_S3); And
And a second signal coupling portion coupling the resolver's second-stage output signal (V_S2) and the fourth-stage output signal (V_S4)
Wherein the first signal coupling unit comprises:
A first resolver output signal input terminal to which one capacitor C and one resistor R1 are connected in series and receives the first stage output signal V_S1 of the resolver;
A third resolver output signal input terminal having one capacitor and one resistor connected in series and receiving the third-stage output signal V_S3 of the resolver; And
A first voltage input terminal having a resistor R2 connected in parallel with the first resolver output signal input terminal and the third resolver output signal input terminal and having a predetermined voltage V1 applied to the resistor R2; Included resolver failure detection circuit.
delete The method according to claim 1,
Wherein the sinusoidal signal output unit comprises:
A first sinusoidal signal output unit for converting a signal obtained by coupling the first stage output signal V_S1 of the resolver and the third stage output signal V_S3 to generate a first sinusoidal output signal V_S1 + S3; And
A second sinusoidal signal output unit for converting a signal coupled between the second stage output signal V_S2 of the resolver and the fourth stage output signal V_S4 to generate a second sinusoidal output signal V_S2 + S4;
And a resistor connected in series with said resolver.
The method according to claim 1,
Wherein the failure detection unit comprises:
Wherein when the first sinusoidal output signal (V_S1 + S3) exceeds a predetermined threshold value based on a predetermined offset voltage, the first and third stages of the resolver are determined to be in a fault state. .
The method according to claim 1,
Wherein the failure detection unit comprises:
And the second and fourth stages of the resolver are determined to be in a fault state when the second sinusoidal output signal (V_S2 + S4) exceeds a predetermined threshold value based on a predetermined offset voltage. .
The method according to claim 1,
The predetermined offset voltage (V_offset)

Is calculated by the following equation.
The method according to claim 1,
Wherein the predetermined threshold value is + 0.6V or -0.6V.
delete The method according to claim 1,
Wherein the second signal coupling unit comprises:
A second resolver output signal input terminal having one capacitor and one resistor connected in series and receiving the second output signal V_S2 of the resolver;
A fourth resolver output signal input terminal having one capacitor and one resistor connected in series and receiving the fourth-stage output signal V_S4 of the resolver; And
A second voltage input terminal having one resistor (R2) connected in parallel to the second resolver output signal input terminal and the fourth resolver output signal input terminal and to which a predetermined voltage is applied to the resistor (R2);
And a resistor connected in parallel with said resolver.
The method of claim 3,
The first sinusoidal output signal (V_S1 + S3)

Is calculated by the following equation.
The method of claim 3,
The second sinusoidal output signal (V_S2 + S4)

Is calculated by the following equation.
The method of claim 3,
Wherein the first sinusoidal signal output unit comprises:
A resistor R3 connected in series to the operational amplifier OPAMP and a resistor R4 connected in parallel to the operational amplifier OPMP, Wherein a signal obtained by coupling the first stage output signal (V_S1) of the resolver and the third stage output signal (V_S3) is input.
The method of claim 3,
Wherein the second sinusoidal signal output unit comprises:
(OP AMP), a resistor connected in series to the operational amplifier (OP AMP), and a resistor connected in parallel to the operational amplifier (OP AMP), and the second terminal of the resolver And a signal obtained by coupling the output signal (V_S2) and the output signal (V_S4) of the fourth stage is input to the resolver.
10. The method of claim 9,
The capacitors and the resistors of the second resolver output signal input terminal and the fourth resolver output signal input terminal have the same capacitor value C and the same resistance value R1,
Wherein the resistance of the second voltage input terminal and the applied voltage have the same resistance value (R2) and the same voltage value (V1).
14. The method of claim 13,
A resistor connected in series to the operational amplifier in the second sinusoidal signal output unit and a resistor connected in parallel to the operational amplifier are connected in series to the operational amplifier OP AMP in the first sinusoidal signal output unit And a resistor R4 connected in parallel to the operational amplifier OPMP and having the same resistance value R3 and R4, respectively. The method according to claim 1,
The capacitors and resistors of the first resolver output signal input terminal and the third resolver output signal input terminal have the same capacitor value C and the same resistance value R1,
Wherein the resistance of the first voltage input terminal and the applied voltage have the same resistance value (R2) and the same voltage value (V1).

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