KR101602158B1 - Device status management method and apparatus through memory improvement - Google Patents

Abstract

The present invention relates to a defect status information management device for a test target apparatus. The device includes: a defect determining unit which determines the defect of the test target apparatus; a non-volatile memory area which stores the error code status information generated by the defect determining unit; a volatile memory area including parallel random access memory (RAM) areas; and a memory controller managing the memory areas. The memory controller stores the error code status information to the volatile memory area at first, converts the error code status information in the volatile memory area to error code status values in the minimum memory units to store the information to a memory bit corresponding to a predetermined fault number in the non-volatile memory area when the data in the volatile memory area is stored in the non-volatile memory area secondarily.

Description

TECHNICAL FIELD [0001] The present invention relates to a device status management method and apparatus,

The present invention relates to a method and apparatus for managing the state of aviation electronic equipment, and more particularly, to a method and apparatus for managing an aviation electronic equipment or an operational flight program (OFP) by reducing unnecessary waste of a memory space, ≪ / RTI >

There are numerous error codes for error management of avionics or OFP. These error codes are managed by a mission computer (MC), and even if a power down occurs in a mission computer, the error codes must be stored in a nonvolatile memory area for continuous management of error codes and have persistence. As the function and performance of the aircraft develops, the number of error codes required to maintain maintenance has increased, and each error code has to periodically store and manage the current error code status values at specific intervals in order to have persistence, The increase in the size of the data to be stored and managed increases the performance of the entire avionics system due to the lack of hardware memory space in parallel and the increase of the data processing processing for maintaining the data.

1 is a diagram illustrating a method of storing data from a volatile memory area to a nonvolatile memory area including a RAM (Random Access Memory) according to a conventional method.

Referring to FIG. 1, in the error code management method of the conventional mission computer, when error code data of the volatile memory area 110 is written in the non-volatile memory area 120, I have used the method of transferring it as it is. That is, the mission computer firstly generates error code related information, writes it to the volatile memory area 110, and transfers the information to the nonvolatile memory area 120. The error code 1 written as the first word is directly transferred to the non- Can also be written as the first word in region 120. [

That is, conventionally, there is a problem that the memory area is insufficient as the data type and the size of the error codes are stored in the nonvolatile memory area.

It is an object of the present invention to solve the above-mentioned problems and to provide an apparatus management system and a system management method, which can reduce waste of hardware storage space in unnecessary parallel through a minimum storage area in order to more efficiently manage error codes in an aircraft, A method and an apparatus.

According to an aspect of the present invention, there is provided an apparatus for managing defect information of a device under test, including: a defect determination unit for determining whether a device under test is defective; a nonvolatile memory for storing error code status information generated by the defect determination unit; And a memory controller for managing the memory area, wherein the memory controller stores the generated error code state information in a primary memory area of the volatile memory Volatile memory area, and when the data of the volatile memory area is secondarily stored in the non-volatile memory area, one error code status information of the volatile memory area is converted into an error code status value of the minimum memory unit, A memory bit at a position corresponding to a predetermined fault number Can.

The error code status value of the minimum storage unit may be an error code status value of 1 bit.

One error code state information stored in the volatile memory area may be 32-bit data.

The error code status value may be a value indicating an error according to the corresponding fault number.

The storage location may be determined through a shift operation such that the error code state value is stored at a location corresponding to each fault number.

The non-volatile memory area may be composed of a memory array based on 32-bit data processing.

The period of storing the data of the volatile memory area in the nonvolatile memory area may be set to be constant.

The equipment under test may include avionics equipment or avionics software programs.

According to another aspect of the present invention, there is provided a defect management method for a device under test, comprising: a defect determination step of determining whether a defect of a device under test is defective; and a nonvolatile memory And a memory control step of managing a volatile memory area including a random access memory (RAM) area, wherein the memory control step comprises: storing the generated error code state information primarily in the volatile memory area And storing the data of the volatile memory area in a secondary nonvolatile memory area, wherein the step of storing the nonvolatile memory area in the nonvolatile memory area includes storing one error code status information of the volatile memory area in the minimum memory unit Into an error code state value to determine the state of the nonvolatile memory area The position corresponding to the re-determined fault number can include the step of storing in a memory bits.

According to the apparatus state management method and apparatus of the present invention, unnecessary waste of memory space can be minimized by minimizing the use of memory space for error code management and ease of maintenance and improvement of aviation electronics by minimizing hardware constraints in parallel with memory space .

1 illustrates a method of storing data in a nonvolatile memory area in a volatile memory area including a RAM area according to a conventional method,
FIG. 2 illustrates an apparatus state management apparatus according to an embodiment of the present invention. FIG.
3 is a diagram illustrating a method of storing data from a volatile memory area to a nonvolatile memory area in an apparatus state management apparatus according to an embodiment of the present invention;
4 is a diagram for explaining a shift operation for shifting 32-bit data to a nonvolatile memory area,
5A and 5B are diagrams for explaining a method of arranging and reading a specific array according to a fault number,
6 is a flowchart illustrating an apparatus state management method according to an exemplary embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate the understanding of the present invention, the same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

Device state management device

FIG. 2 illustrates an apparatus state management apparatus according to an exemplary embodiment of the present invention. Referring to FIG. 2, the apparatus state management apparatus 200 according to an exemplary embodiment of the present invention may include a defect determination unit 210, a memory controller 220, and a memory region 230.

Referring to FIG. 2, the apparatus state management apparatus 200 may be a mission computer, which determines whether there is an OFP in an anti-aircraft device or an anti-aircraft device, and stores the information in the memory area 230.

The defect judging unit 210 judges whether or not the equipment to be tested is error based on the error code. Then, the state result of judging whether or not an error has occurred can be generated as data. The defect determination unit 210 may be located outside the apparatus state management apparatus 200. [ The defect determination unit 210 determines the presence or absence of a defect of various functions of the device under test, and can determine whether the function is an error based on an error code corresponding to the function. For example, regarding the function 1 of the first avionics device, it is determined whether an error is caused by the first error code. If the function 2 of the first avionics device is judged as an error through the second error code, And judges whether or not an error has occurred by using a corresponding error code for the function. The determination result may be generated with error code state information, and the error code state information may include the contents of the error code. For example, it may include the type of error, error identification information (which may correspond to a fault number (FN) or a test number). The fault number or test number is the father identification number so that the defect or defect test can be identified according to the properties of the defect or defect test. The defect determination unit 210 should know the error code corresponding to the fault number or the test number, and record it as the identification information. Or the error code status information may be sequentially generated according to a preset fault number sequence.

The memory controller 220 is a component that manages and controls the memory area 230. The memory controller 220 receives the error code status information from the defect determination unit 210 and stores the error code status information in the memory area 230. The memory controller 220 firstly stores the error code state information in the volatile memory area 232 first. Then, the data in the volatile memory area 232 is written into the nonvolatile memory area 234 every predetermined period.

The volatile memory area 232 is a memory area in which error code state information is primarily stored. Since the error code state information is written as it is, the volatile memory area 232 can have a size of 32 bits per error code. The data held in the volatile memory area 232 when the power is turned off may be lost. Therefore, the memory stored in the volatile memory area 232 must be written into the nonvolatile memory area 234 every predetermined period. The nonvolatile memory area 234 may not lose data in the memory even if the power is turned off.

The operation of the memory controller 220 will be described in more detail with reference to FIG.

3 is a diagram illustrating a method for storing data from a volatile memory area to a nonvolatile memory area in an apparatus state management apparatus according to an embodiment of the present invention.

Referring to FIG. 3, in moving the data of the volatile memory area 310, which is primarily stored, to the nonvolatile memory area 320 in a predetermined period, the memory controller turns on / off 32-bit error code status information only the value of 1 bit indicating only the on / off state can be processed and recorded in the nonvolatile memory area 320. This is not necessarily limited to one bit but may be represented by a value of the minimum memory unit. In the present embodiment, the bit type will be described as a base. To maximize the performance of the processor, the memory controller can apply memory management functions based on computation shift operations, and can be optimized for 32-bit computer systems through 32-bit basic data processing. However, the present invention is not limited to 32 bits but may be applied to data processing such as 16 bits and 64 bits.

The memory controller generates a 1-bit error code status value, which may be a value indicating whether or not an error has occurred according to the fault number. That is, information indicating the presence or absence of an error in the 32-bit error code status information can be parsed and generated as a value of 1 or 0.

The memory controller can determine a position to store the generated error code status value through a shift operation based on a fault number (FN). This will be described in detail with reference to FIG.

4 is a diagram for explaining a shift operation for transferring 32-bit data to a non-volatile memory area.

Referring to FIG. 4, in the 32-bit data processing, the error code state information of the volatile memory area can be written into the nonvolatile memory space by processing the presence or absence of the state with only a value of 1 or 0, The position is determined by a shift operation so that data can be read and written at a predetermined position.

Can be sequentially written from the fault number 0, one bit at a time, based on the fault number FN. That is, the error code status value (0 or 1) of FN 0 can be written to the uppermost rightmost bit, and FN 1 to FN 31 can be written to the first word line to the left of FN 0. Then, 32 error code status values from FN 32 to FN 63 are written to the second word line. The second word line may be filled from the left. Then, the third word line is filled with the error code status value of FN 64 to FN 95, and is filled from the right side.

This can be expressed as WORD = COMPACT_ACTIVE + (FN > 5). Here, the COMPACT_ACTIVE value is a variable.

5A and 5B are diagrams for explaining a method of arranging and reading a specific array according to a fault number.

Referring to FIG. 5A, when it is desired to read out an error code status value of FN = 0, a number for position determination is obtained with reference to the target FN to be read and 0x1F. 00011111 of Ox1F represents a maximum value for shifting to a value representing 31 in binary number, and serves to guide only a value of 31 or less. That is, it indicates that 32 bits or more are not allowed. 00000, Compact Active reads the least significant bit of the first array.

Referring to FIG. 5B, when it is desired to read out an error code status value of FN = 79, since the FN is 79, it is represented by binary number 1001111 (2). Since discarded 1 is the number of the 6th digit (2 of 6: 26), the value must be found in the 3rd array below the 2th column based on the 5th digit (5th power of 2: 25). If the 5-digit number 01111 is ANDed with 0x1F, 01111 is output. Based on this, the 16th bit of the third array 2 columns below the first array is read out. The writing method is the same as the reading method.

In this way, the position of the error code status value can be automatically calculated based on the FN, and written into and read from the corresponding position.

How to Manage Equipment Status

6 is a flowchart illustrating an apparatus state management method according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the mission computer may generate error code status information based on the presence or absence of a defect based on the error code, or may receive error code status information from the external defect presence / absence determination apparatus (S610). Then, the error code state information is sequentially stored in the volatile memory area (S620). The data in the volatile memory area is written to the nonvolatile memory area at regular intervals. Therefore, it is determined whether the specific cycle has been reached (S630), and the error code is written into the nonvolatile memory area when the cycle is reached. At this time, the error code state information can be written into the error code state value of the minimum memory unit (e.g., bit unit) and written (S640). The error code status value can be generated with a value of 1 bit. This may be a value indicating an abnormality depending on the fault number. That is, information indicating the presence or absence of an error in the 32-bit error code status information can be parsed and generated as a value of 1 or 0.

A fault number is extracted from the error code state information while generating an error code state value (S650), and a position to be written in the nonvolatile memory area is determined through a shift operation on the fault number. As the shift operation, a shift operation method in which 32-bit error code status values are sequentially stored while changing word lines can be used when 32-bit is used as a reference. Once the location is determined, the corresponding error code state value is stored in the nonvolatile memory area at the determined location (S670).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions as defined by the following claims It will be understood that various modifications and changes may be made thereto without departing from the spirit and scope of the invention.

Claims (9)

A defect judging unit for judging whether or not the equipment to be tested is defective;
A volatile memory area including a non-volatile memory area and a random access memory (RAM) area for storing error code status information generated by the defect determination part; And
And a memory controller for managing the memory area,
Storing the generated error code status information in the volatile memory area,
Wherein when the data of the volatile memory area is secondarily stored in the nonvolatile memory area, one error code status information of the volatile memory area is converted into an error code status value of the minimum memory unit, Wherein the defect management information is stored in a memory bit at a position corresponding to the fault number. The method according to claim 1,
Wherein the error code status value of the minimum storage unit is a 1-bit error code status value. The method according to claim 1,
And the one error code state information stored in the volatile memory area is 32-bit data. The method according to claim 1,
Wherein the error code status value is a value indicating an abnormality according to the fault number. The method according to claim 1,
Wherein the storage location is determined by a shift operation so that the error code status value is stored at a location corresponding to each fault number. The method according to claim 1,
Wherein the non-volatile memory area comprises a 32-bit data processing based memory array. The method according to claim 1,
Wherein the cycle of storing data in the volatile memory area in the nonvolatile memory area is set to be constant. The method according to claim 1,
Wherein the device under test includes an avionics device or an avionics software program. A defect judgment step of judging whether or not the equipment to be tested is defective; And
And a memory control step of managing a volatile memory area including a non-volatile memory area for storing error code state information generated in the defect determination step and a RAM (Random Access Memory) area,
Storing the generated error code state information primarily in the volatile memory area; And
And storing data of the volatile memory area in a secondary nonvolatile memory area,
Wherein the step of storing in the nonvolatile memory area converts one error code state information of the volatile memory area into an error code state value of a minimum memory unit to store a memory bit at a position corresponding to a predetermined fault number in the nonvolatile memory area, And storing the defect status information of the test target device in the defect management table.

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