KR101672978B1 - Semiconductor memory device - Google Patents

Abstract

A memory device is disclosed. The memory device includes a core region including a plurality of banks, a command timing control section for outputting a command signal delayed by delaying a read signal or a write signal upon activation of a delay control signal, a command timing control section for delaying a bank address A bank address timing control section for outputting a delayed bank address by decoding the delayed bank address to generate a bank selection signal for selecting one bank among the plurality of banks by decoding the delayed bank address, A column address timing control unit for outputting a read signal delayed by delaying the read signal or the write signal or a delayed write signal when the delay control signal is activated, The delayed And a column address transfer unit for transferring the column address to the plurality of banks in response to the write signal or the delayed write signal.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor memory device.

As is well known, the memory device is composed of a core region including a plurality of banks and peripheral circuits for controlling input / output of data stored in the core region. A bank is a collection of memory cells storing data, and memory cells are arranged in a matrix form between a plurality of rows and columns. A predetermined address is set in each row and column.

In the operation of the core region in the memory device, the row address is first selected to amplify the data of the corresponding word line, and the column address is selected and the amplified data is transferred to the data line. At this time, in order to transfer the correct data, the column selection must be performed while the data of the word line is sufficiently amplified. To do this, in the memory development stage, the test is performed to delay the column selection signal to different delay amounts in the test mode.

1 is a configuration diagram of a conventional memory device.

1, a conventional memory device includes a command timing control unit 101, a bank selection unit 103, a column selection signal transfer unit 105, a column address transfer unit 107, and a core region 109 .

The command timing control section 101 outputs a delayed command signal CAS_D by delaying the read signal CASRD or the write signal CASWT when the delay control signal YSTM is activated.

The delay control signal YSTM is used in the delay test mode for ensuring the operation margin of the column select signal YS <0: 7> and the column address ADDYS (2: 9>) in the core region 109 Lt; / RTI &gt;

The read signal CASRD is a signal activated in the memory device when a column address strobe signal CAS applied from the outside of the memory device is activated and a write enable signal WE is inactivated, (CASWT) is a signal activated in the memory device when the column address strobe signal CAS and the write enable signal WE are activated.

The bank selection unit 103 decodes the bank address BKADD <0: 2> to activate one of the bank selection signals BK <0: 7>. Since it is assumed that the core region 109 includes eight banks, the number of the bank selection signals BK <0: 7> is also eight.

The column selection signal transfer unit 105 transfers the delayed command signal CAS_D to the column selection signal YS <0: 7> of the selected bank by the bank selection signal BK <0: 7>. For example, when the bank selection signal BK <2> is activated, the delayed command signal CAS_D is transferred to the column selection signal YS <2>.

The column address transfer unit 107 strobes the input address ADDRD <2: 9> with the read signal CASRD in the read period and outputs the column address ADDYS <2: 9> In the write section, the input address ADDWT <2: 9> is strobeed with the write signal CASWT and transferred to the core region 109 with the column address ADDYS <2: 9>.

In the core region 100, a specific column is selected by the input column select signal YS <0: 7> and the column address ADDYS <2: 9>, and data of the memory cell is input / output.

The conventional memory device has only the command timing control section 101 that delays the command signal such as the read signal CASRD or the write signal CASWT as described above. The column selection signal transfer section 105 outputs the delayed command signal CAS_D (BK < 0: 7 &gt;) are activated are different from each other. Also, there is a problem in that the activation timing between the column selection signal YS <0: 7> and the column address ADDYS <2: 9> not delayed becomes different from each other in the core region 109 as well.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device capable of ensuring a margin with respect to a bank address and a column address in a delay test mode of a column selection signal.

In order to achieve the above object, a memory device according to the present invention is a memory device including a core region including a plurality of banks, a command timing for outputting a command signal delayed by delaying a read signal or a write signal upon activation of a delay control signal A bank address timing control unit for delaying a bank address when the delay control signal is activated and outputting a delayed bank address to generate a bank selection signal for selecting one of the plurality of banks by decoding the delayed bank address; And a column selection signal transfer unit for transferring the delayed command signal to the column selection signal of the bank selected by the bank selection signal.

A column address timing controller for outputting a read signal or a delayed write signal delayed by delaying the read signal or the write signal upon activation of the delay control signal and a column address controller for outputting a column address in response to the delayed read signal or the delayed write signal And a column address transfer unit for transferring the column address to the plurality of banks.

The delay amounts of the command timing control section, the bank address timing control section and the column address timing control section can be designed to be adjustable.

The column address may be strobeed by the delayed read signal in the read period to be transferred to the plurality of banks or may be strobeed by the delayed write signal in the write period to be transferred to the plurality of banks.

According to the present invention, the command signal is delayed and the bank address and the column address are also delayed and transferred to the core region, thereby ensuring the margin between the column selection signal and the bank address and the column address.

Further, there is an advantage that the memory development period can be shortened by performing the test while adjusting the delay amount of the column select signal and the column address at the margin test of the core region.

1 is a configuration diagram of a conventional memory device;
2 is a configuration diagram of an embodiment of a memory device according to the present invention;
3 is an internal configuration view of the core region 109 of FIG.
4 is a circuit diagram of an embodiment of the command timing control section 101 of FIG.
5 is a circuit diagram of an embodiment of the bank address timing control section 201 of FIG.
6 is a circuit diagram of an embodiment of the column selection signal transfer unit 105 of FIG.
7 is a circuit diagram of an embodiment of the column address timing controller 203 of FIG.
8 is a circuit diagram showing an embodiment of the column address transfer unit 107 of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

2 is a block diagram of a memory device according to an embodiment of the present invention.

2, the memory device according to the present invention includes a core region 109 including a plurality of banks, a read signal CASRD or a write signal CASWT at the time of activation of the delay control signal YSTM A command timing control section 101 for outputting a delayed command signal CAS_D and a bank address ADDBK_D <0: 2> delayed by delaying the bank address ADDBK <0: 2> upon activation of the delay control signal YSTM, , A bank address timing control section 201 for outputting a bank selection signal BK <0: 7> for decoding one bank of the plurality of banks by decoding the delayed bank address ADDBK_D <0: 2> A column selection signal transfer unit 107 for transferring the delayed command signal to the column selection signals YS <0: 7> of the banks selected by the bank selection signals BK <0: 7> The read signal CASRD or the write signal CASWT is delayed when the delay control signal YSTM is activated A column address timing control section 203 for outputting a delayed read signal CASRD_D or a delayed write signal CASWT_D and a column address ADDYS <2: 9 in response to a delayed read signal CASRD_D or a delayed write signal ADDWT_2: >) To a plurality of banks.

In this embodiment, it is assumed that the core region 109 is composed of eight banks.

The read signal CASRD and the write signal CASWT are command signals activated in the memory device by the column address strobe signal CAS. Specifically, when the column address strobe signal CAS is activated to high and the write enable signal WE is deactivated to low in the command decoder, the read signal CASRD is set to ' High ', and when the column address strobe signal CAS and the write enable signal WE are both' high ', the write signal CASWT is activated to' high '.

The delay control signal YSTM is a signal activated in the test mode for ensuring the operation margin of the column selection signal YS <0: 7> in the core region 109. The command timing control section 101, the bank address timing control section 201 and the column address timing control section 203 delay and output the input signal or address when the delay control signal YSTM is activated high. At this time, each control unit can be designed so that the delay amount can be adjusted.

The command timing control section 101 delays the read signal CASRD or the write signal CASWT which is the command signal at the time of activation of the delay control signal YSTM and outputs the delayed command signal CAS_D. The delayed command signal CAS_D determines the timing at which the column selection signal YS <0: 7> is activated in the core region 109. That is, by adjusting the delay amount for delaying the command signal in the test mode, the word line is selected in the bank, and the column selection signal YS <0: 7> is activated with the most appropriate margin during the data amplification time And determines the timing.

The bank address timing control section 201 delays the bank address ADDBK <0: 2> input at the time of activation of the delay control signal YSTM and outputs the delayed bank address ADDBK_D <0: 2>. Since the conventional memory device has only a configuration for delaying only the command signal in the test mode, it is difficult to match the timing between the delayed command signal CAS_D and the bank address ADDBK <0: 2> that has not been delayed. In order to solve this problem, a configuration is added in which a bank address (ADDBK <0: 2>) is also delayed as in the case of a command signal. Here, it is preferable that the delay amounts of the command timing control section 101 and the bank address timing control section 201 are the same.

The bank selection unit 103 decodes the delayed bank address ADDBK_D <0: 2> to generate a bank selection signal BK <0: 7> for selecting one of the banks in the core region 109 Output.

Table 1 shows the relationship between the delayed bank address ADDBK_D <0: 2> and the corresponding bank selection signals BK <0> to BK <7>.

BKADD_D <0: 2> The bank selection signal BKADD_D <0: 2> The bank selection signal 000 BK <0> 100 BK <4> 001 BK <1> 101 BK <5> 010 BK <2> 110 BK <6> 011 BK <3> 111 BK <7>

The column selection signal transfer unit 105 receives the delayed command signal CAS_D and the bank selection signals BK <0: 7> and outputs the delayed command signals CAS_D to the bank selection signals BK <0: 7> To the column select signal YS <0: 7> of the bank selected by the column select signal YS <0: 7>. This will be described later in detail with reference to FIG.

The column address timing controller 203 outputs the delayed read signal CASRD_D by delaying the read signal CASRD in the read interval and activates the delayed write signal CASRD_D in the write interval when the delay control signal YSTM is activated, And outputs a delayed light signal CASWT_D. The conventional memory device has only a configuration in which only the command signal is delayed in the test mode and the margin between the column selection signal YS <0: 7> and the column address ADDYS <2: 9> The delayed read signal CASRD_D or the delayed write signal CASWT_D is used to match the timing with the column select signal YS <0: 7>. Here, it is preferable that the delay amounts of the command timing control section 101 and the column address timing control section 203 are the same.

The reason why the delayed read signal CASRD_D and the delayed write signal CASWT_D are distinguished from each other is that the cache latency CL and the write latency WL may be different from each other and the optimum margin in the core region 109 may be secured This is because the delay amount of the read signal CASRD and the delay amount of the write signal CASWT may be different from each other.

The column address transfer unit 107 transfers the column address ADDYS <2: 9> strobeed by the delayed read signal CASRD_D or the delayed write signal CASWT_D to the core region 109. Specifically, in the read period, the input read address ADDRD <2: 9> is strobeed with the delayed read signal CASRD_D and transferred to the column address ADDYS <2: 9> ADDWT <2: 9>) with the delayed write signal CASWT_D and transfers the strobe signal to the column address ADDYS <2: 9>.

3 is a block diagram of an embodiment of the core region 109 of FIG. Although the present embodiment has exemplified the case of including eight banks (BANK0 to BANK7), the concept of the present invention can be applied to four banks, sixteen banks, and the like.

The bank selection unit 103 decodes the delayed bank address ADDBK_D <0: 2> to activate one of the eight bank selection signals BK <0> to BK <7>, activates the activated bank selection signals BK The column select signals YS <0> to YS <7> corresponding to the selected one of the banks BANK0 to BANK7 are applied.

The column address ADDYS <2: 9> transferred from the column address transfer unit 107 is input to all the banks BANK0 to BANK7 in the core region 109 to allow data input and output.

4 is a circuit diagram of an embodiment of the command timing control section 101 of FIG.

4, the command timing control section 101 may include a NAND gate 401, a delay section 403, and two pass gates 405 and 407. [

When the delay control signal YSTM is activated, the pass gate 405 is turned off and the pass gate 407 is turned on so that the read signal CASRD or the write signal CASWT is input to the NAND gate 401, the delay unit 403, And the pass gate 407 and is transmitted as a delayed command signal CAS_D. When the delay control signal YSTM is inactivated, the pass gate 405 is turned on and the pass gate 407 is turned off so that the read signal CASRD or the write signal CASWT is passed through the delay unit 403 do.

When the delay control signal YSTM is inactivated, the NAND gate 401 prevents the command signals CASRD and CASWT from being transmitted to the delay unit 403, thereby preventing unnecessary current consumption due to the delay unit 403 The effect can be obtained. In addition, since the delay amount of the delay unit 403 can be designed to be adjustable, it is easy to find the optimum timing for ensuring the margin of the column selection signal YS <0: 7> using the test mode .

5 is a circuit diagram of one embodiment of the bank address timing controller 201 of FIG.

5, the bank address timing control section 201 includes three delay circuit sections 501 to 503. The delay circuit section 501 includes a NAND gate 511, a delay section 513, Gates 515 and 517, respectively.

The operation of the bank address timing control section 201 through the delay circuit section 501 will be described. The remaining delay circuit units 502 and 503 operate in the same manner.

When the delay control signal YSTM is activated, the pass gate 515 is turned off and the pass gate 517 is turned on, and the bank address ADDBK <0> is input to the NAND gate 511, the delay unit 513, And is transferred to the delayed bank address ADDBK < 0 > through the gate 517. When the delay control signal YSTM is inactivated, the pass gate 515 is turned on and the pass gate 517 is turned off so that the bank address ADDBK <0> is transferred without passing through the delay unit 513. [

The delayed command signal CAS_D and the bank selection signals BK <0> to BK <7> are delayed by a delay amount equal to that of the delay unit 403 of the command control unit 101, The timing to be inputted to the selection signal transmitting unit 105 can be adjusted. Similar to the command timing control section 101, the delay amount of the delay section 513 in the test mode can be adjusted.

6 is a circuit diagram of an embodiment of the column selection signal transfer unit 105 of FIG.

6, the column selection signal transfer unit 105 includes eight circuit units 601 to 608 for generating eight column selection signals YS <0> to YS <7> The inverter 601 may include two PMOS transistors PM61 and PM62, two NMOS transistors NM61 and NM62 and three inverters IV61, IV62 and IV63.

NMOS transistors NM61 and NM62 are turned on when the delayed command signal CAS_D and the bank selection signal BK < 0 > are activated to a high level by examining the operation of the column selection signal transfer unit 105 through the circuit unit 601. [ And the column selection signal YS <0> is activated to high while passing through the inverters IV61, IV62 and IV63. When the delayed command signal CAS_D is low, the column select signal YS <0> is also brought to a low state and held by the low latches PM62 and IV61. The column select signals YS <0> are transferred to the corresponding banks BANK0 and the remaining column select signals YS <1> to YS <7> are also activated to transfer the corresponding banks BANK1 to BANK7, Lt; / RTI &gt;

7 is a circuit diagram of an embodiment of the column address timing controller 203 of FIG.

7, the column address timing control section 203 includes a read signal delay circuit section 701 and a write signal delay circuit section 702. The read signal delay circuit section 701 includes a NAND gate 711, A portion 713 and two pass gates 715 and 717. [

The operation of the column address timing control section 201 through the read signal delay circuit section 701 will be described. The operation of the write signal delay circuit portion 702 is the same.

When the delay control signal YSTM is activated, the pass gate 715 is turned off and the pass gate 717 is turned on so that the read signal CASRD is supplied to the NAND gate 711, the delay portion 713, And is transferred to the delayed read signal CASRD. When the delay control signal YSTM is inactivated, the pass gate 715 is turned on and the pass gate 717 is turned off so that the read signal CASRD is transferred without passing through the delay unit 713. [ The delay amount of the delay unit 713 can be adjusted.

Here, the delay amount of the delay unit 713 for delaying the read signal CASRD and the delay amount of the delay unit 723 for delaying the write signal CASWT may be different from each other. This is because, when the cache latency CL in the read operation and the write latency WL in the write operation are different, the timing of strobeing the address in each operation may be different.

8 is a circuit diagram of an embodiment of the column address transfer unit 107 of FIG.

As shown in FIG. 8, the column address transfer unit 107 receives the addresses ADDRD <2> to ADDRD <9> input in the read interval or the addresses ADDWT <2> to ADDWT < The transfer circuit 801 includes four PMOS transistors PM81 to PM84, four PMOS transistors PM81 to PM84, and eight transfer circuits 801 to 808 for transferring the four PMOS transistors PM81 to PM84 to the column addresses ADDYS <2> to ADDYS < NMOS transistors NM81 to NM84 and latch portions IV81 and IV82.

The operation of the column address transfer unit 107 through the transfer circuit unit 801 will be described.

When the address ADDRD <2> is input in the read interval, the delayed read signal CASRD_D is strobeed by the delayed read signal CASRD_D and transferred to the column address ADDYS <2> The transferred column address ADDYS < 2 > is held until the next address is input by the latch portions IV81 and IV82. Similarly, when the address ADDWT <2> is input in the write interval, it is transferred as the column address ADDYS <2> when the delayed write signal CASWT_D is activated.

In this way, the column address ADDYS <2: 9> is transferred through the eight transfer circuit units 801 to 808 and input to all the banks BANK0 to BANK7 of the core region 109. [

As described above, in the present invention, at the time of the margin test of the core region, the command signal is delayed to activate the column select signal, and at the same time, the bank address and the column address are delayed and transferred to the core region, A memory device capable of shortening a memory development period by making it possible to secure a margin and conducting a test while adjusting a delay amount of a column select signal and a column address.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, But the present invention is not limited thereto.

Claims (8)

A core region including a plurality of banks;
A command timing controller for delaying a read signal or a write signal and outputting a delayed command signal upon activation of a delay control signal;
A bank address timing control unit for delaying a bank address and outputting a delayed bank address when the delay control signal is activated;
A bank selector for decoding the delayed bank address to generate a bank select signal for selecting one of the plurality of banks; And
A column selection signal transfer unit for transferring the delayed command signal to a column selection signal of a bank selected by the bank selection signal;
&Lt; / RTI &gt;
Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
Wherein the delay amount of the command timing control section and the bank address timing control section is adjustable
Memory device.
Claim 3 has been abandoned due to the setting registration fee. The method according to claim 1,
The read signal
When the column address strobe signal is activated and the write enable signal is inactivated
Memory device.
Claim 4 has been abandoned due to the setting registration fee. The method according to claim 1,
The write signal
Activated when the column address strobe signal and the write enable signal are activated
Memory device.
Claim 5 has been abandoned due to the setting registration fee. The method according to claim 1,
A column address timing controller for delaying the read signal or the write signal and outputting a delayed read signal or a delayed write signal upon activation of the delay control signal; And
A column address transfer unit for transferring a column address to the plurality of banks in response to the delayed read signal or the delayed write signal,
&Lt; / RTI &gt;
Claim 6 has been abandoned due to the setting registration fee. 6. The method of claim 5,
The delay amount of the column address timing control section is adjustable
Memory device.
Claim 7 has been abandoned due to the setting registration fee. 6. The method of claim 5,
The column address
And is strobed by the delayed read signal in the read period to be transferred to the plurality of banks
Memory device.
Claim 8 has been abandoned due to the setting registration fee. 6. The method of claim 5,
The column address
Strobe is delayed by the delayed light signal in the write interval and is transferred to the plurality of banks
Memory device.

Images