KR101750699B1 - A method for ADC(analog-digital converter) circuit monitoring using DAC(digital-analog converter) circuit - Google Patents

Abstract

A method and apparatus for monitoring an ADC circuit condition using a DAC circuit are disclosed. The ADC circuit status monitoring method using the DAC circuit receives the recalibrated digital signal from the first register in the difference calculator and receives the calibrated digital signal from the second register to determine the difference between the calibrated digital signal and the recalibrated digital signal And controlling the ADC circuit status monitoring apparatus to transmit a correction request signal to the control unit when the difference value is out of the predetermined threshold range.

Description

[0001] The present invention relates to a method of monitoring an ADC circuit state using a DAC circuit,

The present invention relates to a circuit state monitoring method and apparatus, and more particularly, to a method and circuit for monitoring ADC circuit state using a DAC circuit.

The analog-to-digital conversion circuit is called an analog / digital (A / D) converter or simply an analog-digital converter (ADC), which converts an electrical signal into an electrical signal.

 The signal is difficult to store and easy to operate compared with the digital signal. Therefore, most of the electronic signals are now digitized and used. Generally, when an analog signal is converted into a digital signal, it is advantageous for noise of the signal. The distortion due to the conversion of the analog signal to the digital signal must be tolerated. The digital signal can be converted to an analog signal via a DAC.

For example, early telephones transmitted analog signals. As the switching network evolves, the voice signal is digitized by a pulse code modulation method, and the digitized voice signal is transmitted and decoded to an analog voice signal at the receiving end.

A digital-to-analog converter (DAC) is a D / A converter that converts an encoded electrical signal into an electrical signal (voltage, current, etc.). The signal conversion process of the DAC circuit is a reverse process of the signal conversion process of the circuit. Since the number of bits determined in the encoding process is determined, the accuracy of restoration is limited. The step signal can be output by converting the digital signal into the analog signal having the limited accuracy and the step signal can be restored to the original analog signal using the filter circuit. The ADC circuit and the DAC circuit are mainly represented by binary numbers and predetermined bits are predetermined. If the number of bits is large, the representation of the signal becomes high, the precision becomes high, the original signal can be restored, but the complexity of the processing circuit can be increased.

KR 10-2009-0034634

One aspect of the present invention provides a method of monitoring an ADC circuit condition using a DAC circuit.

Another aspect of the present invention provides an ADC circuit condition monitoring circuit using a DAC circuit.

An ADC (analog-digital converter) circuit status monitoring method using a DAC (digital-analog converter) circuit according to an aspect of the present invention is a method in which an ADC circuit status monitoring apparatus stores a digital signal corrected by a correction unit in a first register Controlling the ADC circuit state monitoring apparatus to store the corrected digital signal in the second register, and the ADC circuit state monitoring apparatus notifies the corrected digital signal transmitted by the first register to the first register, The ADC circuit status monitoring device is configured to store the recalibrated digital signal in the first register so that the ADC circuit status monitoring device stores the recalibrated digital signal in the first register Wherein the ADC circuit state monitoring apparatus comprises: Receiving the recalculated digital signal from the second register and receiving the calibrated digital signal from the second register to calculate a difference value between the calibrated digital signal and the recalibrated digital signal, And controlling the state monitoring apparatus to transmit a correction request signal to the control unit when the difference value is less than a predetermined threshold range.

Meanwhile, the ADC circuit status monitoring method using the DAC circuit may include controlling the ADC circuit status monitoring apparatus to generate a counter signal by operating a counter in the controller based on the correction request signal, And controlling the correction unit to reset the correction parameters of the correction algorithm by comparing the counter signal and the converted counter signal obtained by converting the counter signal through the DAC circuit and the ADC circuit.

Also, the corrected digital signal may be a signal obtained by converting an external input signal, which is an analog signal, into a digital signal through the ADC circuit, and then correcting the digital signal through the correction unit.

In the ADC circuit state monitoring method using the DAC circuit, the ADC circuit state monitoring apparatus determines whether to transfer the external input signal to the ADC circuit in the first selector or not, and to transmit the corrected digital signal to the ADC circuit And controlling the ADC circuit status monitoring apparatus to determine whether to forward the counter signal to the DAC circuit or to transmit the corrected digital signal to the DAC circuit in the second selection unit .

An apparatus for monitoring an analog-digital converter (ADC) circuit using a digital-analog converter (DAC) circuit according to another aspect of the present invention includes a control unit, and the control unit controls a digital signal Converting the corrected digital signal transferred by the first register into the digital signal through the DAC circuit and the ADC circuit, and outputting the corrected digital signal through the correction unit Correcting the digital signal to generate the recalculated digital signal, controlling the first register to store the recalibrated digital signal, receiving the recalibrated digital signal from the first register in the difference calculator, Receiving the corrected digital signal from a second register and comparing the corrected digital signal with the recalculated digit In case the control to calculate a difference value between the signal and the threshold range is beoteo the difference value is set, and can be configured to control to transmit the correction request signal to the controller.

The controller controls the counter to generate a counter signal based on the correction request signal. The counter corrects the counter signal and the counter signal through the DAC circuit and the ADC circuit, So as to reset the correction parameters of the correction algorithm.

Also, the corrected digital signal may be a signal obtained by converting an external input signal, which is an analog signal, into a digital signal through the ADC circuit, and then correcting the digital signal through the correction unit.

The control unit may control the first selector to determine whether to transfer the external input signal to the ADC circuit or to transmit the corrected digital signal to the ADC circuit, To transfer the signal to the DAC circuit or to determine whether to deliver the corrected digital signal to the DAC circuit.

A method and circuit for monitoring an ADC status using a DAC according to an embodiment of the present invention monitors the accuracy of a correction algorithm of a correction algorithm with a digital signal of an analog signal and re-sets the parameters of the correction algorithm when the accuracy is low, Accuracy can be increased. Therefore, it is possible to detect the change (aging) of the ADC circuit or peripheral circuit by measuring the output error of the ADC circuit, and to reset the previously set correction algorithm according to circuit function aging or environment change to maintain the output accuracy by continuously re- And life extension may be possible.

1 is a conceptual diagram showing an ADC circuit state monitoring apparatus using a DAC circuit according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating an ADC accuracy measurement operation of an ADC circuit condition monitoring apparatus according to an embodiment of the present invention.
3 is a conceptual diagram illustrating a procedure for resetting the correction algorithm of the ADC circuit according to the embodiment of the present invention.
4 is a flowchart illustrating a procedure for resetting the correction algorithm of the ADC circuit according to the embodiment of the present invention.
5 is a conceptual diagram illustrating a correction check procedure of a correction algorithm according to an embodiment of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

Hereinafter, an embodiment of the present invention discloses a self-test and diagnostic apparatus that calculates an error between an output value and an actual voltage (input) value in an analog-digital converter (ADC) having an output correcting algorithm.

A method and an apparatus for monitoring an analog-digital converter (ADC) circuit using a digital-analog converter (DAC) circuit according to an embodiment of the present invention can reset the correction algorithm when the correction error is out of the allowable range of the system . The ADC circuit status monitoring method and circuit using the DAC circuit can be applied to the structure for outputting the output value by performing the correction algorithm in all the mixed signal circuits including the ADC circuit.

Specifically, the ADC status monitoring method and apparatus using the DAC circuit are configured such that 1) the output value of the ADC circuit and 2) the output value of the corrected ADC circuit are converted into the register by the DAC circuit and the ADC circuit, And the degree of error of the current correction can be determined. As described above, when the correction error is out of the range allowed by the system, the parameters of the correction algorithm of the ADC circuit can be measured again using the internal counter circuit and the DAC roulette.

By measuring the output error of the ADC circuit, the degree of change (aging) of the ADC circuit or peripheral circuit can be detected. The ADC circuit state monitoring method and apparatus using the DAC circuit can reset the previously set correction algorithm to circuit function aging or environment change to continuously recalibrate the output value. In this way, the output accuracy of the ADC circuit can be maintained and lifetime extension possible. In addition, with the emphasis on the importance of self-test and diagnostics due to performance degradation over time of the ADC circuit, the DAC circuit and self-diagnosis and recalibration structure with few registers can be applied to many ADC circuits that require accurate output .

1 is a conceptual diagram showing an ADC circuit state monitoring apparatus using a DAC circuit according to an embodiment of the present invention.

Referring to FIG. 1, an ADC status monitoring apparatus using a DAC includes a first selector, an ADC circuit, a correction unit, a DAC circuit, a second selector, a counter, a first register, a second register, a difference calculator, can do.

The ADC circuit state monitoring apparatus using the DAC circuit is expressed by the term ADC circuit state monitoring apparatus.

The first selector may be configured to receive the input signal and to select the output signal output through the first selector according to the din_sel signal. Specifically, the din_sel signal may be a signal for determining an input signal (or an input voltage) input to the ADC circuit determined by the control unit. When the value of the din_sel signal is 1, the external input signal is selected and outputted through the first selector. When the value of the din_sel signal is 0, the signal transmitted from the DAC circuit for resetting the accuracy measurement or correction algorithm is 1 Can be output through the selection unit.

The ADC circuit can be implemented to convert the input analog signal into a digital signal. The ADC circuit can convert an analog signal input through the first selector. Specifically, an analog signal input through an ADC circuit may be an external input signal or a signal converted into a digital signal through an ADC circuit, a signal converted into a digital signal through an ADC circuit, or a signal converted back to an analog signal through a DAC circuit have.

The correction unit may be implemented to perform a correction operation based on the correction algorithm. The correction algorithm can correct the digital signal output through the ADC circuit based on the set correction parameter value. The accuracy of the correction can be increased by adjusting the set parameter values. If the correction accuracy is low, the correction parameters of the correction algorithm can be reset to increase the accuracy of the correction.

The difference calculator may determine that it is necessary to reset the correction algorithm of the correction unit on the basis of the result of calculating the difference between the values stored in the first register and the second register and in this case the correction unit performs the reset operation of the correction algorithm . The test_en signal can be input to the calibration unit to reset the calibration algorithm. The test_en signal may be a test notification signal to the corrector for resetting the calibration algorithm (resetting the parameters). The output value of the DAC circuit may be selected as the input of the ADC circuit for resetting the calibration algorithm of the calibration.

A counter execution signal for generating the actual input data together with the output of the ADC circuit necessary for resetting the correction algorithm of the correction unit may be generated for the cnt_en signal as a counter for the resetting procedure of the correction algorithm. Specifically, the test_en signal, which is a test notification signal for resetting the correction algorithm, is applied to the corrector so that the values of the counter can be sequentially generated. In this way, the correction algorithm (parameters of the algorithm) can be reset by simultaneously inputting the actual value of the counter signal and the counter signal output to the ADC circuit through the DAC circuit.

The DAC circuit can be implemented to convert the input analog signal into a digital signal. The DAC circuit may receive a signal input from the counter or a signal stored in the first register according to the selection of the second selection unit. The DAC circuit converts the input analog signal into a digital signal and can transmit it to the first selector.

The second selector may be implemented to transfer the signal input from the counter or the signal stored in the first register to the DAC circuit according to the selection. The second selector may be operated by receiving the mod_sel signal from the controller.

When the input mod_sel signal has a value of 1, the second selector may input the output value of the ADC circuit stored in the first register to the DAC circuit through the second selector for accuracy measurement. If the input mod_sel signal has a value of 0, the second selector may select a counter value for resetting the correction algorithm. That is, the output value or the counter value of the ADC circuit may be input to the DAC circuit according to the selection of the second selection unit.

The counter may be implemented to receive a cnt_en signal, which is a counter execution signal for generating actual input data of the correction algorithm, and to generate a counter signal.

The first register may be implemented to store information about the ADC circuit and the corrected digital signal generated by the correction unit. The information on the corrected digital signal stored in the first register is again generated as a digital signal corrected through the second selection unit, the DAC circuit, the first selection unit, the ADC circuit, and the correction unit, Signal.

The second register may be implemented to receive and store information about the corrected digital signal stored in the first register from the first register.

The difference calculator may be implemented to calculate the difference between the recalibrated digital signal information stored in the first register and the corrected digital signal information stored in the second register. The difference calculator may generate a rec_en signal when the difference between the corrected digital signal and the recalculated digital signal information is greater than or equal to the threshold range. The rec_en signal may be a signal for performing a reset of the correction algorithm of the control unit.

The control unit may be implemented to control operations of the first selection unit, the ADC circuit, the correction unit, the DAC circuit, the second selection unit, the counter, the first register second register, and the difference calculation unit. The difference calculation unit may transmit a reg_en signal to the control unit when it is determined that the correction algorithm needs to be reset based on the result values received from the first register and the second register, cnt_en, shi_en, din_sel, and mod_sel), and control procedures can be performed.

Table 1 below shows the signals output from the controller.

Signal name Explanation test_en The test notification signal to the calibration unit for resetting the calibration algorithm (resetting the parameters) cnt_en A counter execution signal for generating actual input data together with an output of the ADC circuit necessary for resetting the correction algorithm shi_en A register signal to store the output value to measure the accuracy of the ADC circuit, two application signals din_sel When the ADC input signal is selected, the external input voltage (or external input signal) is set to 1, and when it is 0, the DAC output is selected to measure the accuracy or reset the calibration algorithm. mod_sel 1, the ADC output value stored in Reg0 (first register) is used for accuracy measurement. When it is 0, the counter value for resetting the calibration algorithm is selected

Hereinafter, an embodiment of the present invention discloses an ADC circuit accuracy measurement procedure of a specific ADC circuit condition monitoring apparatus.

FIG. 2 is a flowchart illustrating an ADC accuracy measurement operation of an ADC circuit condition monitoring apparatus according to an embodiment of the present invention.

2, the operation of each component for measuring the ADC accuracy of the ADC status monitoring circuit is disclosed.

2, an external input signal (or an external input voltage) is selected as an input signal (or an input voltage) of the ADC circuit and input to the ADC state monitoring apparatus, and the inputted external voltage is corrected through the correction unit (step S200) .

The external input signal may be inputted through the first selector and corrected through the ADC circuit and the correction unit as described above. The control unit can instruct each component to set test_en: 0, cnt_en: 0, shi_en: 0, din_en: 1, and mod_sel: 1 as the control signal for the operation of step S200. With the above setting, the external input signal can be input through the first selector and corrected through the ADC circuit and the correction unit.

The corrected output of the ADC circuit is stored in the first register (step S210).

An external input signal through the correction unit through step S200 may be generated as a first corrected digital signal and the first corrected digital signal may be stored in a first register. The control unit can set the control signals for the operation of step S210 as test_en: 0, cnt_en: 0, shi_en: 1, din_en: 1, and mod_sel: 1 to command the operation of each constituent unit. With the above setting, the first corrected digital signal can be stored in the first register.

The first corrected digital signal stored in the first register is selected as the input signal of the ADC circuit via the DAC circuit (step S220).

The first corrected digital signal stored in the first register may be selected as the input signal of the ADC circuit via the DAC circuit. Specifically, the first corrected digital signal stored in the first register may again be generated as a second corrected digital signal via the second selector, the DAC circuit, the first selector, the ADC circuit, and the correction unit. The control unit can set the control signals for the operation of step S220 as test_en: 0, cnt_en: 0, shi_en: 0, din_en: 0, and mod_sel: 1 to command the operation of each constituent unit. With the above setting, the first corrected digital signal can be stored in the first register.

The first corrected digital signal stored in the first register is stored in the second register and the second corrected digital signal is stored again in the first register (step S230).

In the ADC state monitoring circuit according to the embodiment of the present invention, the output value (the first corrected digital signal) of the ADC circuit obtained through the correction and the output value (the first corrected digital signal) The output value (second corrected digital signal) output by inputting as the input value can be stored in a separate register and compared, and the error of the current correction can be grasped. If the calibration error is greater than the system allows, the internal counter and DAC circuitry can be used to re-calibrate the calibration algorithm parameters for the digital signal output through the ADC circuitry. The control unit may instruct each component to set test_en: 0, cnt_en: 0, shi_en: 1, din_en: 0, and mod_sel: 1 as the control signal for the operation of step S220. With the above setting, the first corrected digital signal stored in the first register may be stored in the second register, and the second corrected digital signal may be stored again in the first register.

The difference calculator outputs the comparison result between the first corrected digital signal stored in the second register and the second corrected digital signal stored in the first register to the controller (step S240).

The difference calculation unit may output the comparison result to the controller in response to the first corrected digital signal stored in the second register and the second corrected digital signal stored in the first register. If it is determined in the result of the difference calculator that a reset of the correction algorithm is necessary, the reset procedure of the correction algorithm can be started via the signal of reg_en and the signals of the controller can be controlled.

When the above ADC circuit condition monitoring method is used, it is possible to detect the change (aging) of the ADC circuit or peripheral circuit by measuring the output error of the ADC circuit. The previously set compensation algorithm can be reconfigured to adapt to circuit aging or environmental changes, and the output value can be continuously re-calibrated to maintain output accuracy and extend life. This method of monitoring the ADC circuit condition can be performed by using a DAC circuit and a self-diagnosis and re-calibration structure using a small number of resistors in a situation where the importance of self test and diagnosis due to decrease in the performance of the ADC circuit due to time is emphasized ADC circuit.

Table 2 below shows the setting of the control signals generated by the control unit for each step.

order test_en cnt_en shi_en din_sel mod_sel Explanation One 0 0 0 One One An external voltage is selected as an input to the ADC circuit, corrected and output 2 0 0 One One One The corrected output of the ADC circuit is stored in the first register (Reg0) 3 0 0 0 0 One The value stored in the first register Reg0 (value output by the ADC circuit itself) is selected as the input of the ADC circuit through the DAC circuit 4 0 0 One 0 One The value of the first register Reg0 stored first is shifted to the second register Reg1 and the output value of the ADC circuit due to the input of the value of the first register Reg0 is stored again in the first register Reg0 5 0 0 0 0 One The difference calculator compares the value of the first register Reg0 with the value of the second register Reg1 and outputs the result to the controller

Hereinafter, in the embodiment of the present invention, specific resetting of the correction algorithm of the ADC circuit is started.

3 is a conceptual diagram illustrating a procedure for resetting the correction algorithm of the ADC circuit according to the embodiment of the present invention.

In Fig. 3, a procedure for resetting the correction algorithm of the ADC circuit to be executed when it is determined that a reset is necessary after measuring the accuracy of the ADC circuit is disclosed.

Referring to FIG. 3, when the control unit receives an application signal of rec_en from the difference measurement unit, the second selection unit can be configured to receive a signal generated in the counter. Specifically, the mod_sel signal for controlling the operation of the second selector may be set to 0 so that the counter signal generated from the counter may be selected as the input of the DAC circuit. Also, the din_sel signal is set to 0 so that the output value of the DAC circuit is selected as the input of the ADC circuit.

Thereafter, the cnt_en signal is applied to the counter, the test_en signal is applied to the correcting unit, the values of the counter are sequentially generated, and the values of the actual counter signal and the counter signal output to the ADC circuit through the DAC circuit are simultaneously You can reset the calibration algorithm (parameters of the algorithm) by entering it. The correction unit can reset the correction algorithm (parameter of the algorithm) by comparing the counter signal inputted directly from the counter and the counter signal inputted through the DAC circuit and the ADC circuit.

4 is a flowchart illustrating a procedure for resetting the correction algorithm of the ADC circuit according to the embodiment of the present invention.

In Fig. 4, a procedure for resetting the correction algorithm of the ADC circuit to be executed when it is determined that resetting is necessary after the accuracy measurement of the ADC circuit is started.

Referring to FIG. 4, the control unit receives the rec_en signal from the difference measuring unit and sets the second selecting unit to receive the signal generated in the counter (step S400).

Specifically, the controller may set the mod_sel signal of the second selector to 0 so that a value generated from the counter is selected as an input to the DAC circuit. Also, the din_sel signal of the first selector is set to 0 so that the output value of the DAC circuit is selected as the input of the ADC circuit.

The control unit applies the cnt_en signal to the counter, and applies the test_en signal to the correcting unit (step S410).

The control unit applies the cnt_en signal to the counter, generates the counter values sequentially by applying the test_en signal to the correcting unit, and simultaneously outputs the actual counter signal value and the counter signal value output to the ADC circuit through the DAC circuit to the correcting unit You can reset the calibration algorithm (parameters of the algorithm) by entering it. The correction unit can reset the correction algorithm (parameter of the algorithm) by comparing the counter signal inputted directly from the counter and the counter signal inputted through the DAC circuit and the ADC circuit.

5 is a conceptual diagram illustrating a correction check procedure of a correction algorithm according to an embodiment of the present invention.

In FIG. 5, a reconfirmation procedure for confirming whether or not the parameters of the correction algorithm of the correction unit are properly reset is reversed.

Referring to FIG. 5, the difference calculation unit compares the values input to the first register and the second register through a procedure for receiving the input signal as shown in FIG. 2 to determine whether the parameters of the correction algorithm are correctly reset The following reaffirmation procedure can be performed.

Specifically, an external voltage is selected as the input voltage of the ADC circuit, and the external voltage is inputted to the ADC state monitoring circuit, and the inputted external voltage is corrected through the correction unit (step S500).

An external voltage input may be input through the first selector and corrected through the ADC circuit and the correction unit. The corrected output of the ADC circuit is stored in the first register (step S510).

An external voltage through the correction unit through step S200 may be generated as a first corrected digital signal and the first corrected digital signal may be stored in a first register.

The first corrected digital signal stored in the first register is selected as the ADC input via the DAC circuit (step S520).

The first corrected digital signal stored in the first register may again be generated as a second corrected digital signal via the second selector, the DAC circuit, the first selector, the ADC circuit, and the correction unit.

The first corrected digital signal stored in the first register is stored in the second register, and the second corrected digital signal is stored again in the first register (step S530).

In the ADC status monitoring circuit according to the embodiment of the present invention, the output value (first corrected digital signal) of the ADC circuit obtained through the correction and the output value obtained by inputting the output value again as the input value of the ADC circuit through the DAC circuit (Second corrected digital signal) is stored in a separate register, and the error of the current correction can be grasped. If the calibration error is greater than the system allows, the internal counter and DAC circuitry can be used to re-calibrate the parameters of the ADC's calibration algorithm.

The difference calculation unit outputs the first corrected digital signal stored in the second register and the second corrected digital signal stored in the first register to the controller (step S540).

The difference calculator may output the first corrected digital signal stored in the second register and the second corrected digital signal stored in the first register to the controller. The result of the difference calculator can be reconfirmed whether the parameters of the calibration algorithm of the calibration station are correctly reset.

The ADC status monitoring method using the DAC can be implemented in an application or in the form of program instructions that can be executed through various computer components and recorded in a computer-readable recording medium. The computer-readable recording medium may include program commands, data files, data structures, and the like, alone or in combination.

The program instructions recorded on the computer-readable recording medium may be ones that are specially designed and configured for the present invention and are known and available to those skilled in the art of computer software.

Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tape, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.

Examples of program instructions include machine language code such as those generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules for performing the processing according to the present invention, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

Claims (8)

A state monitoring method of an analog-digital converter (ADC) circuit using a digital-analog converter (DAC)
Controlling an ADC circuit state monitoring apparatus to convert an external input signal, which is an analog signal, into a digital signal through the ADC circuit, and then store the corrected digital signal through a correction unit;
Controlling the ADC circuit state monitoring apparatus to store the corrected digital signal in a second register;
Controlling the ADC circuit state monitoring apparatus to recalculate the corrected digital signal transmitted by the first register through the DAC circuit and the ADC circuit, and re-adjust the corrected digital signal through the correction unit to generate a recalibrated digital signal;
Controlling the ADC circuit state monitoring apparatus to store the recalibrated digital signal in the first register;
Wherein the ADC circuit condition monitoring device receives the recalibrated digital signal from the first register in a difference calculator and receives the corrected digital signal from the second register and outputs the corrected digital signal and the recalculated digital Controlling a difference value of the signal to be calculated;
Controlling the ADC circuit state monitoring apparatus to transmit a correction request signal to the control unit when the difference value is out of a set threshold range;
Controlling the ADC circuit state monitoring apparatus to generate a counter signal by operating a counter in the controller based on the correction request signal; And
The ADC circuit state monitoring apparatus compares the converted counter signal obtained by converting the counter signal and the counter signal through the DAC circuit and the ADC circuit in the correcting unit to reset the correction parameter of the correction algorithm Wherein the ADC circuit further comprises a DAC circuit. delete delete delete delete delete delete delete

Images