KR101835611B1 - Multi bit capacitorless dram using band offset technology and manufacturing method thereof - Google Patents

Abstract

A multi-bit capacitorless DRAM according to the present invention includes a substrate, a source and a drain formed on the substrate, a plurality of nanowire channels formed on the substrate, a gate insulating film formed on the plurality of nanowire channels, and a gate formed on the gate insulating film, Wherein at least two of the plurality of nanowire channels have different threshold voltages and each nanowire channel surrounds a silicon layer, a first epitaxial layer formed around the silicon layer, and a first epitaxial layer And a second epitaxial layer formed. Thus, a highly integrated multi-bit capacitorless DRAM capable of operating in multiple bits can be realized, and the accumulation performance of excess holes can be improved by using the energy band gap.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-bit capacitorless DRAM using band offsets and a method of manufacturing the same.

The present invention relates to a capacitorless DRAM, and more particularly, to a capacitorless DRAM capable of multi-bit implementation using a band offset and a method of manufacturing the same.

Dynamic random access memory (DRAM), which is one of semiconductor components that is essential for computing, consists of one transistor and one capacitor. However, since the size of the conventional DRAM must be reduced along with the size of the device, it has been considered difficult to secure a capacitor having a sufficiently large capacity. In addition, the capacitor forming process is a stumbling block due to the high step difference of the capacitor when the embedded chip is formed together with other devices. Accordingly, a capacitorless DRAM capable of storing data without a capacitor causing a complicated process is attracting attention. Since the capacitorless DRAM is not used, it has a great advantage in terms of integration and fabrication cost as compared with the conventional DRAM.

1A is a cross-sectional view schematically showing the operation principle of a conventional capacitorless DRAM, and FIG. 1B is an energy band diagram of a conventional capacitorless DRAM. The capacitorless DRAM is fabricated using a silicon-on-insulator (SOI) substrate or a general silicon substrate and a floating body device. When a predetermined voltage is applied to the gate 2 and the drain 4 of the transistor, an excess hole is generated in the channel on the drain 4 side by impact ionization. The generated excess holes are accumulated in the body 5 because there is no place to escape. The transistor having the accumulated holes differs from the threshold voltage and the current level in comparison with the case where there is no hole in the body 5, and distinguishes the '0' state from the '1' state by using the difference.

A state in which holes are accumulated in the body 5 is referred to as a '1' state, and a state in which holes are completely exhausted from the inside of the body 5 is referred to as a '0' state. That is, the conventional data of the capacitorless DRAM can exist only in two states of '0' state and '1' state. This means that only one bit of information can be stored. In other words, conventional capacitorless DRAMs can not operate with more than two bits due to the structural limitations of having only one body region (channel region).

The present invention is an improvement of a conventional capacitorless DRAM that operates only in a single bit. It is an object of the present invention to provide a capacitorless DRAM that has a higher integration density than a conventional capacitorless DRAM, A capacitorless DRAM and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a multi-bit capacitorless DRAM comprising: a substrate; A source and a drain formed on the substrate; A plurality of nanowire channels formed on the substrate; A gate insulating layer formed on the plurality of nanowire channels; And a gate formed on the gate insulator, wherein at least two of the plurality of nanowire channels have different threshold voltages, each nanowire channel comprising: a silicon layer; A first epitaxial layer formed to surround the silicon layer; And a second epitaxial layer formed surrounding the first epitaxial layer.

And, the first epitaxial layer may be an epitaxially grown Si _{1 - x} Ge _x layer.

Also, the first epitaxial layer may be an epitaxially grown Si _{1 - x} C _x layer.

And, the second epitaxial layer may be a silicon layer grown by epitaxy.

Further, the two or more nanowire channels may have different threshold voltages by changing at least one of the type, the depth, the concentration, and the angle of the doping ions.

The two or more nanowire channels may have different threshold voltages by changing the shape or area of the cross section.

In addition, the two or more nanowire channels may have different cross-sectional shapes or areas by etching at least one of different types of etch materials, concentration of etch materials, etch time, vacuum degree, and etch temperature.

A controller for controlling the operation of the multi-bit capacitorless DRAM; And a storage for storing a driving voltage for each of the plurality of nanowire channels based on a threshold voltage of the plurality of nanowire channels, wherein the controller is configured to apply a voltage to at least one of the gate and the drain By controlling the driving voltage, data of two or more bits can be programmed or erased.

According to another aspect of the present invention, there is provided a method of manufacturing a multi-bit capacitorless DRAM, including: (a) depositing a hard mask on a substrate; (b) etching at least a portion of the hard mask; (c) patterning the nanowire on the substrate through an anisotropic etch; (d) forming a protective film on the substrate; (e) forming a nanowire channel in the substrate through isotropic etching; (f) repeating the steps (c) and (e) to form a plurality of nanowire channels; (g) forming a source, a drain, and a gate, wherein step (f) comprises: treating the plurality of nanowire channels to each have a different threshold voltage, Thereby forming a first epitaxial layer and a second epitaxial layer.

The first epitaxial layer may be an epitaxially grown Si _1-x Ge _x layer surrounding the nanowire channel.

The first epitaxial layer may also be a Si _1-x C _x layer that surrounds the nanowire channel and is grown epitaxially.

And, the second epitaxial layer may be a silicon layer which surrounds the first epitaxial layer and is epitaxially grown.

In the step (f), each time the nanowire channel is formed, a dopant is injected by varying at least one of the kind, the depth, the concentration, and the implantation angle of the doping ions, Can be processed to have different threshold voltages.

In the step (f), each of the plurality of nanowire channels is formed by varying at least one of an etching material type, an etching material concentration, an etching time, a vacuum degree, and an etching temperature, Each can be processed to have a different threshold voltage.

The method may further include forming a gate insulating film on the substrate before the step (g).

According to another aspect of the present invention, there is provided a multi-bit capacitorless DRAM comprising: a substrate; A source and a drain formed on the substrate; A plurality of nanowire channels formed on the substrate; A gate insulating layer formed on the plurality of nanowire channels; And a gate formed on the gate insulating layer, wherein at least two of the plurality of nanowire channels have different threshold voltages, each nanowire channel comprising: a first silicon layer; And a second silicon layer surrounding the first silicon layer.

The first silicon layer may be a p-type to n-type doped silicon layer through an ion implantation process.

Also, the second silicon layer may be a p-type silicon layer not implanted with ions.

According to another aspect of the present invention, there is provided a method of manufacturing a multi-bit capacitorless DRAM, including: (a) depositing a hard mask on a substrate; (b) etching at least a portion of the hard mask; (c) patterning the nanowire on the substrate through an anisotropic etch; (d) forming a protective film on the substrate; (e) forming a nanowire channel in the substrate through isotropic etching; (f) repeating the steps (c) and (e) to form a plurality of nanowire channels; (g) forming a source, a drain, and a gate, wherein step (f) comprises: treating the plurality of nanowire channels to have different threshold voltages, respectively, An n-type silicon layer is formed on each of the channels.

The method may further include, before the step (g), forming a gate insulating film on the substrate.

According to the multi-bit capacitorless DRAM of the present invention having the above-described structure and the method of fabricating the same, it is possible to realize a highly integrated DRAM capable of operating in multiple bits, and to improve the accumulation performance of excess holes by using an energy band gap .

1A is a cross-sectional view schematically showing the operation principle of a conventional capacitorless DRAM.
1B is an energy band diagram of a conventional capacitorless DRAM.
2A is a perspective view of a multi-bit capacitorless DRAM according to the present invention.
2B is a cross-sectional view of the multi-bit capacitorless DRAM taken along line A-A 'in FIG. 2A.
FIG. 3 is a cross-sectional view of a multi-bit capacitorless DRAM taken along the line B-B 'in FIG. 2A, illustrating a phenomenon of ionization collision.
4 is a perspective view illustrating a main configuration of a multi-bit capacitorless DRAM according to the present invention.
FIGS. 5A through 5E are diagrams illustrating steps of forming a plurality of nanowires in a multi-bit capacitorless DRAM according to the present invention.
6A through 6C are diagrams illustrating steps of forming a plurality of nanowires in a multi-bit capacitorless DRAM according to the present invention.
7A and 7B are diagrams showing only a plurality of formed nanowire channels in a highlighted state.
8A and 8B are transmission electron micrographs of a nanowire channel having different shapes or areas in a multi-bit capacitorless DRAM according to the present invention.
9A and 9B are graphs showing the operating voltage range of a multi-bit capacitorless DRAM according to the present invention.
10A is a block diagram illustrating a configuration of an apparatus for measuring the operation of a multi-bit capacitorless DRAM according to the present invention.
FIGS. 10B and 10C are diagrams showing pulse voltages of input operating voltages in the respective operation regions. FIG.
11A is a graph showing a current value of a first operation region output by the pulse-type operation voltage shown in FIG. 10B.
And FIG. 11B is a graph showing a current value of the second operation region output by the pulse-type operation voltage shown in FIG. 10C.
12 is a flowchart illustrating a method of manufacturing a multi-bit capacitorless DRAM according to an embodiment of the present invention.
14A to 14C are views for explaining a multi-bit capacitorless DRAM according to the first embodiment of the present invention.
15A to 15C are views for explaining a multi-bit capacitorless DRAM according to a second embodiment of the present invention.
16A to 16C are a perspective view and a cross-sectional view of a multi-bit capacitorless DRAM according to the first and second embodiments of the present invention.
17A to 17C are views for explaining a multi-bit capacitorless DRAM according to a third embodiment of the present invention.

The following description of the invention refers to the accompanying drawings which illustrate, by way of example, specific embodiments that may be practiced. The described embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

The multi-bit capacitorless DRAM according to the present invention includes two or more channel regions. The two or more channel regions may be formed of nanowires, and two or more nanowire channels may be formed with different intrinsic threshold voltages by different ion implantation processes or by different etching processes. Since two or more nanowire channels have different threshold voltages, they have their own operating voltages that cause a collision ionization phenomenon.

FIG. 2A is a perspective view of a multi-bit capacitorless DRAM according to the present invention, and FIG. 2B is a cross-sectional view of a capacitorless DRAM taken along line A-A 'in FIG. 2A. Particularly, FIG. 2B further shows the structure of the drain 104 by cutting off a part of the drain 104 as well. As shown in FIGS. 2A and 2B, the multi-bit capacitorless DRAM according to the present invention has a plurality of nanowire channels unlike the prior art. Although only two nanowire channels 105a and 105b are shown in FIGS. 2A and 2B, this is only for the sake of simplicity, and a larger number of nanowire channels can be included.

The multi-bit capacitorless DRAM according to the present invention includes a substrate 100, a source 103 and a drain 104 formed on the substrate 100, a plurality of nanowire channels 105a and 105b formed on the substrate 100, A gate insulating film 101 formed on the plurality of nanowire channels 105a and 105b and a gate 102 formed on the gate insulating film 101. [ On the other hand, it may further include a shallow trench isolation oxide (106) for isolation between the respective structures. The STI oxide layer 106 is intended to reduce the leakage current between the source 103 and the drain 104 or the leakage current generated between different transistors. It may be formed of a silicon oxide film (SiO ₂ ) using vapor-phase chemical vapor deposition (CVD) or oxidation.

The substrate 100 may be a wafer of bulk wafers, insulating layer buried silicon wafers, insulating layer buried germanium wafers, insulating layer buried strained germanium wafers, insulating layer buried strained silicon wafers, III-V (Group 3 and 5 elements) And silicon germanium (SiGe) wafers, but is not limited thereto.

The gate insulating film 101 may be a silicon oxide film or a high-K film. More specifically, the gate insulating film 101 may be formed of silicon oxide, a nitride film, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, lanthanum oxide lanthanum oxide, hafnium silicon oxide, and the like. However, the present invention is not limited thereto.

The gate 102 may be made of metal or polysilicon. That is, the gate 102 is formed of a metal such as aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum Polycrystalline silicon, a high-concentration p-type doped polysilicon, a high-conductivity polymer or an organic material may be used. Also, the gate 102 may be made of a metal silicide film such as NiSi or a similar material, but is not limited to the above-mentioned materials.

Furthermore, the gate 102 may have a planar FET structure, a gate all around (GAA) FET structure, a FinFET structure, a double gate FET structure, a tri-gate FET structure, or an omega gate structure.

Before describing the material, the structure, and the formation method thereof with respect to the plurality of nanowire channels 105a and 105b, the driving principle of the multi-bit capacitorless DRAM according to the present invention will be described with reference to FIG.

FIG. 3 is a cross-sectional view of the capacitorless DRAM taken along the line B-B 'in FIG. 2A, illustrating the ionization collision phenomenon.

First, the first nanowire channel 105a located at the top has a unique threshold voltage. The driving voltage region can be determined according to the intrinsic threshold voltage of the first nanowire channel 105a. These are referred to as a first threshold voltage and a first driving voltage region, respectively.

When the voltage corresponding to the first driving voltage region is applied to the gate 102 and the drain 104 at this time the source 103 may be fixed at 0 V and the drain 104 is activated by impact ionization, Excess holes (portions marked with + in Fig. 3) are generated in the side channels. The generated excess holes are embedded in the body of the first nanowire channel 105a since there is no place to escape. When the excess hole is filled, the threshold voltage and the current level differ from each other in the absence of holes, and the difference between the '0' state and the '1' state can be distinguished.

On the other hand, the second nanowire channel 105b located at the bottom also has a unique threshold voltage. The driving voltage region can be determined according to the intrinsic threshold voltage of the second nanowire channel 105b. This is referred to as a second threshold voltage and a second driving voltage region, respectively.

At this time, the first threshold voltage and the second threshold voltage may be different from each other, whereby the first driving voltage region and the second driving voltage region are different. To make the first and second threshold voltages have different values, the following scheme can be used.

(1) In forming a plurality of nanowire channels, different threshold voltages may be obtained by varying at least one of the kind, depth, concentration, and angle of the doping ions.

(2) When forming a plurality of nanowire channels, different threshold voltages may be obtained by changing shapes or areas of respective cross sections. At this time, in each nanowire channel forming step, by changing at least one of the kind of the etching material, the concentration of the etching material, the etching time, the degree of vacuum and the etching temperature, the shape (triangle, circle, rhombus, Can be made different.

The second nanowire channel 105b can be formed by applying a voltage corresponding to the second driving voltage region to the gate 102 and the drain 104 (the source 103 can be fixed at 0 V) An excess hole (a portion marked with + in Fig. 3) is generated in the channel on the side of the drain 104 by impact ionization. The excess holes produced are accumulated in the body of the second nanowire channel 105b since there is no place to escape. When the excess hole is filled, the threshold voltage and the current level differ from each other in the absence of holes, and the difference between the '0' state and the '1' state can be distinguished.

Control of the intrinsic operating voltage of each of the first nanowire channel 105a and the second nanowire channel 105b results in a '0' state in each of the first nanowire channel 105a and the second nanowire channel 105b Quot; 1 " state, it is possible to store 2-bit information. By expanding this, it is possible to store 2 ⁿ bits of information when n nanowire channels are provided, thereby achieving integration of the memory.

Hereinafter, with reference to FIGS. 4, 5A to 5E, and 6A to 6C, a method of forming a plurality of nanowire channels in a multi-bit capacitorless DRAM according to the present invention will be described.

4 is a perspective view illustrating a main configuration of a multi-bit capacitorless DRAM according to the present invention. As shown in FIG. 4, the multi-bit capacitorless DRAM according to the present invention may have a plurality of nanowire channels 105a to 105i. The configurations of the source 103, the drain 104 and the gate 102 are described above, and will not be described here. Although a gate insulating film (not shown) surrounding the nanowire channels 105a to 105i is not clearly shown in Fig. 4, this is achieved by the steps of Figs. 5A to 5E and the steps of Figs. 6A to 6C, After the channels 105a to 105i are formed, a gate insulating film formation process (not shown) may be performed.

First, a substrate 100 is provided as shown in FIG. 5A. The provided substrate 100 may be a single crystal silicon substrate. In addition, the substrate 100 may be n-type or p-type depending on the type of material, and as described above, a bulk wafer, an insulating layer buried silicon wafer, an insulating layer buried germanium wafer, an insulating layer buried strained germanium wafer, An insulating layer buried strained silicon wafer, a wafer of a III-V (Group 3 and Group 5 element) material, and a silicon germanium (SiGe) wafer.

In the present embodiment, it is assumed that a p-type silicon substrate 100 is used for the sake of convenience.

When the substrate 100 is provided, the hard mask 10 is laminated, as shown in FIG. 5B. When the hard mask 10 is laminated, the photoresist 9 is again patterned.

Then, the hard mask 10 is etched using the stacked photoresist 9 as a protective film, and then the remaining photoresist 9 is removed. When this process is performed, the state shown in FIG. 5C is obtained. In a state where the photoresist film 9 is completely removed, an anisotropic etching is performed to form a region to be a nanowire channel, and then a passivation layer 20a is formed as shown in FIG. 5D . At this time, chlorine (Cl ₂ ) gas may be used for the anisotropic etching. The protective film 20a may be a polymer-based C _x F _y gas, and may be octafluorocyclobutane (C ₄ F ₈ ), which is one of them. However, the material used for the anisotropic etching or the material used for the protective film 20a is not limited to the above-mentioned materials.

As a next step, isotropic etching is used to form a separate nanowire channel with the substrate 100, as shown in Figure 5E. 5A through 5E, one first nanowire channel 105a is formed. At this time, sulfur hexafluoride (SF ₆ ) may be used for isotropic etching, but is not limited thereto.

FIGS. 6A through 6C illustrate a process of forming a plurality of nanowire channels by forming another nanowire channel below the nanowire channel 105a formed by the processes of FIGS. 5A through 5E.

As shown in FIG. 6A, after the first nanowire channel 105a is formed, anisotropic etching is again performed. At this time, chlorine (Cl ₂ ) gas may be used for the anisotropic etching, but the present invention is not limited thereto.

Next, as shown in FIG. 6B, a protective film 20b is formed using polymer-based octafluorocyclobutane (C ₄ F ₈ ), and then, as shown in FIG. 6C, sulfur hexafluoride (SF ₆ ) is used for the isotropic etching process. As a result, a second nanowire channel 105b spaced a predetermined distance is formed under the first nanowire channel 105a. When this process is performed nine times, a total of nine nanowire channels 105a to 105i are formed. However, this is merely an example, and a plurality of nanowire channels can be formed by various methods.

The following description will briefly describe a process in which a plurality of nanowire channels 105a to 105i are formed. After the plurality of nanowires 105a to 105i are formed, silicon oxide is deposited and chemical-mechanical polishing is performed.

Thereafter, a patterned photoresist film is formed to remove regions where the nanowire channels 105a to 105i are present, and the silicon oxide in the exposed regions is patterned by patterning the photoresist film to form trenches.

At this time, the step of removing the photoresist layer, controlling the size of the cross section of the nanowire channels 105a to 105i through sacrificial oxidation, and curing the damage caused in the etching process may be further performed have. Next, a gate insulating film is formed in the nanowire channel exposed through the trench formation, and a gate layer is formed on the gate insulating film.

The gate insulating film 101 may be a silicon oxide film or a high-K film. More specifically, the gate insulating film 101 may be formed of silicon oxide, a nitride film, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, lanthanum oxide (lanthanum oxide), hafnium silicon oxide (hafnium silicon oxide), and the like.

Meanwhile, the gate layer may be made of metal or polysilicon. That is, the gate layer is formed of a metal such as polysilicon, aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum (Pt) Materials, but are not limited thereto.

Then, the region to be removed from the silicon oxide and the gate layer is a region where the source and the drain are to be formed, and accordingly, appropriate patterning is performed in consideration of this. A gate insulating layer 101 is present in a region where a plurality of nanowire channels 105a to 105i are formed, silicon oxide is formed on both sides, and a gate layer is formed on the top surface.

Thereafter, a heavily doped n + type impurity ion (group 5 element of the periodic table) or a p + type impurity ion (group 3 element of the periodic table) is implanted to form the doped gate 102 and the nanohole channel 105a to 105i Source 103 and drain 104 are formed.

 At this time, instead of using a high-concentration n-type ion (group 5 of the periodic table) implanted into polysilicon as a gate layer, a metal may be used. And hydrogen annealing to relax the nanowire-shaped surface roughness.

The processes after forming the plurality of nanowires 105a to 105i are not limited to the above-mentioned processes, and can be variously performed by applying known semiconductor manufacturing processes and methods. Some of the processes after the plurality of nanowire formation 105a to 105i may be omitted or replaced with other necessary processes, and in some cases, the order may be changed or a plurality of processes may be performed simultaneously .

Figures 7A and 7B show only a plurality of nanowire channels 105a through 105i formed. The plurality of nanowire channels 105a to 105i may be spaced apart from each other by a predetermined distance.

Although FIG. 7B shows a plurality of nanowire channels 105a through 105i in the same shape and area, they can be made different in shape and area by various methods.

For example, in the etching step during the process of forming the plurality of nanowire channels 105a to 105i, if the kind or concentration of the etching material is changed, or the etching time, the degree of vacuum, or the etching temperature is changed, So that the channels 105a to 105i can be formed. A plurality of nanowire channels formed by the above method are shown in Figures 8A and 8B.

8A and 8B are transmission electron micrographs of nanowire channels 105a-105f with different shapes or areas in a multi-bit capacitorless DRAM according to the present invention. A total of six nanowire channels 105a to 105f are provided. As shown in FIG. 8A, each nanowire channel 105a-105f is different in shape or area from each other. For example, the first nanowire channel 105a is shaped differently from the other nanowire channels 105b through 105f. In addition, each of the nanowire channels 105a to 105f has a larger area as it goes down. Accordingly, the nanowire channels 105a to 105f have different threshold voltages, and operate in different driving voltage regions. Here, the driving voltage means a drain voltage causing ionization collision and a gate voltage (VG READ) used for reading.

Although Figures 8A and 8B illustrate nanowire channels having different shapes or areas, in other embodiments, the threshold voltages of each nanowire channel can be made different by different ways. In FIG. 8B, a gate insulating film 101 formed on the nanowire channel 105 is also shown.

For example, when forming a nanowire channel, the threshold voltage of each nanowire channel can be made different by varying at least one of the type, depth, concentration, and angle of ions doped in each nanowire channel.

9A and 9B are graphs showing the operating voltage range of a multi-bit capacitorless DRAM according to the present invention. Assuming two nanowire channels, four regions of the '00' state, the '01' state, the '10' state, and the '11' state can be used as memories.

9A and 9B, when the difference in magnitude of the current between the '00' state and the '01' state is used as a memory, this is referred to as a 'first operation region' Is used as a memory, this is referred to as a " second operation area ".

As shown in Figure 9a, the DRAM in order to '11' in the program (PROGRAM) the state of the initial state, so that the V _PROGRAM2 operating region corresponding to the drain voltage (V _D) is used, and the initial state of the DRAM 01 ', The drain voltage (V _D ) of V _PROGRAM1 is used. Accordingly, the number of bits usable in the multi-bit capacitorless DRAM according to the present invention is two, and when the number of bits is increased and the number of the nanowire channels is increased, the memory operates as a memory capable of storing a larger number of bits . 9B shows actual data representing the drain voltage region measured from the actually fabricated device. The drain voltage V _D for programming into the '11' state is about 5.5 V and the drain voltage for programming into the '01' state V _D ) becomes approximately 5V. However, it should be apparent to those skilled in the art that the drain voltage (V _D ) is not limited thereto, but may be varied depending on other factors such as the length, width, insulating film thickness, and the like of the nanowire channel.

A controller (not shown) for controlling the operation of the multi-bit capacitorless DRAM according to the present invention, and a storage unit (not shown) for storing a driving voltage for each of the plurality of nanowire channels. At this time, the driving voltage for each of the nanowire channels is based on the threshold voltage inherent to each channel as described above.

9A and 9B, a controller (not shown) controls the driving voltage applied to the gate 102 and the drain 104 to program two bits of data, erase. However, if a larger number of nanowire channels is provided, more than two bits of data may be programmed or erased.

FIG. 10A is a block diagram showing a configuration of an apparatus for measuring the operation of a multi-bit capacitorless DRAM according to the present invention. FIGS. 10B and 10C are diagrams showing, in each operation region (first operation region and second operation region) In pulse form.

The pulsed operation voltage input to the gate 102 and the drain 104 causes ionization collision phenomenon in each of the nanowire channels, thereby increasing the output current (source current I _S ).

The state where the output current I _S is relatively high is a program state, and the state where the output current is relatively low is an erase state.

The pulsed operating voltage input in the case of the first operating region is as shown in FIG. 10B. In order to program the multi-bit capacitorless DRAM according to the present invention into the '01' state, a drain voltage (V _D ) of V _PROGRAM1 of FIG. 9A is applied to the drain 104. _Through the drain voltage (V _D ) of V _PROGRAM1 , the capacitorless DRAM programmed to the '01' state is again set to '00' by the erase voltage V _ERASE1 .

On the other hand, the pulse-type operating voltage input in the case of the second operation region is as shown in FIG. In order to program the capacitor-less dynamic random access memory according to the present invention the "11" state, the drain 104 is applied to the drain voltage (V _D) of V _PROGRAM2 of Figure 9a. The capacitorless DRAM programmed to the '11' state through the drain voltage (V _D ) of V _PROGRAM2 is erased to the '10' state by the erase voltage V _ERASE2 .

FIG. 11A shows the current value of the first operating region output by the pulse-type operating voltage shown in FIG. 10B. That is, _when the drain voltage (V _D ) of the V _{PROGRAM 1} is input to the drain 104, an ionization collision phenomenon occurs in the corresponding nanowire channel, so that the source current I _S , which is the output current, Corresponds to the drain current I _D in the region ([Delta] I _SENSING1 ).

FIG. 11B shows the current value of the second operation region output by the pulse-type operation voltage shown in FIG. 10C. That is, when the drain voltage V _D of V _{PROGRAM 2} is input to the drain 104, an ionization collision phenomenon occurs in the corresponding nanowire channel, and thus the source current I _S , which is the output current, Corresponds to the drain current I _D in the region (ΔI _{SENSING 2} ).

As described above, according to the multi-bit capacitorless DRAM and the method of manufacturing the same according to the present invention, unlike a conventional memory that can store (process) only a single bit, it can operate with multiple bits of two or more bits, Not only improvement but also high integration can be achieved.

12 is a flowchart illustrating a method of manufacturing a multi-bit capacitorless DRAM according to the present invention.

First, a hard mask is deposited on the substrate (S200). Subsequently, at least a part of the hard mask is etched (S210), before the patterning process of the photoresist film can be performed.

Thereafter, an anisotropic etching is performed to form a region to be a nanowire channel, and then a passivation layer is formed (S220, S230).

At this time, chlorine (Cl ₂ ) gas may be used for the anisotropic etching. The protective film may be a polymer-based C _x F _y gas, and may be octafluorocyclobutane (C ₄ F ₈ ), which is one of them. However, the material used as a gas or a protective film used for anisotropic etching is not limited to the above-mentioned materials.

As a next step, an isotropic etching is used to form a nanowire channel separated from the substrate (S240). In this manner, a plurality of nanowire channels are formed (S230) while repeating the processes of nanowire patterning (S220), protective film formation (S230), and nanowire channel formation (S240) using anisotropic etching.

At this time, the plurality of nanowire channels to be formed may each have a different threshold voltage.

In one embodiment, each time the nanowire channel is formed, dopants may be implanted with different dopant species, depth, concentration, and / or implantation angle to provide different threshold voltages. In another embodiment, each time the nanowire channel is formed, it may be possible to have different threshold voltages by varying at least one of the type of etchant, the concentration of etchant material, the etch time, the degree of vacuum, and the etch temperature .

By using a band offset for a multi-bit capacitorless DRAM according to the present invention, a further improved performance can be realized. Hereinafter, a multi-bit capacitorless DRAM using a band offset will be described in order to improve performance.

FIG. 13A is a cross-sectional view of the multi-bit capacitorless DRAM described above, and FIG. 13B is an energy band diagram of a multi-bit capacitorless DRAM having the structure of FIG. 13A.

In the drawings after FIG. 13A, the same reference numerals are used for the same configurations as those of FIGS. 2A to 12. However, for the sake of brevity, reference number 200 is used. For example, the gate 102 of FIG. 3 is described as the gate 202 in FIG. 13A.

13A, since the plurality of nanowire channels consist of only the silicon layer Ll, the energy band diagram for each nanowire channel is as shown in FIG. 13B.

A multi-bit capacitorless DRAM according to the first embodiment, which further improves the accumulation performance of excess holes by using an energy band gap, is shown in Figs. 14A to 14C. The multi-bit capacitorless DRAM according to the second embodiment is shown in Figs. 15A to 15C, and the multi-bit capacitorless DRAM according to the third embodiment is shown in Figs. 17A to 17C. 16A to 16C are a perspective view and a cross-sectional view of a multi-bit capacitorless DRAM according to the first and second embodiments.

First, FIG. 14A shows a structure in which the accumulation performance of excess holes is improved by using epitaxially grown Si _{1 - x} Ge _x . FIG. 14B shows only one nanowire channel in the structure of FIG. 14A separately, and the energy band diagram at that time is shown in FIG. 14C.

In a multi-bit capacitorless DRAM having the structure of FIG. 14A, each of the plurality of nanowire channels includes a silicon layer (L1), a first epitaxial layer (L2) grown by epitaxy and a second epitaxial layer (L3) .

At this time, the first epitaxial layer L2 is an epitaxially grown Si _{1 - x} Ge _x layer and the second epitaxial layer L 3 is a epitaxially grown silicon layer.

More specifically, as shown in FIGS. 16A to 16C, a first epitaxial layer L2 is deposited in the form of surrounding the silicon layer L1, and a second epitaxial layer L3 is deposited in the first epitaxial layer And is deposited in the form of surrounding the special layer L2.

Si _{1 - x} Ge _x is an energy level of the valance gap as the mixture ratio _x of germanium is increased and the energy level of the conduction band is lowered so that the band gap E _g is narrow . The multi-bit capacitorless DRAM according to the embodiment of Fig. 14A utilizes this energy level characteristic.

That is, an epitaxial layer (Si _1-x Ge _x ) epitaxially grown between the silicon layer L 1 and the epitaxially grown silicon layer L ₃ is provided, and this epitaxial layer (Si _1-x Ge _x ) Is used as a quantum well for further improved performance.

The quantum well formed by the first epitaxial layer L2 using Si _{1 - x} Ge _x has a much deeper depth of the energy band diagram and a greater variation of the energy level compared to the case (FIG. 13A) . Therefore, the excess holes generated due to the ionization collision can be more effectively accumulated in the quantum well.

Moreover, Si _{1 - x} Ge _x claim multiple bits having a first epitaxial layer (L2) capacitor-less DRAM Using are, Si _{1 - x} Ge _x in the case 1 does not have an epitaxial layer (L2) (Figure 13a using It is possible to maintain the accumulation of excess holes for a longer period of time as compared with the case where the memory is used to improve the sensing window, the retention time, and the endurance, which are the main characteristics of the memory. do.

15A shows a structure in which the accumulation performance of excess holes is improved by using epitaxially grown Si _{1 - x} C _x . Fig. 15B shows only one nanowire channel in the structure of Fig. 15A separately, and the energy band diagram at that time is shown in Fig. 15C.

The plurality of nanowire channels of the multi-bit capacitorless DRAM having the structure of FIG. 15A includes a silicon layer L4, a first epitaxial layer L5 grown by epitaxy and a second epitaxial layer L6 grown by epitaxy . At this time, the first epitaxial layer L5 may be an epitaxially grown Si _{1 - x} C _x layer, and the second epitaxial layer L 6 may be a epitaxially grown silicon layer.

16A to 16C, the first epitaxial layer L5 is deposited in the form of surrounding the silicon layer L4, and the second epitaxial layer L6 is deposited in the first epitaxial layer L6, And is deposited in the form of surrounding the special layer L5.

Unlike the Si _{1 - x} Ge _x layer mentioned above, the Si _{1 - x} C _x layer has a characteristic that the band gap (E _g ) increases as the carbon mixture ratio (x) increases. Therefore, the excess holes generated through the ionization collision process can not be surpassed by the energy barrier of the first epitaxial layer (L 5) using Si _{1 - x} C _x, and can be accumulated more efficiently in the quantum well.

The quantum well formed by the first epitaxial layer L5 using Si _{1 - x} C _x has a much deeper depth of the energy band diagram and a greater variation of the energy level compared to the case (FIG. 13A) . Therefore, the excess holes generated due to the ionization collision can be more effectively accumulated in the quantum well.

In addition, since the capacitorless DRAM having the first epitaxial layer L5 using Si _{1 - x} C _x can maintain the accumulation of excess holes for a longer time than when it does not have (Fig. 13A) The sensing window, the retention time, and the endurance, which are the main characteristics of the memory, are improved.

Like a multi-bit capacitorless DRAM according to the embodiment of FIGS. 14A and 15A, a material such as Si _{1 - x} Ge _x having a narrow band gap (E _g ) or Si _{1 - x} C _x having a wide band gap By using an epitaxy process as a quantum well, it is possible to effectively accumulate excess holes in the nanowire channel to achieve improved performance.

17A shows a structure in which the accumulation performance of excess holes is improved by using ion implantation. FIG. 17B shows only one nanowire channel separately in the structure of FIG. 17A, and the energy band diagram at that time is shown in FIG. 17C. As in the embodiment of Figs. 17A to 17C, the above-described effects can be achieved through ion implantation.

The plurality of nanowire channels provided in the multi-bit capacitorless DRAM shown in FIG. 17A includes a first silicon layer L7 and a second silicon layer L8, wherein the first silicon layer L7 is formed by ion implantation Lt; RTI ID = 0.0 > n-type < / RTI > The formation of the first silicon layer L7 may be realized by implanting n-type ions such as phosphorus (P) or arsenic (As) to a specific depth with respect to the silicon layer L8 of the nanowire channel.

Since the valence band energy of the p-type is higher than the n-type band-band energy, it can be used as an energy barrier to efficiently accumulate excess holes. In other words, excess holes accumulate in the body of the nanowire channel without exceeding the energy barrier created by the n-type semiconductor.

In addition, since the capacitorless DRAM according to the embodiment of the present invention having the n-type silicon layer L7 can maintain the accumulation of excess holes for a longer time than when it has no structure (the structure of FIG. 13A) The sensing window, the retention time, and the endurance, which are the main characteristics of the memory, are improved.

In the meantime, a method of manufacturing a multi-bit capacitorless DRAM according to an embodiment of the present invention includes all the steps of FIG. 12, but the step S250 may further include an additional step.

That is, the step S250 of FIG. 12 may further include a step of forming a first epitaxial layer and a second epitaxial layer on each of the plurality of nanowire channels, such that the plurality of nanowire channels each have a different threshold voltage .

Wherein the first epitaxial layer is an epitaxially grown Si _1-x Ge _x layer or a Si _{1 - x} Ge _x layer surrounding the nanowire channel. Further, the second epitaxial layer is a silicon layer which surrounds the first epitaxial layer and is grown epitaxially.

In another embodiment, all of the steps of FIG. 12 are all included, but the step S250 may further include an additional step.

That is, in step S250 of FIG. 12, a plurality of nanowire channels are processed so as to have different threshold voltages, and a silicon layer of each of a plurality of nanowire channels is doped with n Type ions are implanted to form an n-type silicon layer.

Thus, the multi-bit capacitorless DRAMs according to the first to third embodiments of the present invention can be manufactured. Thus, the main characteristics of the memory, i.e., the sensing window, the retention time, the endurance and the like can be improved.

The features, structures, effects and the like described in the embodiments are included in one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Accordingly, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100 ‥‥‥‥‥‥‥‥‥‥ Substrate
101 ......... insulating film
102 ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ gate
103 ‥‥‥‥‥‥‥‥ Source
104 ‥‥‥‥‥‥‥‥‥ drain
105 ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ Nanowire channel
106 ......... STI oxide layer
L1, L4 ......... .. silicon layer
L3, L6 ......... The epitaxially grown silicon layer (second epitaxial layer)
L2 ... An epitaxially grown Si _{1 - x} Ge _x layer (first epitaxial layer)
L5 ... An epitaxially grown Si _{1 - x} C _x layer (first epitaxial layer)
L7 ... n type silicon layer < RTI ID = 0.0 >
L8 ......... p type silicon layer

Claims (20)

Board;
A source and a drain formed on the substrate;
A plurality of nanowire channels formed on the substrate;
A plurality of gate insulating films formed on the plurality of nanowire channels; And
And a gate formed on the plurality of gate insulating films,
Wherein at least two of the plurality of nanowire channels have different threshold voltages,
Each gate insulating film is formed surrounding each nanowire channel,
One nanowire channel formed surrounded by one gate insulating film,
A silicon layer;
A first epitaxial layer formed to surround the silicon layer; And
And a second epitaxial layer formed surrounding the first epitaxial layer,
Wherein the energy band gap of the first epitaxial layer is less than the energy band gap of each of the silicon layer and the second epitaxial layer. The method according to claim 1,
Wherein the first epitaxial layer is an epitaxially grown Si _{1 - x} Ge _x layer. The method according to claim 1,
Wherein the first epitaxial layer is an epitaxially grown Si _{1 - x} C _x layer. The method according to claim 1,
Wherein the second epitaxial layer is an epitaxially grown silicon layer. 5. The method according to any one of claims 1 to 4,
Wherein the two or more nanowire channels have different threshold voltages by differentiating at least one of the type, depth, concentration, and angle of the doping ions. 5. The method according to any one of claims 1 to 4,
Wherein the two or more nanowire channels have different threshold voltages by different shapes or areas of cross-section. 5. The method according to any one of claims 1 to 4,
Wherein the two or more nanowire channels are etched differently in at least one of the type of etchant material, the concentration of the etchant material, the etch time, the degree of vacuum, and the etch temperature, thereby having different cross-sectional shapes or areas. 5. The method according to any one of claims 1 to 4,
A controller for controlling operation of the multi-bit capacitorless DRAM; And
Further comprising a storage for storing a driving voltage for each of the plurality of nanowire channels based on a threshold voltage of the plurality of nanowire channels,
The controller controls a driving voltage applied to at least one of the gate and the drain to program or erase data of two or more bits. (a) depositing a hard mask on a substrate;
(b) etching at least a portion of the hard mask;
(c) patterning the nanowire on the substrate through an anisotropic etch;
(d) forming a protective film on the substrate;
(e) forming a nanowire channel in the substrate through isotropic etching;
(f) repeating the steps (c) to (e) to form a plurality of gate insulating films surrounding the plurality of nanowire channels and the plurality of nanowire channels, respectively;
(g) forming a source, a drain, and a gate,
The method of claim 1, wherein step (f) comprises: treating the plurality of nanowire channels to have different threshold voltages, respectively forming a silicon layer, a first epitaxial layer surrounding the silicon layer, and a second epitaxial layer in a single nanowire channel And a second epitaxial layer surrounding the first epitaxial layer, wherein an energy band gap of the first epitaxial layer is smaller than an energy band gap of each of the silicon layer and the second epitaxial layer, Method of manufacturing dyram. 10. The method of claim 9,
Wherein the first epitaxial layer surrounds the nanowire channel and is an epitaxially grown Si _1-x Ge _x layer. 10. The method of claim 9,
Wherein the first epitaxial layer surrounds the nanowire channel and is an epitaxially grown Si _1-x C _x layer. 10. The method of claim 9,
Wherein the second epitaxial layer is a silicon layer that surrounds the first epitaxial layer and is epitaxially grown. 10. The method of claim 9,
The step (f)
Each time a nanowire channel is formed, a dopant is implanted at least one of a type, a depth, a concentration, and an implant angle of doping ions, so that each of the plurality of nanowire channels is processed to have a different threshold voltage A method of manufacturing a capacitorless DRAM. 10. The method of claim 9,
The step (f)
Treating each of the plurality of nanowire channels to have a different threshold voltage by varying at least one of the type of etchant material, the concentration of the etchant material, the etch time, the degree of vacuum, and the etch temperature each time the respective nanowire channel is formed A method of manufacturing a multi - bit capacitorless DRAM. delete delete delete delete delete delete

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