KR101889295B1 - Liquid crystal display device - Google Patents

Abstract

There is provided a liquid crystal display device capable of preventing power consumption and heat generation of the data driver. A liquid crystal display device includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines, a timing controller for generating a plurality of control signals for driving the liquid crystal panel, a plurality of gate drivers for driving the plurality of gate lines, A plurality of data drivers for driving the plurality of data lines and a plurality of data lines electrically connected to the plurality of data lines and for charging the data voltages according to the source output enable signals provided by the timing controller, .

Description

[0001] Liquid crystal display device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of preventing power consumption and heat generation of a data driver.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used today because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

The liquid crystal display device includes a plurality of gate lines and data lines crossing each other and defining pixels, and a switching transistor formed in the pixel. Scan pulses are sequentially applied to the plurality of gate lines every horizontal period to turn on the switching transistors located in the pixels of the corresponding row line. In synchronism with this, the data driver outputs the data voltages to the plurality of data lines, and the data voltages thus output are applied to the corresponding pixels.

In this way, the data driver outputs the data voltage every horizontal period, and the output data voltage changes in polarity or voltage value, i.e., gradation, every horizontal period. That is, a variation amount of the output data voltage is generated. When the fluctuation amount of the data voltage increases, the power consumption of the data driver increases.

Therefore, in order to reduce the fluctuation amount of the data voltage, a charge share driving method has been proposed. The charge share drive scheme is to average all the data line voltages before output by shorting all the data lines to each other between neighboring horizontal periods. That is, the data line is pre-charged with the charge sharing voltage before the next output. As a result, the variation amount of the output data voltage can be reduced.

However, the charge-share driving method is very effective in reducing the power consumption in the dot-inversion method, but it increases the power consumption in the column-inversion method. When charge-share driving is not performed, a DC voltage is output to the data line for one frame. However, when charge-share driving is performed, a voltage variation occurs in the data line during a high level period of the source output enable signal, There is a problem in that power is consumed in the data driver as much as it occurs.

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device capable of preventing power consumption and heat generation of a data driver.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above objects, a liquid crystal display according to a first embodiment of the present invention includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines arranged to have a plurality of unit pixels, A data driver for driving the plurality of data lines, a positive polarity buffer and a negative polarity buffer, which are provided in the data driver and are connected to corresponding data lines through respective first switches, And a capacitor for charging the data voltage of the corresponding data line or discharging the charged data voltage according to the source output enable signal.

The capacitor is mounted on a printed circuit board, and the capacitance of the capacitor corresponds to a load of the liquid crystal panel.

The capacitor shares a data voltage applied to the corresponding data line during a period in which the source output enable signal is at a high level, and simultaneously charges the data voltage or discharges the charged data voltage.

The data lines are divided into a plurality of groups having two or more same polarities, and the data voltages are shared by the groups.

The capacitor includes a first capacitor charging and discharging a positive data voltage and a second capacitor charging and discharging a negative data voltage.

The first and second capacitors are two or more.

The liquid crystal display according to the second embodiment of the present invention includes a liquid crystal panel including a plurality of gate lines and a plurality of data lines arranged to have a plurality of unit pixels and including an edge region and a remaining region excluding the edge region, A timing controller for generating a plurality of control signals for driving the liquid crystal panel, a gate driver for driving the plurality of gate lines, and a plurality of data lines for driving the plurality of data lines, Wherein the edge region comprises a first switch disposed between the plurality of output buffers and the plurality of data lines and a second switch disposed between the plurality of output buffers and each of the plurality of data lines, A plurality of second and third switches connected to the data lines of the second and third switches, And a first and a second wiring to which a positive polarity and a negative polarity precharge voltage are applied, respectively, and an area other than the edge area is disposed between the plurality of output buffers and the plurality of data lines Third and fourth wirings to which the positive and negative precharge voltages are applied respectively and first and second capacitors respectively connected to the ends of the third and fourth wirings .

The first to fourth switches are turned on or off according to a control signal provided by the timing control unit.

When the first and second switches are turned on, the data lines connected to the first and second switches share a precharge voltage of positive polarity with the data voltage.

When the first and third switches are turned on, the data lines connected to the first and third switches share a negative precharge voltage with the data voltage.

The fourth switch is electrically connected to one of the output buffer, the first wiring, and the second wiring in accordance with a control signal provided from the timing control unit.

The first and second capacitors are mounted on a printed circuit board, respectively.

Wherein the edge region includes a plurality of fifth switches disposed between the plurality of output buffers and the plurality of data lines and a plurality of fifth switches disposed between the plurality of output buffers and the plurality of data lines, Group.

A plurality of first group switches electrically connecting the plurality of groups are disposed between the plurality of groups.

The one group includes six or twelve output buffers, and the one group includes six or twelve data lines.

The fifth switch is electrically connected to one of the output buffer, the fifth wiring, and the sixth wiring according to a control signal provided from the timing control unit.

Wherein the edge region includes a sixth switch disposed between the plurality of output buffers and the plurality of data lines, and a plurality of seventh and eighth switches, respectively, disposed between the adjacent data lines and connected to the plurality of data lines, And seventh and eighth wirings connected to the seventh and eighth switches and to which positive and negative precharge voltages are applied, respectively.

A plurality of second group switches electrically connecting the plurality of groups are disposed between the plurality of groups.

The one group includes six or twelve output buffers, and the one group includes six or twelve data lines.

The sixth to eighth switches are turned or off according to a control signal provided by the timing control unit.

When the sixth and seventh switches are turned on, the data lines connected to the sixth and seventh switches share a precharge voltage of positive polarity with the data voltage.

When the sixth and eighth switches are turned on, the data lines connected to the sixth and eighth switches share a negative precharge voltage with the data voltage.

As described above, the liquid crystal display device according to the present invention provides the effect of preventing power consumption and heat generation of the data driver.

1 is a view showing a liquid crystal display device according to a first embodiment of the present invention.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a charge-
Fig. 3 is a view showing the inside of the buffer of Fig. 2; Fig.
FIG. 4 is a waveform diagram showing charges stored in a capacitor according to the source output enable signal according to the first embodiment of the present invention; FIG.
5 is a view showing a liquid crystal panel according to a second embodiment of the present invention.
6A is a view showing switches for charge-share arranged in the edge region of the liquid crystal panel according to the second embodiment of the present invention.
FIG. 6B is a view illustrating charge-sharing switches disposed in the remaining region except for the edge region of the liquid crystal panel according to the second embodiment of the present invention; FIG.
FIG. 7A is a view showing switches for charge-share arranged in an edge region of a liquid crystal panel according to a third embodiment of the present invention; FIG.
FIG. 7B is a view showing charge-sharing switches disposed in the remaining regions except the edge region of the liquid crystal panel according to the third embodiment of the present invention; FIG.
8A is a view showing switches for charge-share arranged in an edge region of a liquid crystal panel according to a fourth embodiment of the present invention.
FIG. 8B is a view showing switches for charge-share arranged in a remaining region except an edge region of the liquid crystal panel according to the fourth embodiment of the present invention; FIG.

Hereinafter, preferred embodiments of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to a first embodiment of the present invention.

1, the liquid crystal panel 110 includes a plurality of unit pixels arranged in a matrix and connected to a plurality of display signal lines GL and DL as equivalent circuits. do.

Here, the display signal lines GL and DL include a plurality of gate lines GL for transferring gate signals and data lines DL for transferring data signals. The gate lines GL extend in the row direction, are substantially parallel to each other, the data lines DL extend in the column direction, and are substantially parallel to each other.

Each unit pixel includes a switching element TFT connected to the display signal lines GL and DL and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The storage capacitor Cst may be omitted as needed.

The control terminal and the providing terminal of the three-terminal device are connected to the gate line GL and the data line DL, respectively, and the output terminals thereof are connected to the liquid crystal capacitors Clc and Clc. And is connected to the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, that is, a pixel electrode of the TFT substrate and a common electrode of the color filter substrate, and the liquid crystal layer between the two electrodes functions as a dielectric. The pixel electrode is connected to the switching element (TFT), and the common electrode is formed on the front surface of the color filter substrate and receives the common voltage Vcom. Here, the common electrode may be provided on the TFT substrate, and both electrodes are made linear or rod-shaped.

The storage capacitor Cst is formed by superimposing a separate signal line (not shown) and a pixel electrode provided on the TFT substrate, and a predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed by superimposing the pixel electrode on the immediately preceding gate line via the insulator.

On the other hand, in order to realize color display, each unit pixel must be able to display a color, which can be achieved by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. Here, the color filter may be formed in the corresponding region of the color filter substrate, or may be formed on or below the pixel electrode of the TFT substrate.

A polarizer (not shown) for polarizing light is attached to the outer surface of at least one of the TFT substrate and the color filter substrate of the liquid crystal panel 110.

The gate driver 120 is connected to the gate line GL of the liquid crystal panel 110 and applies a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff from the outside to the gate line GL do.

The data driver 130 is connected to a data line DL of the liquid crystal panel 110 and generates a plurality of gradation voltages based on a plurality of gamma voltages supplied from a gamma voltage generator Voltage is applied to the unit pixel as a data signal and is usually composed of a plurality of integrated circuits.

The timing controller 140 generates control signals CONT1 and CONT2 for controlling operations of the gate driver 120 and the data driver 130 and supplies the corresponding control signals to the gate driver 120 and the data driver 130 ).

Although not shown in the drawing, a plurality of driving voltage generating units are generated. For example, the driving voltage generating section generates the gate-on voltage Von, the gate-off voltage Voff, and the common voltage Vcom.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 140 receives a control signal, for example, a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync, for controlling the RGB video signals R, G, and B and the display thereof from an external graphics controller (not shown) ), A main clock (MCLK), a data enable signal (DE), and the like. The timing controller 140 generates a gate control signal CONT1 and a data control signal CONT2 based on the provided control signals and outputs the video signals R, G, and B to the liquid crystal panel 110 in accordance with the operation conditions of the liquid crystal panel 110 A gate control signal CONT1 is supplied to the gate driver 120 and a data driver 130 is supplied with the data control signal CONT2 and the processed video signal DAT.

Here, the gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (gate-on voltage section), a gate clock signal CPV for controlling the output timing of the gate- An output enable signal OE for limiting the width of the pulse, and the like. Among them, the output enable signal OE and the gate clock signal CPV are provided to the drive voltage generating section.

The data control signal CONT2 includes a horizontal synchronization start signal STH for instructing the start of the provision of the image data DAT and a load signal LOAD for applying the corresponding data voltage to the data line DL, (RVS) and a data clock signal (HCLK) for inverting the polarity of the data voltage (hereinafter, referred to as 'the polarity of the data voltage with respect to the common voltage').

The data driver 130 sequentially receives the video data DAT corresponding to the unit pixel of one row according to the data control signal CONT2 from the timing controller 140 and outputs the video data DAT corresponding to each video data DAT The image data DAT is converted into the corresponding data voltage.

The gate driver 120 applies a gate-on voltage Von to the gate line GL in accordance with the gate control signal CONT1 from the timing controller 140 to apply a switching element TFT connected to the gate line GL Turn on.

The gate-on voltage Von is applied to one gate line GL so that one row of the switching elements TFT connected thereto is turned on (this period is referred to as '1H' or '1 horizontal period' And the data driver 130 supplies the respective data voltages to the corresponding data lines DL. The data driver 130 supplies the data voltages to the corresponding data lines DL. The data voltage supplied to the data line DL is applied to the corresponding unit pixel through the turned-on switching element (TFT).

The liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode and the common electrode, and the polarization of the light passing through the liquid crystal layer changes accordingly. This change in polarization is caused by a change in transmittance of light by a polarizer (not shown) attached to the TFT substrate and the color filter substrate.

In this manner, the gate-on voltage Von is sequentially applied to all the gate lines GL during one frame to apply a data voltage to all the unit pixels. When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 130 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to the polarity of the previous frame reversal'). In this case, the polarity of the data voltage flowing through one data line may be changed ('line inversion') or the polarity of the data voltage applied to one pixel line may be different according to the characteristics of the inversion signal RVS within one frame 'Dot inversion').

FIG. 2 is a view showing a charge-sharing unit included in the data driver according to the first embodiment of the present invention. FIG. 3 is a view showing the inside of the buffer of FIG. 2, FIG. 8 is a waveform diagram showing charges stored in a capacitor in accordance with an output enable signal; FIG.

2, the data driver 130 including the charge sharing unit according to the first embodiment of the present invention includes a plurality of buffers BF11 to BF1 (K) and a plurality of data lines DL1 to DL (N) A plurality of first switches SW11 to SW1 (L) connected between the plurality of data lines DL1 to DLm and a plurality of second switches SW21 to SW4 connected between the plurality of data lines DL1 to DLm, SW2 (M).

Each of the plurality of buffers BF11 to BF1 (K) supplies the analog data voltage to the corresponding data lines DL1 to DL (N) via the corresponding first switches SW11 to SW1 (L) do. The first switches SW11 to SW1 (L) and the second switches SW21 to SW2 (M) are connected to the data output enable signal DOE, which is one of the data control signals supplied from the timing controller 140 Are complementarily turned on. When the data output enable signal DOE is high (or low), the first switches SW11 to SW1 (L) are turned on while the second switches SW21 to SW2 M) is turned off. On the other hand, when the data output enable signal DOE is low (or high), the first switches SW11 to SW1 (L) are turned on and off while the second switches SW21 to SW2 (M) Is turned off.

For example, when the scan signal is supplied to the first gate line GL1 and the thin film transistors TFT connected to the gate line GL1 are turned on and the data output enable signal DOE is high , Each of the plurality of buffers BF11 to BF1 (K) supplies a pixel data voltage opposite to the adjacent buffers via the corresponding first switches SW11 to SW1 (L) to the corresponding data lines DL. Then, each of the thin film transistors TFT connected to the first gate line GL1 causes the data voltage on the corresponding data line DL to be charged in the corresponding liquid crystal cell Clc and the corresponding storage capacitor Cst .

Conversely, when the data output enable signal DOE is low, the second switches SW21 to SW2 (M) are turned on instead of the first switches SW11 to SW2 (L) to turn on the plurality of data lines DL1 To DL (N) are connected to each other. Then, the charging and discharging of the voltage between the data lines DL1 to DL (N) charged with the data voltages having the opposite polarity to the adjacent data lines are simultaneously performed. For example, when the odd data lines DL1, DL3, ..., DL (N-1) are charged with a negative data voltage and the even data lines DL2, DL4, ..., DL (N) The odd-numbered data lines DL1, DL3, ..., DL (N-1) are connected to the even-numbered data lines DL2, DL4, ..., DL (N) While the even data lines DL2, DL4, ..., DL (N) charge the charged positive polarity data voltage to the adjacent odd data lines DL1, DL3, ..., DL (N-1) As a result, charge sharing occurs in which all of the data lines DL1 to DL (N) are precharged to the intermediate level voltage between the positive data voltage and the negative data voltage. The charge-share driving method in which the effect of pre-charge is exhibited decreases the power consumption of the data driver and the liquid crystal display device including the data driver It is advantageous.

In the first embodiment of the present invention, the data lines share the data voltages. However, the data lines having two or more same polarities may be divided into groups to share the data voltages.

However, the charge-share driving method is a factor that increases the power consumption in the column-inversion method. Therefore, in order to solve this problem, the first embodiment of the present invention provides a method for reducing power consumption Capacitors are each mounted on a printed circuit board and electrically connected to the data lines to which the positive polarity and negative polarity data voltages are respectively applied.

Referring to FIG. 3, one buffer BF11 includes a positive polarity buffer BF11_1 for outputting a positive polarity data voltage and a negative polarity buffer BF11_2 for outputting a negative polarity data voltage. The positive and negative buffers BF11_1 and BF11_2 are connected to the first switches SW11_1 and SW11_2 respectively and the first switches SW11_1 and SW1_2 are connected to the second switches SW21_1 and SW21_2 And the second switches SW21_1 and SW21_2 are connected to the power consumption reduction capacitors C11 and C12, respectively. At this time, the capacitors for power consumption reduction (C11, C12) are capacitors charged with the data voltages of the positive polarity and the negative polarity, respectively. The capacitors C11 and C12 for reducing the power consumption are mounted on the printed circuit board although the capacitors C11 and C12 for reducing the power consumption are not actually shown in the drawings, load can be set.

4, according to the first embodiment of the present invention, in order to reduce the power consumption of the charge-share driving method, according to the source output enable signal SOE provided from the timing control unit 140, , The data voltage applied to the corresponding data line is shared, and the voltage for charging the capacitors C11 and C12 for power consumption reduction or the charged voltage is discharged.

Here, the data voltage applied to the corresponding data line is shared during the period (a) during which the source output enable signal SOE is at the high level, and the capacitors C11 and C12 for power consumption reduction are connected to the capacitors C11, C12) is consumed. That is, while sharing the data voltage applied to the corresponding data line during the period in which the source output enable signal SOE is at the high level, the voltage charged in the capacitors C11 and C12 for power consumption reduction is supplied to the corresponding data lines DL1, DL3, ..., DL (N-1).

During the period (a) during which the next source output enable signal SOE is at the high level, the data voltage applied to the corresponding data line is shared and the capacitors C11 and C12 for power consumption reduction are charged to a constant voltage level.

Subsequently, the data voltage applied to the corresponding data line is shared during the period (a) during which the next source output enable signal SOE is at the high level, and the voltage charged in the capacitors for power consumption reduction (C11, C12) And precharges the lines DL1, DL3, ..., DL (N-1). These operations are repeatedly performed.

As described above, in the first embodiment of the present invention, the capacitors for reducing the power consumption corresponding to the positive and negative data voltages are mounted on the printed circuit board, respectively, and the capacitors are connected to the positive and negative data voltages The data voltage applied to the corresponding data line is shared during the period in which the source output enable signal SOE is at the high level and the voltage charged in the power consumption reducing capacitors C11 and C12 is Discharging or charging the voltage may be repeatedly performed to reduce the heat generation and power consumption of the data driver by about 50%.

In the first embodiment of the present invention, the two power consumption reduction capacitors corresponding to the positive and negative data voltages have been described. However, the power consumption reduction capacitor may be mounted on two or more printed circuit boards.

However, according to the first embodiment of the present invention, when displaying a pattern in which the difference in data voltages is large on the left and right sides of the center of the liquid crystal panel, for example, white on the left side and black on the right side, There is a problem that a block-dim phenomenon may occur in the central part of the liquid crystal panel depending on the amount of electric charge stored in the capacitor for reducing power consumption mounted on the liquid crystal panel.

Therefore, in order to solve the above problems, in the second embodiment of the present invention, the charge share switches disposed in the edge region of the liquid crystal panel and the charge share switches disposed in the remaining regions except for the edge region are arranged differently .

FIG. 5 is a view showing a liquid crystal panel according to a second embodiment of the present invention, FIG. 6A is a view showing switches for charge-share arranged in an edge region of a liquid crystal panel according to a second embodiment of the present invention, Are diagrams illustrating charge-sharing switches disposed in other regions except the edge region of the liquid crystal panel according to the second embodiment of the present invention.

5 to 6A, a plurality of buffers BF31 to BF3 (J) and a plurality of data lines DL1 (J) are provided in an edge region b of the liquid crystal panel 210 according to the second exemplary embodiment of the present invention. A plurality of first switches SW41 to SW4 (K) connected in correspondence with each of the plurality of data lines DL1 to DL (N), and a plurality of second switches The first and second wirings PL11 and PL12 to which positive and negative precharge voltages VHC and VLC are applied respectively to the first and second switches SW51 to SW5 (L) and the third switches SW61 to SW6 (M) PL12). The second switches SW51 to SW5 (L) are electrically connected to the first wiring line PL11 to which the positive precharge voltage VHC is applied, and the third switches SW61 to SW6 (M) Is electrically connected to a second wiring line PL12 to which a precharge voltage VLC of negative polarity is applied.

The edge region b of the liquid crystal panel 210 is connected to the precharge voltages VHC and VLC of the positive and negative polarities applied from the outside for each of the adjacent data lines DL1 to DL And the third switches SW51 to SW5 (L), SW61 to SW6 (M) are disposed so that adjacent data lines are more affected by the pre-charge voltage, and the power consumption of the external printed circuit board The influence due to the voltage charged in the capacitor is received differently from the area other than the edge area of the liquid crystal panel.

At this time, control signals for turning on / off the second and third switches SW51 to SW5 (L), SW61 to SW6 (M) are provided from the timing control section 140, The third switches SW51 to SW5 (L), SW61 to SW6 (M) are turned on or off to share the data voltage applied to the corresponding data line during the period in which the source output enable signal SOE is at the high level A voltage of a capacitor for reducing power consumption mounted on an external printed circuit board, that is, a precharge voltage, is charged or discharged to the corresponding data line.

6B, a plurality of buffers BF31_C to BF3 (J) _C) and a plurality of data lines (BF31_C to BF3 (J) _C) are provided in the remaining region b except for the edge region of the liquid crystal panel 210 according to the second exemplary embodiment of the present invention. A plurality of switches SW41_C to SW4 (K) _C and a plurality of precharge voltages VHC and VLC of a positive polarity and a negative polarity are connected to each other in correspondence with each of the transistors DL1_C to DL (N) And the first and second wirings PL11_C and PL12_C. At this time, the ends of the first and second wirings PL11_C and PL12_C are connected to the power-saving capacitors C31_C and C32_C mounted on the external printed circuit board.

Unlike the edge region b of the liquid crystal panel 210, the remaining region c except for the edge region of the liquid crystal panel 210 has switches disposed between the first and second lines PL11_C and PL12_C And the plurality of switches SW41_C to SW4 (K) _C are connected to the plurality of buffers BF31_C to BF3_J (C)), the first wiring line PL11_C And is electrically connected to any one of the second wirings PL11_C and PL21_C, thereby applying the data voltage to the corresponding data lines DL1_C to DL (N) _C.

As described above, in the second embodiment of the present invention, the charge sharing switches disposed in the remaining region (c) except the edge region (b) of the liquid crystal panel (210) and the edge region of the liquid crystal panel are arranged differently, It is possible to minimize the occurrence of the block dim phenomenon in the central portion.

However, in the second embodiment of the present invention, a plurality of third switches SW51 to SW5 (L) and fourth switches SW51 to SW5 (M) are provided between the plurality of data lines DL1 to DLm There is a problem that the resistance is greatly increased.

In order to solve the above problems, in the third embodiment of the present invention, a plurality of buffers and a plurality of data lines arranged in the edge region (b) of the liquid crystal panel 210 are divided into a plurality of groups, So that the influence of the voltage charged in the capacitor for power consumption mounted on the external printed circuit board is received differently from the area other than the edge area of the liquid crystal panel.

FIG. 7A is a view showing charge-sharing switches disposed in the edge region of the liquid crystal panel according to the third embodiment of the present invention. FIG. Lt; RTI ID = 0.0 > switches < / RTI >

Referring to FIG. 7A, the edge region b of the frame structure panel 210 according to the third embodiment of the present invention applies a data voltage to a corresponding data line for each of a plurality of groups G11 to G1 (N). At this time, the first group G11 includes a plurality of switches SW411 to SW416 respectively connected between the plurality of buffers BF311 to BF316 and the plurality of data lines DL11 to DL16, And first and second wirings PL21 and PL22 to which polarity and negative polarity precharge voltages VHC and VLC are respectively applied.

At this time, a group switch G_SW11 is arranged between each of the groups G11 to G1 (N), and each of the groups G11 to G1 (N) includes six or twelve buffers or data lines It can be divided into one group.

Here, the control signals for turning on / off the plurality of switches SW411 to SW416 and the plurality of group switches G_SW11 are provided from the timing control unit 140 and are controlled by the control signals to control the switches SW411 to SW416 And the plurality of group switches G_SW11 are turned on or off and the plurality of switches SW411 to SW416 are connected to the plurality of buffers BF311 to BF316), the first wiring line PL11_C or the second wiring lines PL11_C and PL21_C , And accordingly applies a data voltage to the corresponding data lines DL11 to DL16.

Referring to FIG. 7B, a region c excluding the edge region of the liquid crystal panel 210 according to the third exemplary embodiment of the present invention includes a plurality of buffers BF311_C to BF311 (J) _C) A plurality of switches SW411_C to SW41 (K) _C connected in correspondence with each other between the data lines DL11_C to DL1 (N) _C and a plurality of precharge voltages VHC and VLC of positive and negative polarities, And the first and second wirings PL21_C and PL22_C. At this time, the ends of the first and second wirings PL21_C and PL22_C are connected to capacitors C311_C and C312_C for power consumption reduction mounted on an external printed circuit board.

Here, the control signals for turning on / off the plurality of switches SW411_C to SW41 (K) _C are provided from the timing control unit 140, and are controlled by the control signals SW411_C to SW41 (K) _C The plurality of switches SW411_C to SW41 (K) _C are turned on or off from among the plurality of buffers BF311_C to BF311 (J) _C), the first wiring line PL21_C or the second wiring line PL22_C And is thereby electrically connected to any one of them, thereby applying the data voltage to the corresponding data lines DL11_C to DL1 (N) _C.

FIG. 8A is a view showing charge-sharing switches disposed in an edge region of a liquid crystal panel according to a fourth embodiment of the present invention, FIG. 8B is a cross-sectional view of a remaining region except for the edge region of the liquid crystal panel according to the fourth embodiment of the present invention, Lt; RTI ID = 0.0 > switches < / RTI > Here, the fourth embodiment of the present invention is a combination of the second embodiment of the present invention and the third embodiment.

Referring to FIG. 8A, the edge region b of the liquid crystal panel 210 according to the fourth embodiment of the present invention applies a data voltage to a corresponding data line for each of a plurality of groups G21 to G2 (N). At this time, the first group G11 includes a plurality of switches SW611 to SW616 connected correspondingly between the plurality of buffers BF511 to BF516 and the plurality of data lines DL21 to DL2 (N) And a plurality of second switches SW711 to SW716 and third switches SW811 to SW816 connected between the plurality of data lines DL21 to DL2 (N) And first and second wirings PL31 and PL32 to which charge voltages VHC and VLC are respectively applied.

At this time, the second switches SW711 to SW716 are electrically connected to the first wiring line PL31 to which the positive precharge voltage VHC is applied, and the third switches SW811 to SW816 are electrically connected to the negative And is electrically connected to the second wiring line PL12 to which the charge voltage VLC is applied. A group switch G_SW21 is disposed between each of the groups G21 to G2 (M), and each of the groups G21 to G2 (M) includes six or twelve buffers or data lines It can be divided into one group.

Here, the control signals for turning on / off the second switches SW711 to SW716 and the third switches SW811 to SW816 are provided from the timing control unit 140, and the control signals are supplied to the second and third switches (SW711 to SW716, SW811 to SW816) are turned on or off to share a data voltage applied to the corresponding data line during a period in which the source output enable signal (SOE) is at a high level, and are mounted on an external printed circuit board The voltage of the capacitor for reducing power consumption, that is, the precharge voltage, is charged or discharged to the corresponding data line.

8B, a plurality of buffers BF511_C to BF51 (J) _C) and a plurality of data lines (BF511_C to BF51 (J) _C) are provided in the remaining region b except for the edge region of the liquid crystal panel 210 according to the fourth exemplary embodiment of the present invention. A plurality of switches SW611_C to SW61 (K) _C connected in correspondence with each of the first to fourth transistors DL21_C to DL2 (N) _C and a plurality of precharge voltages VHC and VLC of positive and negative polarities, And the first and second wirings PL31_C and PL32_C. At this time, the ends of the first and second wirings PL31_C and PL32_C are connected to capacitors C411_C and C412_C, which are mounted on an external printed circuit board, for power consumption reduction.

Here, the control signals for turning on / off the plurality of switches SW41_C to SW4 (K) _C are provided from the timing control unit 140 and are supplied to the plurality of switches SW41_C to SW4 (K) _C The plurality of switches SW41_C to SW4 (K) _C are turned on or off from among the plurality of buffers BF511_C to BF51 (J) _C), the first wiring line PL31_C or the second wiring line P32_C And applies a data voltage to the corresponding data lines DL21_C to DL2 (N) _C accordingly.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the claims and the appended claims.

110, 210: liquid crystal panel 120: gate driver
130: Data driver 140: Timing controller

Claims (25)

A liquid crystal panel having a plurality of unit pixels arranged with a plurality of gate lines and a plurality of data lines;
A gate driver for driving the plurality of gate lines;
A data driver for driving the plurality of data lines;
A positive polarity buffer and a negative polarity buffer which are provided in the data driver and are connected to the same data line through respective first switches; And
And a second switch connected between the first switch and the corresponding data line through the second switch, respectively, and charging the data voltage of the corresponding data line according to a source output enable signal, And each capacitor discharging the charged data voltage. The method according to claim 1,
Wherein the capacitor is mounted on a printed circuit board. The method according to claim 1,
If the source output enable signal is at a high (or low) level, the first switch is turned on while the second switch is turned off. If the source output enable signal is at a low (or high) level, 1 switch is turned off while the second switch is turned on. The method according to claim 1,
Wherein the capacitor shares a data voltage applied to the corresponding data line during a period in which the source output enable signal is at a high level and simultaneously charges the data voltage or discharges the charged data voltage. 5. The method of claim 4,
Wherein the plurality of data lines are divided into a plurality of groups having two or more same polarities, and the data voltages are shared by the groups. The method according to claim 1,
The capacitor
A first capacitor charging and discharging the positive polarity data voltage; And
And a second capacitor for charging and discharging the negative data voltage. The method according to claim 6,
Wherein the first capacitor and the second capacitor are two or more. A liquid crystal panel including a plurality of gate lines and a plurality of data lines arranged to have a plurality of unit pixels and including an edge region and a remaining region excluding the edge region;
A timing controller for generating a plurality of control signals for driving the liquid crystal panel;
A gate driver for driving the plurality of gate lines; And
And a data driver including a plurality of output buffers driving the plurality of data lines and outputting a plurality of data voltages to the plurality of data lines,
Wherein the edge region comprises a first switch disposed between the plurality of output buffers and the plurality of data lines and a plurality of first and second switches disposed between adjacent ones of the data lines and connected to the plurality of data lines, And first and second wirings connected to the second and third switches and to which positive and negative precharge voltages are respectively applied,
A plurality of fourth switches disposed between the plurality of output buffers and the plurality of data lines, and a third and fourth wirings to which positive and negative precharge voltages are applied, respectively, And first and second capacitors connected to the ends of the third and fourth wirings, respectively. 9. The method of claim 8,
And the first to fourth switches are turned or turned off according to a control signal provided by the timing control unit. 9. The method of claim 8,
Wherein data lines connected to the first and second switches share a precharge voltage of positive polarity with a data voltage when the first and second switches are turned on. 9. The method of claim 8,
Wherein data lines connected to the first and third switches share a pre-charge voltage of a negative polarity with a data voltage when the first and third switches are turned on. 9. The method of claim 8,
And the fourth switch is electrically connected to any one of the output buffer, the first wiring, and the second wiring in accordance with a control signal provided from the timing control unit. 9. The method of claim 8,
Wherein the first and second capacitors are mounted on a printed circuit board, respectively. 9. The method of claim 8,
Wherein the edge region includes a plurality of fifth switches disposed between the plurality of output buffers and the plurality of data lines and a plurality of second switches including fifth and sixth wirings to which positive and negative precharge voltages are respectively applied The liquid crystal display device comprising: 15. The method of claim 14,
And a plurality of first group switches electrically connecting the plurality of groups are disposed between the plurality of groups. 16. The method of claim 15,
Wherein any one of the plurality of groups includes six or twelve output buffers. 16. The method of claim 15,
Wherein one of the plurality of groups includes six or twelve data lines. 15. The method of claim 14,
And the fifth switch is electrically connected to any one of the output buffer, the fifth wiring, and the sixth wiring in accordance with a control signal provided from the timing control unit. 9. The method of claim 8,
The edge region may include a sixth switch disposed between the plurality of output buffers and the plurality of data lines, and a plurality of seventh and eighth data lines disposed respectively between the adjacent data lines and connected to the plurality of data lines. And a seventh and an eighth wiring connected to the seventh and eighth switches and to which a precharge voltage having a positive polarity and a negative polarity is applied, respectively. 20. The method of claim 19,
And a plurality of second group switches electrically connecting the plurality of groups are disposed between the plurality of groups. 21. The method of claim 20,
Wherein any one of the plurality of groups includes six or twelve output buffers. 21. The method of claim 20,
Wherein one of the plurality of groups includes six or twelve data lines. 20. The method of claim 19,
And the sixth to eighth switches are turned or turned off according to a control signal provided by the timing control unit. 24. The method of claim 23,
Wherein data lines connected to the sixth and seventh switches share a precharge voltage of positive polarity with a data voltage when the sixth and seventh switches are turned on. 24. The method of claim 23,
And the data lines connected to the sixth and eighth switches share a negative precharge voltage with a data voltage when the sixth and eighth switches are turned on.

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