KR101920871B1 - Fingerprint cognition sensorand driving method thereof - Google Patents

Abstract

The present invention relates to a fingerprint recognition sensor capable of preventing an RC delay time of a coupling pulse from increasing even when the area of a fingerprint sensor increases, and a driving method thereof. The fingerprint recognition sensor comprises: a sensor panel including a plurality of sensor pixels, a plurality of gate lines, a plurality of coupling lines, and a plurality of data lines; and a gate driving circuit supplying a plurality of gate signals to the plurality of gate lines and supplying a plurality of coupling pulses synchronized with the plurality of gate signals to the plurality of coupling lines.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a fingerprint recognition sensor,

The present disclosure relates to a capacitive fingerprint sensor and a driving method thereof.

In a capacitive fingerprint sensor using a conventional coupling pulse, the coupling pulse is supplied through one electrode to the entire fingerprint sensor. Then, as the area of the fingerprint sensor increases, the parasitic capacitance of the electrode to which the coupling pulse is transmitted increases.

An increase in the parasitic capacitance increases the RC delay time of the coupling pulse, which can affect the image quality of the fingerprint sensor.

A fingerprint recognition sensor and a driving method thereof that can prevent an RC delay time of a coupling pulse from being increased even if an area of a fingerprint sensor is increased.

According to an aspect of the present invention, there is provided a fingerprint recognition sensor including a sensor panel including a plurality of sensor pixels, a plurality of gate lines, a plurality of coupling lines, and a plurality of data lines, And a gate driving circuit for supplying a plurality of coupling pulses synchronized with the plurality of gate signals to the plurality of coupling lines.

The gate drive circuit includes the plurality of stages, and each of the plurality of stages can generate a corresponding gate signal and a corresponding coupling pulse to supply to a corresponding gate line and a corresponding coupling line.

Wherein each of the plurality of stages receives a corresponding two clock signals and a gate signal of an immediately preceding stage and changes a voltage of a first node according to an on level of a gate signal of the immediately preceding stage, A shift register circuit for receiving the continuous coupling pulse and outputting the continuous coupling pulse as the corresponding coupling pulse in accordance with the voltage of the first node; Circuit.

Wherein the shift register circuit includes at least one transistor including a gate connected to the first node, one terminal for inputting the first clock signal, and the other terminal connected to an output terminal of the shift register circuit, And a capacitor connected between the node and the output terminal of the shift register circuit. The coupling pulse output circuit may include a transistor including a gate connected to the first node, one end to which the continuous coupling pulse is input, and the other end to be connected to the output end of the coupling pulse output circuit have.

Wherein the shift register circuit changes the voltage of the second node in accordance with a second clock signal of the two corresponding clock signals to maintain the corresponding gate signal at an off level, The corresponding coupling pulse can be kept off-level according to the voltage of the node.

Wherein the shift register circuit includes at least one shift register circuit including a gate connected to the second node, one end connected to a voltage end to which the voltage of the off level is input, and the other end connected to the output end of the shift register circuit And a capacitor connected between the second node and the voltage terminal, wherein the coupling pulse output circuit includes: a gate connected to the second node; a first terminal for receiving the voltage of the off level; And a transistor including the other end connected to the output terminal of the coupling pulse output circuit.

In the fingerprint recognition sensor, the shift register circuit and the coupling pulse output circuit may constitute a corresponding stage. Alternatively, in the fingerprint recognition sensor, the shift register circuit and the coupling pulse output circuit may separately constitute a corresponding stage.

Wherein each of the plurality of gate lines is formed in a first direction and arranged in a second direction crossing the first direction, each of the plurality of coupling lines is formed in the first direction and arranged in the second direction Each of the plurality of data lines may be formed in the second direction and may be arranged in the first direction.

In each of the plurality of sensor pixels, a capacitance is coupled according to a coupling pulse transmitted through a corresponding coupling line, and a data signal is transmitted to a corresponding data line according to a gate signal transmitted through a corresponding gate line .

According to another aspect of the present invention, there is provided a method of driving a fingerprint recognition sensor including sequentially supplying a plurality of gate signals to a plurality of sensor pixels, sequentially supplying a plurality of coupling pulses to the plurality of sensor pixels, Wherein capacitive coupling is coupled in each of the sensor pixels of the plurality of sensor pixels in response to a corresponding coupling pulse and a step in which the data signals of the plurality of sensor pixels are transmitted to the plurality of data lines in synchronization with each of the plurality of gate signals can do. Each of the plurality of coupling pulses may be synchronized to a corresponding gate signal.

Wherein the first clock signal of at least two clock signals is generated as an (i + 1) -th gate signal according to an on level of an i-th gate signal among the plurality of gate signals, The signal is changed to an on level, and a continuous coupling pulse is generated as an (i + 1) -th coupling pulse according to the on level of the first clock signal.

The driving method of the fingerprint recognition sensor may further include the step of keeping the (i + 1) -th gate signal and the (i + 1) -th coupling pulse at an off level according to a second clock signal of the at least two clock signals .

The method of driving the fingerprint recognition sensor according to claim 1, wherein in each of the plurality of sensor pixels, capacitances are coupled in accordance with a coupling pulse transmitted through a corresponding coupling line, and in each of the plurality of sensor pixels, And transmitting the data signal to the corresponding data line according to the gate signal transmitted through the line.

Provided is a fingerprint recognition sensor and a driving method thereof that can prevent an RC delay time of a coupling pulse from increasing even if the area of a fingerprint sensor increases.

1 is a view showing a fingerprint sensor according to an embodiment.
2 shows a sensor pixel according to an embodiment.
3 is a diagram showing a gate driving circuit according to the embodiment.
4 is a diagram showing an example of a stage according to the embodiment.
5 is a waveform diagram showing a continuous coupling pulse, a start pulse, a plurality of gate signals, and a plurality of coupling pulses according to the embodiment.
6 is a waveform diagram of clock signals according to an embodiment.
7 is a diagram illustrating a stage according to another embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

1 is a view showing a fingerprint recognition sensor according to an embodiment.

1, the fingerprint recognition sensor 1 includes a sensor panel 10, a gate drive circuit 20, a timing control circuit 30, and a sensor signal lead-out circuit 40. As shown in Fig.

The sensor panel 10 includes a plurality of gate lines S0-Sn, a plurality of data lines D1-Dm, a plurality of coupling pulse lines CL1-CLn, and a plurality of sensor pixels TPX.

The plurality of gate lines S0 to Sn extend in a first direction (X direction in FIG. 1) and are arranged in a second direction (Y direction in FIG. 1) that intersects the first direction. The gate signal corresponding to each of the plurality of sensor pixel rows is transmitted through the plurality of gate lines S0-Sn.

In Figure 1, two gate lines correspond to each sensor pixel row. This is because each sensor pixel operates according to the corresponding two gate signals. However, the present invention is not limited to this, and the number of gate lines connected to one sensor pixel row may vary depending on the gate signal required for the operation of the sensor pixel.

The plurality of coupling lines CL1 to CLn extend in the first direction and are arranged in the second direction intersecting the first direction. A coupling pulse corresponding to each of a plurality of sensor pixel rows is transmitted through the plurality of coupling lines CL1 to CLn. The coupling pulse is a pulse signal for continuously performing the coupling in the sensor pixel in the capacitive method.

The plurality of data lines D1 to Dm extend in the second direction and are arranged along the first direction. The data signals of the plurality of sensor pixels are transmitted to the sensor signal lead-out circuit 40 through the plurality of data lines D1-Dm.

Each of the plurality of sensor pixels TPX is connected to two corresponding gate lines, data lines, and coupling lines. Each of the plurality of sensor pixels TPX is reset in synchronization with the gate signal transmitted through one of the two corresponding gate lines. In each of the plurality of sensor pixels TPX, capacitance is coupled in accordance with a coupling pulse transmitted through a corresponding coupling line, and the gate signal synchronized with the gate signal transmitted through the other of the two gate lines The data signal can be transmitted to the data line.

The gate driving circuit 20 generates a plurality of gate signals and a plurality of coupling pulses, and transfers the gate signals to a plurality of gate lines S0-Sn and a plurality of coupling lines CL1-CLn. The gate drive circuit 20 can generate a plurality of coupling pulses synchronized with each of the plurality of gate signals and transmit them to the plurality of coupling lines CL1 to CLn. Then, the parasitic capacitance of the coupling pulse is reduced compared to the conventional case where the coupling pulse is supplied through one electrode, and the RC delay time of the coupling pulse can be improved. The gate drive circuit 20 will be described in detail with reference to FIG. 3 to FIG.

The sensor signal lead-out circuit 40 receives a plurality of data signals transmitted through the plurality of data lines D1 to Dm and generates information on the fingerprints sensed according to the plurality of data signals.

The timing control circuit 30 can generate the control signals CONT1 and CONT2 necessary for controlling the operations of the gate drive circuit 20 and the sensor signal lead-out circuit 40. [

The gate driving circuit 20 can generate a plurality of coupling pulses synchronized with the plurality of gate signals and the plurality of gate signals in accordance with the control signal CONT1. The sensor signal lead-out circuit 40 receives a plurality of data signals in synchronization with the timing at which the plurality of data signals are transmitted through the plurality of data lines D1 to Dm in accordance with the control signal CONT2, It is possible to perform the signal processing necessary for generating the information on the information.

2 shows a sensor pixel according to an embodiment.

2, a sensor pixel TPX located in the i-th row and the j-th column is shown. The sensor pixel TPX at another position also includes the same configuration as shown in Fig. 2, and each configuration may be connected as shown in Fig.

The sensor pixel TPX includes five transistors P1 to P5, a coupling capacitor Ccp, a storage capacitor Cst, and a fingerprint sensing electrode 51.

The fingerprint sensing electrode 51 is an electrode for sensing a corresponding position in the fingerprint to be recognized. A fingerprint capacitor (Cfp) is formed on the fingerprint sensing electrode (51) when the fingerprint is contacted.

The gate of the transistor P1 is connected to the node N1, and both ends of the transistor P1 are connected between the node N3 and the node N4. The gate of the transistor P2 is connected to the node N3, and both ends thereof are connected between the node N4 and the source electrode of the transistor P4. The gate of the transistor P3 is connected to the gate line Si-1, and both ends of the transistor P3 are connected between the node N3 and the node N2. The gate of the transistor P4 is connected to the gate line Si and the drain of the transistor P4 is connected to the data line Dj. The gate of the transistor P5 is connected to the gate line Si-1 and is connected between the node N1 and the node N2. The fingerprint sensing electrode 51 is connected to the node N1 and the coupling capacitor Ccp is connected between the node N1 and the node N2 and the storage capacitor Cst is connected to the node N3, (N4). The voltage VSS is supplied to the node N4.

The transistor P5 and the transistor P3 are turned on and the gate of the transistor P1 and the gate of the transistor P2 are reset by the high level of the coupling pulse. The coupling pulse according to the embodiment is synchronized with the on-time (for example, the falling edge timing) of the corresponding gate signal (for example, the gate signal transmitted through the gate line Sn) (For example, low level). The on level period of the coupling pulse may be shorter than the on level period of the corresponding gate signal.

The node N1 is coupled to the coupling line CLi through a coupling capacitor Ccp. When the coupling pulse falls to the on level, the voltage reduction of the coupling pulse is divided by the two capacitors Cfp and Ccp, and the voltage of the node N1 decreases.

The storage capacitor Cst can maintain the gate voltage of the transistor P2 determined according to the current flowing through the transistor P1 or the voltage output through the transistor P1.

The transistor P4 is turned on by a corresponding gate signal (e.g., a gate signal transmitted through the gate line Si). Then, the current flowing through the transistor P2 is transmitted to the sensor signal lead-out circuit 40 through the data line Dj as a data signal.

A sensor pixel having a structure other than the sensor pixel shown in Fig. 2 can be applied to the embodiment. The sensor pixel is implemented as a p-channel type transistor and the ON level is described as a low level, but the invention is not limited thereto. The sensor pixel may be implemented as an n-channel type transistor, in which case the on level is at a high level and the gate signal and coupling signal may be inversed with those described above.

3 is a diagram showing a gate driving circuit according to the embodiment.

3, the gate drive circuit 20 includes a plurality of stages 20_0 through 20_n, and the current stage receives as input one carry signal which is one of the outputs of the previous stage, And outputs a ring pulse. Each stage receives the corresponding two clock signals (two of CLK1 to CLK4), and a high level voltage (VDD) can be supplied to the voltage terminal VH to be biased.

Four clock signals CLK1 to CLK4 are supplied through the four clock wirings 211 to 214 and a voltage VDD is supplied through the wirings 215 and a continuous coupling pulse CSP) is supplied.

In Fig. 3, the stage 20_0 supplies a gate signal S [0] to the gate line SO. In the sensor pixel shown in Fig. 2, a gate signal corresponding to a sensor pixel row in which a sensor pixel is located and a gate signal (hereinafter referred to as a immediately preceding gate signal) corresponding to the immediately preceding sensor pixel row are required. The stage 20_0 does not generate the coupling pulse in the configuration for generating the immediately preceding gate signal S [0] required for the first sensor pixel row.

In FIG. 3, a separate stage 20_0 is provided to generate the gate signal S [0], but the invention is not limited thereto. The carry signal of the last stage 20_n may be used as a gate signal immediately before the first sensor pixel row.

The stage 20_0 includes an input terminal IN, two clock terminals CK1 and CK2, an output terminal OUT, an output terminal COUT and a voltage terminal VH. The start pulse SP is input through the input terminal IN and the clock signal CLK2 and the clock signal CLK4 are input to the two clock stages CK1 and CK2 respectively. The output terminal OUT is connected to the gate line S0, and the gate signal S [0] is output. The output terminal COUT is connected to the input terminal IN2 of the stage 20_1, and the carry signal of the stage 20_0 is outputted.

Each of the plurality of stages 20_1 to 20_n includes two input stages IN1 and IN2, two clock stages CK1 and CK2, three output stages OUT, COUT and CPOUT, and a voltage stage VH. The carry signal of the immediately preceding stage is input to the input terminal IN1, and the continuous coupling pulse CSP is input to the input terminal IN2. Corresponding clock signals are supplied to each of the clock stage CK1 and the clock stage CK2, and there may be a predetermined phase difference between the two clock signals. In the embodiment, the phase difference between the two clock signals may be two horizontal periods. The output terminal OUT is connected to the corresponding gate line, the output terminal COUT is connected to the input terminal IN2 of the next stage, and the output terminal COUT is connected to the corresponding coupling line. A gate signal is outputted through the output terminal OUT, a carry signal is outputted through the output terminal COUT, and a coupling pulse is outputted through the output terminal CPOUT.

For example, in the stage 20_1, the carry signal CA [0] is input to the input terminal IN1, the clock signal CK1 and the clock terminal CK2 are supplied with the clock signal CLK3 and the clock signal CLK1 Is supplied. The output terminal OUT is connected to the gate line S1 and the output terminal COUT is connected to the input terminal IN1 of the stage 20_2 and the gate signal S [ And the carry signal CA [1] is output through the output terminal COUT. The output terminal CPOUT is connected to the coupling line CL1, and the coupling pulse CP [1] is output through the output terminal CPOUT.

In the stage 20_2, the carry signal CA [1] is input to the input terminal IN1 and the clock signal CLK4 and the clock signal CLK2 are supplied to the clock stage CK1 and the clock stage CK2, respectively . The output terminal OUT is connected to the gate line S2 and the output terminal COUT is connected to the input terminal IN1 of the stage 20_3 and the gate signal S [2] And the carry signal CA [2] is output through the output terminal COUT. The output terminal CPOUT is connected to the coupling line CL2, and the coupling pulse CP [2] is output through the output terminal CPOUT.

In the stage 20_3, the carry signal CA [2] is input to the input terminal IN1, and the clock signal CLK1 and the clock signal CLK3 are supplied to the clock terminal CK1 and the clock terminal CK2, respectively . The output terminal OUT is connected to the gate line S3, the output terminal COUT is connected to the input terminal IN1 of the next stage (not shown), and the gate signal S [3] , And the carry signal CA [3] is output through the output terminal COUT. The output terminal CPOUT is connected to the coupling line CL3, and the coupling pulse CP [3] is output through the output terminal CPOUT.

In the stage 20_n-1, the carry signal CA [n-2] of the immediately preceding stage is input to the input terminal IN1 and the clock signal CK1 and the clock terminal CK2 are supplied with the clock signal CLK1 and clock The signal CLK3 is supplied. The output terminal OUT is connected to the gate line Sn-1 and the output terminal COUT is connected to the input terminal IN1 of the stage 20_n and the gate signal S [n-1 ], And the carry signal CA [n-1] is output through the output terminal COUT. The output terminal CPOUT is connected to the coupling line CLn-1, and the coupling pulse CP [n-1] is output through the output terminal CPOUT.

In the stage 20_n, the carry signal CA [n-1] is input to the input terminal IN1 and the clock signal CLK2 and the clock signal CLK4 are supplied to the clock terminal CK1 and the clock terminal CK2, respectively . The output terminal OUT is connected to the gate line Sn and the gate signal S [n] is outputted through the output terminal OUT. The output terminal CPOUT is connected to the coupling line CLn, and the coupling pulse CP [n] is output through the output terminal CPOUT.

4 is a diagram showing an example of a stage according to the embodiment.

The stage 20_i shown in FIG. 4 includes a shift register circuit 21 and a coupling pulse output circuit 22.

The shift register circuit 21 includes seven transistors P11 to P17 and two capacitors C1 and C2.

The drain of the transistor P11 is connected to the input terminal IN1 and the drain of the transistor P12 is connected to the clock terminal CK1. The gate of the transistor P11 is connected to the drain of the transistor P11, Respectively. The source of the transistor P11 is connected to the node P and the source of the transistor P12 is connected to the node Q. [

The gate of the transistor P13 is connected to the node Q, and both ends of the transistor P13 are connected between the node P and the voltage terminal VH. The gate of the transistor P14 is connected to the input terminal IN1, and both ends thereof are connected between the node Q and the voltage terminal VH. Capacitor C1 is connected between node Q and voltage terminal VH.

The gates of the transistors P15 and P16 are connected to the node P and both ends of the transistor P15 are connected between the clock terminal CK2 and the output terminal COUT, Is connected between the clock terminal CK2 and the output terminal OUT. The gates of the transistors P17 and P18 are connected to the node Q. Both ends of the transistor P17 are connected between the output terminal COUT and the voltage terminal VH, Is connected between the output terminal OUT and the voltage terminal VH. The capacitor C2 is connected between the node P and the output terminal COUT. The level of the gate signal S [i] depends on the voltage of the output terminal OUT.

The coupling pulse output circuit 22 includes two transistors P19 and P20. The gate of the transistor P19 is connected to the node Q, and both ends of the transistor P19 are connected between the output terminal COUT and the wiring to which the voltage CPH is supplied. The gate of the transistor P20 is connected to the node P, and both ends thereof are connected between the input IN2 and the output COUT.

The voltage of the node P and the voltage of the node Q control the gate signal which is the output of the shift register circuit 21 and the coupling pulse output circuit 22 also outputs the voltage One of the continuous coupling pulse CSP and the high-level voltage CPH can be selected and output according to the control signal.

For example, an on-level gate signal and a coupling pulse are outputted in accordance with the voltage of the node P, and a gate signal of an off level and a coupling pulse are outputted in accordance with the voltage of the node Q.

Hereinafter, the operation of the gate driving circuit according to the embodiment will be described with reference to Figs. 5 and 6. Fig.

5 is a waveform diagram showing a continuous coupling pulse, a start pulse, a plurality of gate signals, and a plurality of coupling pulses according to the embodiment.

6 is a waveform diagram of clock signals according to an embodiment.

As shown in FIG. 5, the period of the continuous coupling pulse CSP is a horizontal period, and the continuous coupling pulse CSP alternately has a low level and a high level in the horizontal period. The period of the start pulse SP is one frame period and has a low level pulse synchronized with the start point of one frame. The carry signal and the gate signal have the same waveform and the waveform of the carry signal is not shown in Fig.

As shown in Fig. 6, the period of each of the plurality of clock signals CLK1 to CLK4 is four horizontal periods. There is a phase difference of one horizontal cycle between the clock signal CLK1 and the clock signal CLK2, between the clock signal CLK2 and the clock signal CLK3, and between the clock signal CLK3 and the clock signal CLK4.

At time T0, the gate signal S [0] and the continuous coupling signal CSP fall to a low level. The gate signal S [0] is at the low level during the period T0-T2 and during the period T0-T2, in the plurality of sensor pixels TPX of the first sensor pixel row, the gate of the transistor P1 and the gate of the transistor P2 The voltage is reset to the high level of the coupling pulse CP [1].

During the period T0-T2, the transistor P11 is turned on in the shift register 21 of the stage 20_1 to decrease the voltage of the node P to the low level of the carry signal CA [0] And the transistor P16 are turned on. The transistor P14 is also turned on by the low level carry signal CA [0], and the voltage of the node Q becomes the high level voltage VDD. Then, the three transistors P17, P18 and P19 are turned off.

The continuous coupling pulse CSP rises to the high level and the coupling pulse CP [n] rises to the high level at the time point T1.

During the period T2, the clock signal CLK1 falls to the low level, the level is low during the period T2-T4, and the transistors P15 and P16 are in the on-state, the gate signal S [ to be. Since the node P is coupled through the output terminal OUT and the capacitor C2, the voltage of the node P decreases with the decrease of the output terminal OUT voltage. That is, the voltage of the node P decreases in synchronization with the decrease of the clock signal CLK1, and the transistor P20 is turned on. Then, the coupling pulse CP [1] falls to the low level along the continuous coupling pulse CSP at the time point T2 and rises to the high level at the time point T3.

When the coupling pulse CP [1] falls to the low level, the gate voltage of the transistor P1 falls in the plurality of sensor pixels TPX of the first pixel row, and the gate voltage of the transistor P2 changes. During the period T2-T4, since the transistor P4 is in a turned-on state, the current or output voltage flowing through the transistor P2 is transmitted to the sensor signal lead-out circuit 40 through the data line.

The clock signal CLK1 rises to the high level and the gate signal S [l] rises to the high level at the time T4. Then, the voltage of the node P increases, and the transistor P20 is turned off.

At time T6, the clock signal CLK3 falls to the low level and the transistor P12 is turned on, and the voltage of the node Q becomes the low level. Then, the transistors P17, P18 and P19 are turned on so that the gate signal S [1] and the coupling pulse CP [1] are held at the high level. The transistor P13 is also turned on at the time T6 so that the voltage of the node P becomes the high level voltage VDD and the transistors P15 and P16 are turned off.

In the shift register 21 of the next stage 20_2, during the period T2-T4, the transistor P11 conducts and the voltage of the node P decreases to the low level of the carry signal CA [1] P15 and the transistor P16 are turned on. The transistor P14 is also turned on by the low level carry signal CA [1], and the voltage of the node Q becomes the high level voltage VDD. Then, the three transistors P17, P18 and P19 are turned off.

At the time T4, the clock signal CLK2 falls to the low level, the level is low during the period T4-T6, and the gate signal S [2] is also at the low level during this period. The voltage of the node P decreases in synchronization with the decrease of the clock signal CLK2, and the transistor P20 is turned on. Then, the coupling pulse CP [2] falls to the low level along the continuous coupling pulse CSP at the time T4, and rises to the high level at the time T5.

The clock signal CLK2 rises to the high level and the gate signal S [2] rises to the high level at the time T6. Then, the voltage of the node P increases, and the transistor P20 is turned off.

At time T8, the clock signal CLK4 falls to the low level, the transistor P12 is turned on, and the voltage of the node Q becomes the low level. Then, the transistors P17, P18 and P19 are turned on so that the gate signal S [2] and the coupling pulse CP [2] are maintained at the high level. The transistor P13 is also turned on at the time point T8 so that the voltage of the node P becomes the high level voltage VDD and the transistors P15 and P16 are turned off.

Since this operation is repeated, the gate signal S [3] of the next stage 20_3 is at the low level during the period T6-T8 and the coupling pulse CP [3] is at the low level during the period T6-T7. The gate signal S [n-1] of the stage 20_n-1 is at the low level during the period T10-T12 and the coupling pulse CP [ the gate signal S [n] of the stage 20_n is at the low level during the period T12-T14 and the coupling pulse CP [n] is at the low level during the period T10-T11, -T13 is low level.

The start pulse SP for starting the next frame becomes a low level pulse at the time point T9. Then, in the same manner as the above-described operation, a plurality of gate signals and a plurality of coupling signals sequentially become low-level pulses during the next frame period.

7 is a diagram illustrating a stage according to another embodiment.

Although the shift register circuit and the coupling pulse output circuit are provided in the stage in the above embodiment, a shift register circuit and a coupling pulse output circuit are separately provided in another embodiment. The contents overlapping with those of the previous embodiment are omitted from the description of other embodiments.

As shown in Fig. 7, the stage 20_i includes a divided shift register circuit 23 and a coupling pulse output circuit 24. As shown in Fig.

The shift register circuit 23 includes an input terminal IN1, two clock stages CK1 and CK2, two output stages OUT and COUT, and a voltage stage VH. The carry signal CA [i-1] of the immediately preceding stage is input to the input terminal IN1 and the clock signals CLK [p] and CLK [q] corresponding to the two clock stages CK1 and CK2 are input do. The gate signal S [i] is outputted through the output terminal OUT and the carry signal CA [i] is outputted through the output terminal COUT.

The coupling pulse output circuit 24 includes three input terminals G1, G2 and IN2 and one output terminal CPOUT.

The voltage of the node P is input to the input terminal G1 and the voltage of the node Q is input to the input terminal G2 and the continuous coupling pulse CSP is input to the input terminal IN2. And the coupling pulse CP [i] is output through the output terminal CPOUT.

As described above, according to the embodiments, the coupling pulse is supplied to each of the plurality of sensor pixel rows, so that the load of the coupling pulse can be reduced as compared with the conventional one. This can solve the problem of increasing the RC delay time of the coupling pulse in the conventional large area fingerprint recognition sensor.

 While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

1: Fingerprint sensor
10: Sensor panel
20: Gate driving circuit
30: Timing control circuit
40: Sensor signal lead-out circuit
20_0 to 20_n: stage
21, 23: Shift register circuit
22, 24: coupling pulse output circuit

Claims (14)

A sensor panel including a plurality of sensor pixels, a plurality of gate lines, a plurality of coupling lines, and a plurality of data lines; And
And a gate driving circuit which supplies a plurality of gate signals to the plurality of gate lines and supplies a plurality of coupling pulses synchronized with the plurality of gate signals to the plurality of coupling lines,
Wherein the plurality of coupling pulses are pulse signals for successively performing coupling in the plurality of sensor pixels,
Wherein each of the plurality of sensor pixels comprises:
A first transistor including an end connected to a corresponding data line; And
And a second transistor including one end connected to the other end of the first transistor,
Wherein when the coupling pulse changes to a second level after the gate of the second transistor is reset by the first coupling pulse level, the gate voltage of the second transistor corresponding to the voltage change of the coupling pulse Wherein the fingerprint sensor is a fingerprint sensor. The method according to claim 1,
Wherein the gate driving circuit comprises:
A plurality of stages,
Wherein each of the plurality of stages includes:
And generates a corresponding gate signal and a corresponding coupling pulse to supply the gate signal and the corresponding coupling line to the corresponding gate line. The method according to claim 1,
Wherein each of the plurality of stages includes:
Wherein the first node receives a first clock signal and a second clock signal corresponding to the first clock signal and the gate signal of the immediately preceding stage and the voltage of the first node changes according to the on level of the gate signal of the previous stage, A shift register circuit for outputting the shift register circuit; And
A coupling pulse output circuit for receiving a continuous coupling pulse and outputting the continuous coupling pulse as the corresponding coupling pulse in accordance with the voltage of the first node,
And a fingerprint sensor. The method of claim 3,
The shift register circuit comprising:
At least one transistor including a gate connected to the first node, one end to which the first clock signal is input, and the other end connected to the output terminal of the shift register circuit; And
And a capacitor connected between the first node and the output terminal of the shift register circuit,
The coupling pulse output circuit includes:
And a transistor including a gate connected to the first node, one end to which the continuous coupling pulse is input, and the other end to be connected to the output end of the coupling pulse output circuit. The method of claim 3,
The shift register circuit comprising:
The voltage of the second node is changed in accordance with the second clock signal of the corresponding two clock signals to maintain the corresponding gate signal at the off level,
The coupling pulse output circuit includes:
And maintains the corresponding coupling pulse at an off level according to the voltage of the second node. 6. The method of claim 5,
The shift register circuit comprising:
At least one transistor including a gate connected to the second node, one end connected to a voltage end to which the voltage of the off level is input, and the other end connected to an output end of the shift register circuit; And
And a capacitor coupled between the second node and the voltage terminal,
The coupling pulse output circuit includes:
And a transistor including a gate connected to the second node, one end of which the voltage of the off level is input, and the other end connected to the output terminal of the coupling pulse output circuit. The method of claim 3,
Wherein the shift register circuit and the coupling pulse output circuit together constitute a corresponding stage. The method of claim 3,
Wherein the shift register circuit and the coupling pulse output circuit constitute stages corresponding to each other. The method according to claim 1,
Each of the plurality of gate lines is formed in a first direction and arranged in a second direction crossing the first direction,
Wherein each of the plurality of coupling lines is formed in the first direction and is arranged in the second direction,
Wherein each of the plurality of data lines is formed in the second direction and is arranged in the first direction. The method according to claim 1,
In each of the plurality of sensor pixels, a capacitance is coupled according to a coupling pulse transmitted through a corresponding coupling line, and a data signal is transmitted to a corresponding data line according to a gate signal transmitted through a corresponding gate line Fingerprint recognition sensor. Sequentially supplying a plurality of gate signals to a plurality of sensor pixels;
Sequentially supplying a plurality of coupling pulses to the plurality of sensor pixels;
In each of the plurality of sensor pixels, coupling is continuously performed in accordance with a corresponding coupling pulse so that capacitance is coupled; And
And transmitting data signals of the plurality of sensor pixels to a plurality of data lines in synchronization with each of the plurality of gate signals,
Each of the plurality of coupling pulses being synchronized to a corresponding gate signal,
Wherein each of the plurality of sensor pixels comprises:
A first transistor including an end connected to a corresponding data line; And
And a second transistor including one end connected to the other end of the first transistor,
Wherein when the coupling pulse changes to a second level after the gate of the second transistor is reset by the first coupling pulse level, the gate voltage of the second transistor corresponding to the voltage change of the coupling pulse Further comprising the step of changing the fingerprint sensor. 12. The method of claim 11,
Generating a first clock signal of at least two clock signals as an (i + 1) -th gate signal according to an on level of an i-th gate signal among the plurality of gate signals; And
The first clock signal is changed to the on level and the continuous coupling pulse is generated as the (i + 1) th coupling pulse according to the on level of the first clock signal. 13. The method of claim 12,
And the i + 1 < th > gate signal and the (i + 1) < th > coupling pulse are kept at an off level according to a second clock signal of the at least two clock signals. 12. The method of claim 11,
Coupling capacitances in each of the plurality of sensor pixels according to a coupling pulse transmitted through a corresponding coupling line; And
Further comprising the step of, in each of the plurality of sensor pixels, transmitting a data signal to a corresponding data line according to a gate signal transmitted through a corresponding gate line.

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