KR101957338B1 - Wafer level vacuum sealing method using conformal deposition - Google Patents

Abstract

A wafer level vacuum sealing method using conformal deposition methods is disclosed. The disclosed wafer level vacuum sealing method includes the steps of providing a readout circuit wafer having a plurality of arrays of a plurality of detection elements disposed thereon and a capping wafer for packaging the array of detectors in vacuum on the readout circuit wafer Bonding the capping wafer to the readout circuit wafer; and sealing the via hole formed in the capping wafer with a via material by a conformal deposition method.

Description

[0001] The present invention relates to a wafer level vacuum sealing method using a conformal deposition method,

To a wafer level vacuum sealing of a capping wafer on a wafer having a plurality of infrared thermal detector arrays.

The infrared ray thermal sensor receives infrared rays emitted from an object having a temperature and detects the infrared ray to generate a detection signal. An object having an arbitrary temperature (T) emits a broad band of light that exhibits a maximum value at a specific wavelength by blackbody radiation. The light emitted from the ambient temperature object emits infrared rays having a maximum value in a wavelength band of approximately 10 mu m. When the radiated infrared rays are incident on the thermal mass, the temperature is increased. Polarity, electromotive force, and warpage can be changed depending on the thermal mass material due to the temperature change due to the infrared ray incident, and this change can be quantified to form an image array, resulting in a thermal image.

The change in temperature that occurs in a thermal element due to infrared incidence largely depends on the thermal conductivity with the peripheral part. The thermal conductivity is determined by convection and conduction, and the thermal conductivity by conduction is mainly determined by the structure and material of the device, and the thermal conductivity by convection is determined by the degree of vacuum at the time of sealing the device.

While sealing the infrared lumen sensor array, the metal can or ceramic package surrounds the lumen sensor array due to the constant degree of vacuum and the protection of the lumen sensor array. However, due to the high cost and the necessity of individual sealing for each array, Level vacuum sealing method is required.

A wafer level vacuum sealing method using conformal deposition methods in accordance with an embodiment of the present invention provides a method of vacuum sealing capping wafers on a readout circuit wafer on which a thermal sensor array is formed at a wafer level.

A wafer level vacuum sealing method using a conformal deposition method in accordance with an embodiment of the present invention includes:

Providing a readout circuit wafer on which a plurality of arrays of a plurality of detection elements are arranged;

Providing a capping wafer for vacuum packaging the sensing element array on the readout circuit wafer;

Bonding the capping wafer to the readout circuit wafer; And

And sealing the via hole formed in the capping wafer with a via material by a conformal deposition method.

The detecting element may be an infrared luminescence detector.

The capping wafer forming step may include forming a recess corresponding to the detecting element array, and the recess may form a cavity surrounding the corresponding detecting element array.

The via hole is formed before the bonding step or after the bonding step.

The via hole may be formed to communicate with the cavity.

The via hole may have a diameter of 1 to 10 탆.

Wherein the reading circuit wafer preparation step and the capping wafer preparation step each include depositing a bonding metal at positions corresponding to each other in an area surrounding the sensing element array,

The bonding step may include heat treating the read circuit wafer and the capping wafer in a state in which the bonding metal is in contact with each other.

Each of the bonding metals may be a double layer structure of gold (Au) or Au / tin (Sn).

The sealing step may be performed in a vacuum deposition apparatus under a process pressure of about 1-10 mm Torr so that the degree of vacuum of the cavity is substantially equal to the process pressure.

The encapsulating step may include flattening the via material formed on the capping wafer to expose one side of the capping wafer.

The capping wafer may be made of silicon.

According to the wafer level vacuum sealing method using the conformal deposition method according to the embodiment of the present invention, since the space between the two wafers is vacuum-sealed at the wafer level, the productivity is improved as compared with the conventional metal can or ceramic packaging.

In addition, a relatively inexpensive silicon window can be used instead of the conventional expensive infrared window.

1 is a cross-sectional view illustrating a wafer level sealed lacquer sensor array fabricated in accordance with an embodiment of the present invention.
FIGS. 2A through 2E are views for explaining a wafer level vacuum sealing method using a conformal deposition method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of the layers or regions shown in the figures are exaggerated for clarity of the description. The same reference numerals are used for substantially the same components throughout the specification and the detailed description is omitted.

1 is a cross-sectional view illustrating a wafer level sealed lacquer sensor array fabricated in accordance with an embodiment of the present invention.

Referring to FIG. 1, a plurality of luminescence sensor arrays are disposed between a lower wafer 110 and an upper wafer 120. FIG. 1 shows two liner array 130 for convenience. Each lath sensor array 130 includes a plurality of lath sensors 132 on a lower wafer 110. The lattice detectors 132 may be arranged in a matrix array, and in FIG. 1, five lattice detectors are shown for convenience. The luminescence sensor 132 may be a luminescence sensor for detecting infrared rays of a wavelength band of approximately 10 mu m.

The lower wafer 110 and the upper wafer 120 are bonded to the bonding metal 150. The bonding metal 150 is formed by heat-treating the lower wafer 110 and the upper wafer 120 in a state where a single layer of gold (Au) or a portion of Au / Sn (tin) . The bonding metal 150 is formed to enclose the lumen sensor array 130 to maintain a vacuum state therein.

A via hole 122 is formed in the upper wafer 120 of each thermal image sensor array 130. The via hole 122 is filled with a metal or a dielectric and is sealed. The material filling the bonding metal 150 and the via hole 122 seals the lid array 130 at a predetermined degree of vacuum. The upper wafer 120 may be provided with a recess 128 to cover the lid array 130 on the lower wafer 110 to provide a cavity 128. The via hole 122 is formed to communicate with the cavity 128.

The cavity 128 is formed in the upper wafer 120, but the present invention is not limited thereto. For example, the lower wafer 110 and the upper wafer 120 may be formed by forming the recess 124 in the lower wafer 110 and the upper wafer 120, respectively.

The upper wafer 120 covers the thermal sensor array 130 on the lower wafer 110 and is also referred to as a capping wafer.

The lower wafer 110 may be a read-out integrated circuit (ROIC) wafer. The lower wafer 110 is hereinafter also referred to as a read circuit wafer. The readout circuit wafer 110 has a wiring (not shown) connected to each of the lath sensors 132 on the upper surface thereof and connects an electrical signal from the lath sensor 132 to the outside. In particular, the use of the readout circuit wafer 110 is inevitable in order to externally connect the signal from the array of the lid array 130 consisting of several hundred pixels or more.

The lower wafer 110 may be formed of various materials such as plastic, glass, and semiconductor materials. Particularly, the lower wafer 110 can be a silicon wafer widely used in a semiconductor process, and can form a readout circuit wafer 110 through a wiring process, a via process, or the like.

The upper wafer 120 may be formed of a material, such as silicon, from which infrared radiation can be transmitted.

Infrared rays incident on the capping wafer 120 are incident on the thermal detector 132 of the thermal detector array 130, i.e., the thermal mass not shown. The incident infrared ray causes the temperature of the heat detector 132 to rise, and the resistance of the heat detector 132 may vary with the temperature change. The changed resistance is detected through a wiring formed on the readout circuit wafer 110, and a signal is transmitted to the outside.

Hereinafter, a wafer level vacuum sealing method using a conformal deposition method according to an embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 2A through 2E are views illustrating a wafer level vacuum sealing method of a thermal detector wafer using a conformal deposition method according to an embodiment of the present invention.

Referring to FIG. 2A, a read circuit wafer 210 is provided. A plurality of thermal image sensor arrays 230 are disposed on the readout circuit wafer 210. In FIG. 2a, two liner array 230 are shown for convenience. Each lattice detector array 230 includes a plurality of lattice detectors 232 disposed in a matrix array on readout circuit wafer 210. In FIG. 2a, five lath detectors 232 are shown as a single lath array 230 for convenience.

Wiring (not shown) is connected to each of the readout circuit wafers 210 under the respective row-shaped sensors 232, and the wirings are connected to the outside, thereby facilitating electrical contact to the outside. As the readout circuit wafer 210, various materials can be used, and a silicon wafer, for example, can be used.

A bonding metal 215 is deposited on the readout circuit board so as to surround the periphery of each thermal image sensor array 230. The bonding metal 215 may be formed as a single layer of gold (Au) or Au / Sn (tin) in a two-layer structure. Deposition of the bonding metal 215 is performed using a deposition method commonly known in semiconductor processing, and a detailed description thereof will be omitted.

Referring to FIG. 2B, a capping wafer 220 is prepared. The capping wafer 220 is a lid that covers the lumen sensor array 230 and is intended to maintain the lumen sensor array 230 area at a Torr vacuum degree of approximately 1-10 mm. On the inner surface facing the readout circuit wafer 210 from the capping wafer 220, recesses 224 are formed in the regions corresponding to the respective row-sensor arrays 230. Then, a bonding metal 225 is deposited on an area corresponding to the area where the bonding metal 215 of the readout circuit wafer 210 is deposited on the flat surface of the inner surface. The bonding metal 225 may be formed of the same material as the bonding metal 215 on the readout circuit wafer 210.

The capping wafer 220 may be made of a material that is transparent to infrared light, such as silicon.

At capping wafer 220, at least one via hole 222 is formed in each lath array 230 by a deep RIE method. The diameter of the via hole 222 may be approximately 1 to 10 mu m. The capping wafer 220 may have a thickness of several tens to several hundreds of micrometers. When the diameter of the via hole 222 is 1 탆 or less, the via hole 222 may be difficult to form due to the high cross-sectional area of the via hole 222. When the diameter of the via hole 222 is 10 占 퐉 or more, the material used for the conformal deposition described later increases, and the deposition time may increase.

The formation process of the via hole 222 may be performed in the process of providing the capping wafer 220, or may be performed after the bonding process described below.

In addition, the recess 224 for forming the cavity 228 does not necessarily have to be formed on the capping wafer 220. For example, it may be formed on the readout circuit wafer 210.

Referring to FIG. 2C, the capping wafer 220 is bonded onto the readout circuit wafer 210. In this case, the bonding metal 215 of the readout circuit wafer 210 and the bonding metal 225 of the capping wafer 220 are brought into contact with each other. Then, the bonding metal 215 is heat-treated at a predetermined temperature according to the bonding metals 225 and 225 and bonded. For example, when Au single layer is used for the bonding metals 215 and 225, the bonding process is performed at about 600 ° C, which is below the melting temperature of Au.

When the Au / Sn double layer is used as the bonding metals 215 and 225, the bonding process may be performed at a eutectic temperature depending on the composition, for example, 270 ° C. The bonding metal 215 of the readout circuit wafer 210 and the bonding metal 225 of the capping wafer 220 are bonded to form the bonding metal 250.

2d, the readout circuit wafer 210 and the capping wafer 220 bonded product are placed in a vacuum deposition chamber (not shown) for depositing in vacuum, and then the process pressure is maintained at approximately 1 to 10 mm Torr The capping wafer 220 is subjected to conformal deposition. The deposition method is performed by conventional chemical vapor deposition (CVD) or physical vapor deposition (PVD). In this process, the degree of vacuum in the cavity 228 is maintained at about 1 to 10 mmTorr, which is the process vacuum degree in the vacuum deposition chamber, and at the same time, conformal deposition is performed with the via hole 222. The via material 240 filling the via hole 222 may be a metal or a dielectric material commonly used in a deposition process and is not particularly limited.

The via material 242 may be deposited on the capping wafer 220 in the process of filling the via hole 222 with the via material 240 for sealing in a vacuum state.

Referring to FIG. 2E, via material 242 on capping wafer 220 is removed by a conventional chemical mechanical polishing (CMP) process. The removal of the via material 242 may be accomplished by a grinding method.

Thereafter, an element including each array element 230 can be individually formed using a conventional dicing method, and a detailed description thereof will be omitted.

Although the thermal sensor array 230 is described above as an example of the detection element array, the present invention is not limited thereto. That is, another detection element array is disposed between the readout circuit wafer 210 and the capping wafer 220, and the area including each array may be applied to a wafer level vacuum sealing method requiring a predetermined degree of vacuum.

According to the wafer level vacuum sealing method using the conformal deposition method according to the embodiment of the present invention, productivity is improved as compared with the conventional metal can or ceramic packaging because the vacuum between the two wafers is sealed at the wafer level.

In addition, a relatively inexpensive silicon window can be used instead of the conventional expensive infrared window.

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined by the appended claims. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

210: readout circuit wafer 220: capping wafer
222: via hole 224:
223: Cavity 230: Thermal sensor array
232: Thermal sensor 240: Via material
250: Bonding metal

Claims (11)

Providing a readout circuit wafer having a plurality of arrays of a plurality of detection elements arranged therein;
Providing a capping wafer for vacuum packaging the sensing element array on the readout circuit wafer;
Forming a cavity for forming a cavity corresponding to the detection element array on the capping wafer and forming a via hole passing through the cavity;
Bonding the capping wafer to the readout circuit wafer; And
And sealing the via hole with a via material by a conformal deposition method. The method according to claim 1,
Wherein the detecting element is a wafer level vacuum sealing method using a conformal deposition method which is an infrared ray thermal image sensor. delete delete delete The method according to claim 1,
Wherein the via hole is formed with a diameter of 1 to 10 占 퐉. The method according to claim 1,
Wherein the reading circuit wafer preparation step and the capping wafer preparation step each include depositing a bonding metal at positions corresponding to each other in an area surrounding the sensing element array,
Wherein the bonding step comprises heat treating the readout circuit wafer and the capping wafer in a state in which the bonding metals of the capping wafer and the capping wafer are in contact with each other. 8. The method of claim 7,
Wherein the bonding metal is a double layer of gold (Au) or Au / tin (Sn). The method according to claim 1,
Wherein the sealing step is performed in a vacuum deposition apparatus under a process pressure of 1-10 mm Torr so that the vacuum degree of the cavity is substantially equal to the process pressure. The method according to claim 1,
Wherein the encapsulating step includes planarizing the via material formed on the capping wafer to expose one side of the capping wafer. ≪ RTI ID = 0.0 >< / RTI > The method according to claim 1,
Wherein the capping wafer is a silicon wafer.

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