KR102012901B1 - Operating method of input/output(i/o) interface - Google Patents

Abstract

An operation method of the input / output interface includes selecting any one of a plurality of output driver circuits according to a mode selection signal and outputting a data signal using any one selected output driver circuit.

Description

Operation method of input / output interface {OPERATING METHOD OF INPUT / OUTPUT (I / O) INTERFACE}

An embodiment according to the concept of the present invention relates to a method of operating an input / output interface, and in particular, may select one of a plurality of output driver circuits or one of a plurality of input receiver circuits according to an operation mode. A method for operating an input / output interface.

Each of a system on chip (SoC) including a central processing unit (CPU), a memory controller, and the like, and a memory device (eg, main memory) connected to the SoC interface each other. I / O interface for interfacing) is included.

As the operating speed increases, as the swing width of the data signal transmitted and received between the SoC and the memory device decreases, not only the influence of external noise increases but also the impedance miss in the input / output interface. Impedance mismatching can be a problem.

In order to solve the impedance mismatch, the input / output interface may include an impedance matching circuit called on-die termination or on-chip termination.

The technical problem to be achieved by the present invention is to provide a method for operating an input / output interface that can select any one of a plurality of output driver circuits or any one of a plurality of input receiver circuits according to the operation mode.

According to an embodiment of the present invention, a method of operating an input / output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using any one selected output driver circuit. It may include.

According to an embodiment, the mode selection signal may be a control signal for controlling an on-die termination (ODT) circuit included in the input / output interface.

According to an embodiment of the present disclosure, the method may further include generating the mode selection signal according to memory latency.

According to an embodiment, the memory latency may be a read latency or a write latency.

According to an embodiment of the present disclosure, the method may further include generating the mode selection signal based on a mode register set (MRS) command for adjusting an operating frequency.

According to an embodiment, the selecting may include selecting an output driver circuit including an NMOS pull-up transistor when the mode selection signal indicates an operation mode for high-speed operation, wherein the mode selection signal is When instructing an operation mode for low speed operation, an output driver circuit including a PMOS pull-up transistor can be selected.

The method may further include selecting one of a plurality of termination levels of an ODT circuit included in the input / output interface according to the mode selection signal.

According to an embodiment, the plurality of termination levels may include a power supply voltage level, a ground level, and an intermediate level between the power supply voltage level and the ground level.

According to an embodiment of the present invention, a method of operating an input / output interface includes selecting one of a plurality of input receiver circuits according to a mode selection signal, and receiving a data signal using one selected input receiver circuit. It may include.

According to an embodiment, the mode selection signal may be a control signal for controlling an on-die termination (ODT) circuit included in the input / output interface.

According to an embodiment, the method may further include generating the mode selection signal according to a memory latency, wherein the memory latency may include read latency and write latency.

According to an embodiment of the present disclosure, the method may further include generating the mode selection signal based on a mode register set (MRS) command for adjusting a memory operating frequency.

According to an embodiment of the present disclosure, the selecting may include selecting different input receiver circuits when the mode selection signal indicates an operation mode for high speed operation and when the mode selection signal indicates an operation mode for low speed operation.

According to an embodiment, the selecting may include selecting one of the input receiver circuits having a plurality of stages when the mode selection signal indicates an operation mode for high speed operation.

According to an embodiment of the present disclosure, the selecting may include selecting one of the input receiver circuits including different types of MOS transistors connected in series when the mode selection signal indicates an operation mode for low speed operation. .

The method according to an embodiment of the present invention can implement an input / output interface suitable in the operation mode by selecting and using an output driver circuit or an input receiver circuit according to the operation mode.

The method according to an embodiment of the present invention has an effect of improving power efficiency and maintaining good characteristics of a transmission signal by selecting and using an output driver circuit or an input receiver circuit suitable for the operation mode.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.
1 is a block diagram of a memory system according to an exemplary embodiment.
FIG. 2 is a block diagram of an example embodiment of the memory device illustrated in FIG. 1.
3 is a block diagram illustrating another example embodiment of a memory device illustrated in FIG. 1.
FIG. 4 is a block diagram according to an embodiment of the first input / output interface shown in FIG. 2.
FIG. 5 is a circuit diagram illustrating an output driver block shown in FIG. 4.
6 is a circuit diagram of another example of the output driver block shown in FIG. 4.
FIG. 7 is a block diagram according to an exemplary embodiment of the input receiver block shown in FIG. 4.
FIG. 8 shows an exemplary waveform diagram of a data signal input to the input receiver block shown in FIG. 7.
FIG. 9 is a circuit diagram illustrating an example of a first input receiver circuit shown in FIG. 7.
FIG. 10 is a circuit diagram of an example of a second input receiver circuit shown in FIG. 7.
FIG. 11 is a circuit diagram according to another exemplary embodiment of the second input receiver circuit shown in FIG. 7.
FIG. 12 is a circuit diagram of an example of a third input receiver circuit shown in FIG. 7.
FIG. 13 is a circuit diagram illustrating an example of an on-die termination (ODT) circuit illustrated in FIG. 4.
FIG. 14 is a block diagram according to another exemplary embodiment of the first input / output interface illustrated in FIG. 2.
15 is a flowchart illustrating a method of operating an input / output interface according to an embodiment of the present invention.
16 is a flowchart illustrating a method of operating an input / output interface according to another embodiment of the present invention.
17 is a conceptual diagram illustrating an embodiment of a package including the memory device shown in FIG. 1.
FIG. 18 is a conceptual diagram three-dimensionally illustrating an embodiment of a package including the memory device shown in FIG. 1.
FIG. 19 is a block diagram illustrating a system-in-package and a nonvolatile memory device including the memory system illustrated in FIG. 1.
20 is a block diagram according to another exemplary embodiment of a system-in-package including the memory system illustrated in FIG. 1.
FIG. 21 is a block diagram illustrating a memory system including the memory device illustrated in FIG. 1.
FIG. 22 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.
FIG. 23 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.
FIG. 24 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.
FIG. 25 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.

Specific structural to functional descriptions of the embodiments according to the inventive concept disclosed herein are merely illustrated for the purpose of describing the embodiments according to the inventive concept. It may be embodied in various forms and should not be construed as limited to the embodiments set forth herein.

Embodiments according to the inventive concept may be variously modified and have various forms, so specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments in accordance with the concept of the present invention to a particular disclosed form, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another, for example, without departing from the scope of rights in accordance with the inventive concept, and the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a memory system according to an exemplary embodiment.

Referring to FIG. 1, a memory system 10 according to an embodiment of the present invention may include a memory device 100, such as a main memory and a system on chip (SoC). ; 200).

According to an embodiment, the memory system 10 may be implemented as a mobile application processor (AP), but the technical scope of the present invention is not limited thereto.

The memory device 100 may include a first internal circuit 110 and a first input / output (I / O) interface 120 constituting the inside of the memory device 100.

According to an embodiment, the memory device 100 may be implemented as a dynamic random access memory (DRAM), for example, a synchronous DRAM (SDRAM), but the technical scope of the present invention is not limited thereto.

The first input / output interface 120 may interface a data signal input or output between the first internal circuit 110 and the SoC 200.

The first internal circuit 110 and the first input / output interface 120 are described in detail with reference to FIGS. 2 to 16.

The memory device 100 may be connected to the SoC 200 through a bus 101.

The SoC 200 may include a second internal circuit 210 and a second input / output interface 220 constituting the inside of the SoC 200.

According to an embodiment, the second internal circuit 210 may include a central processing unit (CPU), a graphic processing unit (GPU), and / or a memory controller for performing overall operations of the memory system 10. (memory controller; not shown) and the like.

According to an embodiment, the second input / output interface 220 may be included in the memory controller.

The structure of the second internal circuit 210 is substantially the same as that of the first internal circuit 110.

FIG. 2 is a block diagram of an example embodiment of the memory device illustrated in FIG. 1.

1 and 2, the first internal circuit 110 of the memory device 100 may include a control logic 130, a refresh counter 132, a row multiplexer 134, A plurality of row buffers 136, a plurality of row decoders 138, bank control logic 140, a plurality of column buffers 142, a plurality of columns Column decoders 144, a plurality of banks 150, and input / output gates 154 may be included.

The control logic 130 may respond to a plurality of signals (clock signal CK, command signal CMD, and address signal ADD) in response to each component (eg, refresh counter 132, row multiplexer). 134, the bank control logic 140, or the plurality of column buffers 142 may be controlled.

The command signal CMD may refer to a combination of a plurality of commands (eg, CS, RAS, CAS, and / or WE). According to an embodiment, the command signal CMD and the address signal ADD may be transmitted from a memory controller (not shown) included in the SoC 200.

The control logic 130 may include a command decoder 130-1 and a mode register 130-2. According to an embodiment, the command decoder 130-1 and / or the mode register 130-2 may be separately implemented outside the control logic 130.

The command decoder 130-1 decodes a command signal CMD composed of a combination of a plurality of signals (eg, CS, RAS, CAS, and / or WE) based on the clock signal CK, and decodes the result of the decoding. Accordingly, a command for controlling each component (eg, the refresh counter 132, the row multiplexer 134, the bank control logic 140, or the plurality of column buffers 142) may be generated.

According to an embodiment, the command decoder 130-1 may generate a refresh command for performing various operations (eg, a read operation, a write operation, or a refresh operation) by decoding the command signal CMD.

The mode register 130-2 stores data for controlling various operation modes of the memory device 100. According to an embodiment, the mode register 130-2 may include data related to memory latency of the memory device 100, data related to an operating frequency, and / or an ODT circuit included in the memory device 100. data necessary for controlling a die termination circuit (not shown) may be stored.

The refresh counter 132 may generate a row address corresponding to the refresh command in response to the refresh command output from the command decoder 130-1.

The row multiplexer 134 may select one of a row address generated by the refresh counter 132 and a row address output from the control logic 130 in response to the selection signal (not shown).

According to an embodiment, when the refresh operation is performed, the row multiplexer 134 may select a row address generated by the refresh counter 132.

According to another embodiment, when a normal memory access operation (eg, a read operation or a write operation) is performed, the row multiplexer 134 may select a row address output from the control logic 130.

Each of the row buffers 136 may buffer a row address output from the row multiplexer 134. According to an embodiment, the plurality of row buffers 136 may be implemented as one row buffer, but is not limited thereto.

The row decoder corresponding to the bank selected by the bank control logic 140 among the row decoders 138 may decode the row address output from the row buffer corresponding to the bank among the plurality of row buffers 136. Can be.

According to an embodiment, the plurality of row decoders 138 may be implemented as one row decoder, but is not limited thereto.

The bank control logic 140 may select at least one bank from among the banks 150 according to the control of the control logic 130.

Each of the plurality of column buffers 142 may buffer a column address output from the control logic 130. According to an embodiment, the plurality of column buffers 142 may be implemented as one column buffer, but is not limited thereto.

The column decoder corresponding to the bank selected by the bank control logic 140 among the column decoders 144 may include a column address output from the column buffer corresponding to the bank among the column buffers 142. Can be decoded.

According to an embodiment, the plurality of column decoders 144 may be implemented as one column decoder, but is not limited thereto.

Each of the plurality of banks 150 includes a memory cell array 151, each of which is labeled level Bank 0 through Bank N, and a sense amplifier and write driver block. driver block; 152).

For convenience of description, each of the plurality of banks 150 is illustrated as being implemented in a different layer, but the scope and scope of the present invention are limited by the structure and arrangement of the plurality of banks 150. Can not be done.

The memory cell array 151 includes a plurality of word lines (or row lines), a plurality of bit lines (or column lines), and a plurality of memory cells for storing data.

The sense amplifier & write driver block 152 may operate as a sense amplifier that senses and amplifies a voltage change of each bit line when the memory device 100 performs a read operation.

The sense amplifier & write driver block 152 may operate as a write driver capable of driving each of a plurality of bit lines included in the memory cell array 151 when the memory device 100 performs a write operation. .

The input / output gate 154 transmits the data signals output from the sense amplifier & write driver block 152 to the first input / output interface 120 in response to the column select signal output from any one of the plurality of column decoders 144. Can transmit

According to an embodiment, the input / output gate 154 may transmit data signals input through the first input / output interface 120 to the sense amplifier & write driver block 152 in response to the column selection signal.

According to an embodiment, the input / output gate 154 may be included in the first input / output interface 120.

The first input / output interface 120 may be controlled by the mode selection signal MSEL transmitted from the control logic 130. According to an embodiment, the circuits included in the first input / output interface 120 may be selectively used according to the mode selection signal MSEL.

According to an embodiment, the mode selection signal MSEL may be generated by the control logic 130 based on data for controlling the operation modes of the memory device 100 stored in the mode register 130-2.

According to another exemplary embodiment, the mode selection signal MSEL may be generated by the control logic 130 based on data relating to memory latency stored in the mode register 130-2. For example, the memory latency may be a read latency or a write latency.

According to another embodiment, the mode selection signal MSEL may be generated by the control logic 130 based on data relating to an operating frequency stored in the mode register 130-2.

According to another embodiment, the mode selection signal MSEL may be generated by the control logic 130 based on a mode register set (MRS) command for adjusting an operating frequency.

According to another embodiment, the mode selection signal MSEL may be a control signal for controlling an ODT circuit (not shown) generated by the control logic 130. In this case, the first internal circuit 110 may further include an anti-fuse (not shown) for storing information for controlling the ODT circuit.

According to another embodiment, the memory device 100 may include a separate unit (not shown) for generating the mode selection signal MSEL.

The first input / output interface 120 is described in detail with reference to FIG. 4.

3 is a block diagram illustrating another example embodiment of a memory device illustrated in FIG. 1.

1 to 3, the memory device 100 ′ according to another embodiment of the memory device 100 shown in FIG. 1 may have a mode selection signal MSEL compared to the memory device 100 of FIG. 2. The transmission paths are different.

The mode selection signal MSEL may be transmitted to the first input / output interface 120 from a SoC 200, for example, a memory controller (not shown) included in the SoC 200.

According to an embodiment, the SoC 200 may transmit a control signal for controlling an on-die termination (ODT) circuit included in the first input / output interface 120 to the memory device 100 ′, and the control signal may be The mode selection signal MSEL may be input to the first input / output interface 120.

FIG. 4 is a block diagram according to an embodiment of the first input / output interface shown in FIG. 2.

1, 2, and 4, the first input / output interface 120A according to an embodiment of the first input / output interface 120 illustrated in FIG. 2 may include an output driver block (TX) block; 160, an input receiver block (RX) block 162, an ODT circuit 164, an interface control circuit 166, and an I / O pad 168. can do.

The output driver block 160 may output the data signal transmitted from the input / output gate 154 to the outside of the memory device 100, for example, the SoC 200, through the input / output pad 168.

The output driver block 160 may include a plurality of output driver circuits, which will be described with reference to FIGS. 5 and 6.

The input receiver block 162 may receive a data signal input from the outside of the memory device 100 through the input / output pad 168 and transmit it to the input / output gate 154.

The input receiver block 162 may include a plurality of input receivers, which will be described with reference to FIGS. 7 through 12.

The ODT circuit 164 outputs a data signal to the second input / output interface 220 or the first input / output interface 120A to solve impedance mismatching that may occur when the data signal is input from the second input / output interface 220. ) May be included.

In FIG. 4, the ODT circuit 164 is shown inside the first input / output interface 120A. However, the ODT circuit 164 may be implemented outside the first input / output interface 120A or outside the memory device 100. The technical scope of the present invention should not be limitedly interpreted by the arrangement of the ODT circuit 164.

The ODT circuit 164 is described in detail with reference to FIG.

FIG. 5 is a circuit diagram illustrating an output driver block shown in FIG. 4.

2, 4, and 5, the output driver block 160A according to an embodiment of the output driver block 160 illustrated in FIG. 4 may include a predriver circuit 160A-1, a plurality of pre-driver circuits, and a plurality of output driver blocks 160A-1. Output driver circuits 160A-2 and 160A-3, and a plurality of switches SWT1 and SWT2.

The pre-driver circuit 160A-1 receives a data signal transmitted from the input / output gate 154 and based on the data signal, a plurality of pull-up signals PU1 and PU2 and a plurality of pulldown signals. (pull-down signals; PD1 and PD2) can be generated.

The first output driver circuit 160A-2 may include a PMOS pull-up transistor TXTR1 operating according to the first pull-up signal PU1 and an NMOS pull-down transistor TXTR2 operating according to the first pull-down signal PD1. have.

The first output driver circuit 160A-2 may output the output data signal DOUT1 based on the first pull-up signal PU1 and the first pull-down signal PD1.

The second output driver circuit 160A-3 may include an NMOS pull-up transistor TXTR3 that operates according to the second pull-up signal PU2 and an NMOS pull-down transistor TXTR4 that operates according to the second pull-down signal PD2. have.

The second output driver circuit 160A-3 may output the output data signal DOUT2 based on the second pull-up signal PU2 and the second pull-down signal PD2.

The interface control circuit 166 may generate the selection signals TXSEL1 and TXSEL2 based on the mode selection signal MSEL.

Each of the switches SWT1 and SWT2 may be switched by each of the selection signals TXSEL1 and TXSEL2 output from the interface control circuit 166.

According to an embodiment, when the mode selection signal MSEL indicates an operation mode for high speed operation, the first switch SWT1 is turned off by the first selection signal TXSEL1 and is turned off. The switch SWT2 may be turned on by the second selection signal TXSEL2.

According to another embodiment, when the mode selection signal MSEL indicates an operation mode for low speed operation, the first switch SWT1 is turned on by the first selection signal TXSEL1 and the second switch SWT2 is turned on. May be turned off by the second selection signal TXSEL2.

That is, the first output driver circuit 160A-2 including the PMOS pull-up transistor TXTR1 is used in an operation mode for low speed operation, and the second output driver circuit 160A-3 including the NMOS pull-up transistor TXTR3. Can be used in the operating mode for high speed operation.

6 is a circuit diagram of another example of the output driver block shown in FIG. 4.

4 to 6, the output driver block 160B according to another embodiment of the output driver block 160 illustrated in FIG. 4 includes a pre-driver circuit 160B-1 and a plurality of output driver circuits 160B. -2 and 160B-3).

The pre-driver circuit 160B-1 may receive a data signal transmitted from the input / output gate 154 and generate a plurality of pull-up signals PU3 and PU4 and a pull-down signal PD3 based on the data signal. .

The first output driver circuit 160B-2 is substantially the same as the first output driver circuit 160A-2 in FIG. 5, and the second output driver circuit 160B-3 is the second output driver circuit (FIG. 5). Substantially the same as 160A-3).

The first output driver circuit 160B-2 and the second output driver circuit 160B-3 use the NMOS pull-down transistor TXTR7 in common.

The interface control circuit 166 may generate output driver selection signals TXSEL3 and TXSEL4 based on the mode selection signal MSEL.

Each of the switches SWT3 and SWT4 may be switched by each of the output driver select signals TXSEL3 and TXSEL4 output from the interface control circuit 166.

According to an embodiment, when the mode selection signal MSEL indicates an operation mode for high speed operation, the third switch SWT3 is turned off by the third output driver selection signal TXSEL3 and the fourth switch SWT4. ) May be turned on by the fourth output driver selection signal TXSEL4.

According to another embodiment, when the mode selection signal MSEL indicates an operation mode for low speed operation, the third switch SWT3 is turned on by the third output driver selection signal TXSEL3 and the fourth switch ( SWT4 may be turned off by the fourth output driver select signal TXSEL4.

That is, the first output driver circuit 160B-2 including the PMOS pull-up transistor TXTR5 is used in an operation mode for low speed operation, and the second output driver circuit 160B-3 including the NMOS pull-up transistor TXTR6. Can be used in the operating mode for high speed operation.

FIG. 7 is a block diagram according to an exemplary embodiment of the input receiver block shown in FIG. 4.

4 and 7, the input receiver block 162 may include a plurality of switches SWR1 to SWR3 and a plurality of input receiver circuits 170, 172, and 174.

The interface control circuit 166 may generate a plurality of input receiver selection signals RXSEL1 to RXSEL3 according to the mode selection signal MSEL.

Each of the switches SWR1 to SWR3 may select any one of the input receiver circuits 170, 172, and 174 according to each of the input receiver selection signals RXSEL1 to RXSEL3.

According to an embodiment, the first input receiver circuit 170 has a structure suitable for an operation mode for high speed operation, the second input receiver circuit 172 has a structure suitable for an operation mode for medium speed operation, and has a third input. The receiver circuit 174 may have a structure suitable for an operation mode for low speed operation.

That is, when the mode selection signal MSEL indicates an operation mode for the high speed operation, the first switch SWR1 is turned on according to the first input receiver selection signal RXSEL1 and each of the remaining switches SWR2 and SWR3. Each of the silver input receiver selection signals RXSEL2 and RXSEL3 may be turned off.

In the same manner, the second input receiver 172 may be selected in the operation mode for the medium speed operation, and the third input receiver 173 may be selected in the operation mode for the low speed operation.

The first input receiver circuit 170, the second input receiver circuit 172, or the third input receiver circuit 173 receives the input data signal DIN transmitted from the input / output pad 168, and receives the received input data. The first received data signal RO1, the second received data signal RO2, or the third received data signal RO3 may be output based on the signal DIN.

According to an embodiment, the input receiver block 162 may include only any two of the input receiver circuits 170, 172, and 174.

According to another embodiment, the input receiver block 162 may further include input receiver circuits (not shown) other than the input receiver circuits 170, 172, and 174. In this case, the input receiver block 162 may selectively use any one of four or more input receiver circuits.

The structure of each of the input receiver circuits 170, 172, and 174 is described in detail with reference to FIGS. 8-12.

FIG. 8 shows an exemplary waveform diagram of a data signal input to the input receiver block shown in FIG. 7.

Referring to FIGS. 7 and 8, the first input receiver 170 may be selected and used for the input data signal DIN1 having a high frequency and the signal level swinging near the ground voltage level VSSQ. .

The second input receiver 172 may be selected and used for the input data signal DIN2 in which the frequency is included in the intermediate band and the level of the signal swings near the power supply voltage level VDDQ.

The third input receiver 174 may be selected and used for the input data signal DIN3 having a low frequency and having a large swing level between the ground voltage level VSSQ and the power supply voltage level VDDQ.

FIG. 9 is a circuit diagram illustrating an example of a first input receiver circuit shown in FIG. 7.

Referring to FIGS. 7 and 9, the first input receiver circuit 170 may have a structure having a plurality of stages, for example, two stages.

9 illustrates a structure in which the first input receiver circuit 170 has two stages for convenience of description, but the scope of the present invention should not be limitedly limited by the number of stages.

The first stage 170-1 outputs the data signals DO1 and DO2 based on the input input data signal DIN and the reference voltage signal VREF.

The second stage 170-2 may transmit the received data signal RO1 to the input / output gate 154 based on the data signals DO1 and DO2 output from the first stage 170-1.

As shown in FIG. 9, each of the first stage 170-1 and the second stage 170-2 may be implemented as a P type differential amplifier, but the structure of the first input receiver circuit 170 may be different. Is not limited thereto.

For example, the second stage 170-2 may be implemented as an N-P type differential amplifier instead of the P type differential amplifier. An exemplary structure of the N-P type differential amplifier is shown in FIG.

FIG. 10 is a circuit diagram of an example of a second input receiver circuit shown in FIG. 7.

7 and 10, the second input receiver circuit 172A according to an embodiment of the second input receiver circuit 172 illustrated in FIG. 7 may include an input data signal DIN and a reference voltage signal VREF. Based on the received data signal RO2 can be output.

FIG. 11 is a circuit diagram according to another exemplary embodiment of the second input receiver circuit shown in FIG. 7.

7 and 11, the second input receiver circuit 172B according to another embodiment of the second input receiver circuit 172 illustrated in FIG. 7 may be an N-type differential amplifier 172B-1 and a P-type differential. It can be implemented as an NP type differential amplifier composed of a combination of amplifiers 172B-2.

The input data signal DIN and the reference voltage signal VREF are input to the N type differential amplifier 172B-1 and the P type differential amplifier 172B-2, respectively. The second input receiver circuit 172B may output the received data signal RO2 based on the input input data signal DIN and the reference voltage signal VREF.

The second input receiver circuit 172A or 172B may be implemented as an N type differential amplifier or an NP type differential amplifier as shown in FIGS. 10 and 11, but the structure of the second input receiver circuit 172 is similar thereto. It is not limited.

FIG. 12 is a circuit diagram of an example of a third input receiver circuit shown in FIG. 7.

7 and 12, the third input receiver circuit 174 may be implemented as a CMOS inverter including different types of MOS transistors connected in series.

The third input receiver circuit 174 may receive the input data signal DIN and output the received data signal RO3 based on the received input data signal DIN.

FIG. 13 is a circuit diagram illustrating an example of an on-die termination (ODT) circuit illustrated in FIG. 4.

4 and 13, the ODT circuit 164 includes a plurality of branches B1 to Bn (n is a natural number). The branch B1 includes a first switch SWD1, a first resistor RD1, a second resistor RS1, and a second switch SWS1 connected in series between the power supply VDDQ and the ground VSS. do.

According to an embodiment, the first switch SWD1 may be implemented as a PMOS transistor, and the second switch SWS1 may be implemented as an NMOS transistor.

The termination resistor 184 may have a resistance value according to a combination of the plurality of resistors RD1 to RDn and RS1 to RSn as each of the plurality of switches SWD1 to SWDn and SWS1 to SWSn; n is a natural number. have.

The VDDQ termination switch array 180 may include a plurality of switches SWD1 to SWDn.

Each of the switches SWD1 to SWDn included in the VDDQ termination switch array 180 is turned on or turned on in response to each of the ODT selection signals ODSEL1 to ODSELn output from the interface control circuit 166. Can be off.

The VSSQ termination switch array 182 may include a plurality of switches SWS1 to SWSn.

Each of the switches SWS1 to SWSn included in the VSSQ termination switch array 182 is turned on or turned on in response to each of the ODT selection signals OSSEL1 to OSSELn output from the interface control circuit 166. Can be off.

The ODT circuit 164 may have resistance values of various termination resistors 184 according to the ODT selection signals ODSEL1 to ODSELn and OSSEL1 to OSSELn.

According to an embodiment, when the mode selection signal MSEL indicates an operation mode for a high speed operation, the ODT circuit (ODT) according to the ODT selection signals ODSEL1 to ODSELn and OSSEL1 to OSSELn output from the interface control circuit 166. 164 may be terminated to ground voltage level VSSQ. That is, only some of the switches SWS1 to SWSn may be turned on.

According to another embodiment, when the mode selection signal MSEL indicates an operation mode for low speed operation, the ODT circuit according to the ODT selection signals ODSEL1 to ODSELn and OSSEL1 to OSSELn output from the interface control circuit 166. 164 may be terminated to the power supply voltage level VDDQ. That is, only some of the switches SWD1 to SWDn may be turned on.

According to another embodiment, when the mode selection signal MSEL indicates an operation mode for low speed operation, the ODT according to the ODT selection signals ODSEL1 to ODSELn and OSSEL1 to OSSELn output from the interface control circuit 166. The switches SWD1 to SWDn and SWS1 to SWSn of the circuit 164 may all be turned off. That is, the termination resistor 184 may not be used in the operation mode for low speed operation.

According to another embodiment, some of the switches SWD1 to SWDn and some of the switches SWS1 to SWSn may be turned on together, in which case the ODT circuit 164 may be switched to center tap termination (CTT). Can be implemented.

FIG. 14 is a block diagram according to another exemplary embodiment of the first input / output interface illustrated in FIG. 2.

2, 4, and 14, the first input / output interface 120B according to another embodiment of the first input / output interface 120 illustrated in FIG. 2 may include an output driver block 160 of FIG. 4 and an ODT. The circuit 164 of FIG. 4 may be implemented with an output driver and an ODT block 160 ′ of FIG. 14.

The output driver and the ODT block 160 'operate like the output driver block 160 when the memory device 100 outputs a data signal, and when the memory device 100 receives a data signal, the output driver and the ODT block 160' 164).

That is, the first input / output interface 120B may use the output driver as the ODT circuit without including the separate ODT circuit 164 as shown in FIG. 4.

15 is a flowchart illustrating a method of operating an input / output interface according to an embodiment of the present invention.

4 through 6 and 15, the output driver block 160A or 160B may include a plurality of output driver circuits 160A-2 and 160A-3 or 160B included in the output driver block 160A or 160B. Any one of -2 and 160B-3) may be selected (S10).

According to an embodiment, the output driver block 160A or 160B may be configured according to the output driver selection signals TXSEL1 to TXSEL4 generated by the interface control circuit 166 based on the mode selection signal MSEL. The output driver circuit 160A-2 or 160A-3, 160B-2 or 160B-3 can be selected.

The output driver block 160A or 160B may output the data signal DOUT1 or DOUT2 using the selected output driver circuit 160A-2 160A-3, 160B-2, or 160B-3 (S12).

16 is a flowchart illustrating a method of operating an input / output interface according to another embodiment of the present invention.

7 and 16, the input receiver block 162 may select any one of the plurality of input receiver circuits 170, 172, and 174 included in the input receiver block 162 (S20).

According to an embodiment, the input receiver block 162 according to the input receiver selection signals RXSEL1 to RXSEL3 generated by the interface control circuit 166 based on the mode selection signal MSEL, may be any one of the input receivers. Circuit 170, 172, or 174 can be selected.

The input receiver block 162 may receive the data signals RO1 to RO3 using the selected input receiver circuit 170, 172, or 174 (S22).

17 is a conceptual diagram illustrating an embodiment of a package including the memory device shown in FIG. 1.

1 and 17, the package 300 may include a plurality of semiconductor devices 330, 340, and 350 sequentially stacked on the package substrate 310. Each of the plurality of semiconductor devices 330 to 350 may be a memory device 100.

The package 300 includes Package On Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Chip On Board (COB) , CERamic Dual In-Line Package (CERDIP), plastic metric quad flat pack (MQFP), Thin Quad Flat Pack (TQFP), small-outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline ), A system in package (SIP), a multi chip package (MCP), a wafer-level package (WLP), a wafer-level processed stack package (WSP), or the like.

According to an embodiment, the memory controller (not shown) may be implemented in one or more semiconductor devices among the plurality of semiconductor devices 330 to 350 or on the package substrate 310.

For electrical connection between the plurality of semiconductor devices 330 to 350, electrical vertical connection means (eg, through-silicon via) may be used.

The package 300 may be implemented as a hybrid memory cube (“HMC”) in which a memory controller and a memory cell array die are stacked. Implementing with HMC can reduce power consumption and production costs by improving memory device performance due to increased bandwidth and minimizing the footprint of the memory device.

FIG. 18 is a conceptual diagram three-dimensionally illustrating an embodiment of a package including the memory device shown in FIG. 1.

1, 17, and 18, the package 300 ′ includes a plurality of dies 330-350 of a stacked structure connected to each other through each TSV 360.

FIG. 19 is a block diagram illustrating a system-in-package and a nonvolatile memory device including the memory system illustrated in FIG. 1. 20 is a block diagram according to another exemplary embodiment of a system-in-package including the memory system illustrated in FIG. 1.

1 and 19, the SoC 200 and the memory device 100, such as main memory, may be packaged in a system-in package (SiP) 250.

The SoC 200 may be connected to a non-volatile memory device 400.

According to an embodiment, the nonvolatile memory device 200 may include electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM (MRAM), spin-transfer torque MRAM (MRAM), and conductive. bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM (PoRAM), nano floating gate memory may be implemented as nano floating gate memory (NFGM), holographic memory, molecular electronics memory device, or insulation resistance change memory, but the scope of the present invention is It is not limited to this.

1 and 20, the memory device 100, the SoC 200, and the nonvolatile memory device 400 may be packaged as a SiP 250 ′.

FIG. 21 is a block diagram illustrating a memory system including the memory device illustrated in FIG. 1.

1 and 21, the memory system 500 may be implemented as a personal computer (PC), a tablet PC, or a mobile computing device.

The memory system 500 includes a main memory module 540 through a main board 540, a slot 520 mounted to the main board 540, a memory module 510 that can be inserted into the slot 520, and a slot 520. Chipset 530 capable of controlling operations of the plurality of memory devices 100-100-m mounted in the 510, and a processor 550 for communicating with the plurality of memory devices 100-1-100-m. )

Each of the plurality of memory devices 100-1 to 100-m may be the memory device 100 illustrated in FIG. 1.

In FIG. 21, only one memory module 510 is illustrated for convenience of description, but the memory system 500 includes at least one memory module.

The chipset 530 is used to exchange data, address, or control signals between the processor 550 and the memory module 510.

The chipset 530 includes a memory controller 535 for controlling the plurality of memory devices 100-1 to 100-m.

FIG. 22 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.

1 and 22, the system 600 may be implemented as an electronic device or a portable device. The portable device may be implemented as a cellular phone, a smart phone, or a tablet PC.

System 600 includes a processor 611 and a memory device 613. The memory device 613 may be the memory device 100 of FIG. 1.

According to an embodiment, the processor 611 and the memory device 613 may be packaged in a package 610. In this case, the package 610 may be mounted on a system board (not shown). The package 610 may refer to the package 300 shown in FIG. 17 or the package 300 ′ shown in FIG. 18.

The processor 611 includes a memory controller 615 that can control a data processing operation of the memory device 613, for example, a write operation or a read operation. The memory controller 615 is controlled by a processor 611 that controls the overall operation of the system 600. In some embodiments, the memory controller 615 may be connected between the processor 611 and the memory device 613.

Data stored in the memory device 613 may be displayed through the display 620 under the control of the processor 611.

The radio transceiver 630 may transmit or receive a radio signal through the antenna ANT. For example, the radio transceiver 630 may convert a radio signal received through the antenna ANT into a signal that can be processed by the processor 611. Accordingly, the processor 611 may process a signal output from the wireless transceiver 630, and store the processed signal in the memory device 613 or display it through the display 620.

The radio transceiver 630 may convert a signal output from the processor 611 into a radio signal and output the converted radio signal to the outside through the antenna ANT.

The input device 640 may input a control signal for controlling the operation of the processor 611 or data to be processed by the processor 611. The input device 640 may include a touch pad and a computer mouse. The same may be implemented with a pointing device, a keypad, or a keyboard.

The processor 611 displays the display 620 such that data output from the memory device 613, wireless signal output from the wireless transceiver 630, or data output from the input device 640 may be displayed through the display 620. ) Can be controlled.

FIG. 23 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.

1 and 23, the system 700 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA). , A portable multimedia player (PMP), an MP3 player, or an MP4 player.

The system 700 includes a processor 711 and a memory device 713 for controlling the overall operation of the system 700. The memory device 713 may refer to the memory device 100 illustrated in FIG. 1.

According to an embodiment, the processor 711 and the memory device 713 may be packaged in a package 710. The package 710 may be mounted on a system board (not shown). The package 710 may refer to the package 300 shown in FIG. 17 or the package 300 ′ shown in FIG. 18.

The processor 711 may include a memory controller 715 for controlling the operation of the memory device 713.

The processor 711 may display data stored in the memory device 713 through the display 730 according to an input signal generated by the input device 720. For example, the input device 720 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

FIG. 24 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.

1 and 24, the system 800 may be implemented as a digital camera or a portable device to which a digital camera is attached.

System 800 includes a processor 811 and a memory device 813 that control the overall operation of system 800. In this case, the memory device 813 may refer to the memory device 100 illustrated in FIG. 1.

The processor 811 may include a memory controller 815 that controls an operation of the memory device 813.

According to an embodiment, the processor 811 and the memory device 813 may be packaged in a package 810. The package 810 may be mounted on a system board (not shown). The package 810 may refer to the package 300 shown in FIG. 17 or the package 300 ′ shown in FIG. 18.

The image sensor 820 of the system 800 converts the optical image into a digital signal, which is stored in the memory device 813 or displayed through the display 830 under the control of the processor 811. In addition, the digital signal stored in the memory device 813 is displayed through the display 830 under the control of the processor 811.

FIG. 25 is a block diagram illustrating another example embodiment of a memory system including the memory device illustrated in FIG. 1.

Channel 901 may mean optical connection means. The optical connecting means may mean an optical fiber, an optical waveguide, or a medium for transmitting an optical signal.

1 and 25, the system 900 may include a first system 1000 and a second system 1100.

The first system 1000 may include a first memory device 100a and an all-optical conversion circuit 1010. The all-optical converting circuit 1010 may convert the electrical signal output from the first memory device 100a into an optical signal, and output the converted optical signal to the second system 1100 through the optical connection unit 901. .

The second system 1100 includes a photoelectric conversion circuit 1120 and a second memory device 100b. The photoelectric conversion circuit 1120 may convert the optical signal input through the optical connection unit 901 into an electrical signal and transmit the converted electrical signal to the second memory device 100b.

The first system 1000 may further include a photoelectric conversion circuit 1020, and the second system 1100 may further include an all-optical conversion circuit 1110.

When the second system 1100 transmits data to the first system 1000, the all-optical conversion circuit 1110 converts the electrical signal output from the second memory device 100b into an optical signal and converts the converted optical signal. The optical system may be output to the first system 1000 through the optical connection means 901. The photoelectric conversion circuit 1020 may convert an optical signal input through the optical connection unit 901 into an electrical signal and transmit the converted electrical signal to the first memory device 100a. The structure and operation of each memory device 100a and 100b are substantially the same as the structure and operation of the memory device 100 of FIG. 1.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

10: memory system
100: memory device
110, 210: internal circuit
120, 220: input / output interface
160: output driver block
162: input receiver block
164: on-die termination circuit
166: interface control circuit
200: system on chip

Claims (10)

Selecting one of the plurality of output driver circuits according to the mode selection signal; And
Outputting a data signal using any one of the selected output driver circuits,
The plurality of output driver circuits include a first output driver circuit including an NMOS pull-up transistor and a second output driver circuit including a PMOS pull-up transistor, wherein the first output driver circuit and the second output driver circuit are included. The output driver circuit is selected exclusively,
The first output driver circuit is selected when the mode selection signal indicates an operation mode for high speed operation, and the second output driver circuit is selected when the mode selection signal indicates an operation mode for low speed operation How the interface works. The method of claim 1, wherein the mode selection signal,
A method of operating an input / output interface, which is a control signal for controlling an on-die termination circuit included in the input / output interface. The method of claim 1, wherein prior to said selecting,
And generating the mode selection signal according to a memory latency. The method of claim 3, wherein the memory latency is
Operation method of input / output interface which is read latency or write latency. The method of claim 1, wherein prior to said selecting,
And generating the mode selection signal based on a mode register set (MRS) command for adjusting an operating frequency. delete The method of claim 1,
And selecting one of a plurality of termination levels of an ODT circuit included in the input / output interface according to the mode selection signal. The method of claim 7, wherein
And the plurality of termination levels includes a power supply voltage level, a ground level, and an intermediate level between the power supply voltage level and the ground level. Selecting one of the plurality of input receiver circuits according to the mode selection signal; And
Receiving a data signal using any one input receiver circuit selected;
The plurality of input receiver circuits include a first input receiver circuit including a PMOS type differential amplifier and a second input receiver circuit including an NMOS type differential amplifier, wherein the first input receiver circuit and the second input receiver The circuit is selected exclusively,
The first input receiver circuit is selected when the mode selection signal indicates an operation mode for high speed operation, and the second input receiver circuit is selected when the mode selection signal indicates an operation mode for low speed operation How the interface works. The method of claim 9, wherein the mode selection signal,
A method of operating an input / output interface, which is a control signal for controlling an on-die termination circuit included in the input / output interface.

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