KR102025026B1 - Method and system for converting LVDS video signal to DP video signal - Google Patents

Abstract

The present invention relates to a method for converting an LVDS video signal into a DP video signal, the method comprising: receiving and demodulating an LVDS video signal to generate demodulated data and an LVDS pixel clock in LVDS parallel; Generating LVDS image source data and an LVDS image source synchronization signal by performing image decoding on the demodulated data in parallel with the LVDS image decoding control signal; Generating the corresponding RGB image pixel clock by converting the LVDS image source data and the LVDS image source synchronization signal into an RGB image signal according to an LVDS image conversion control signal and performing a frequency multiplication operation corresponding to the LVDS pixel clock; ; And converting the RGB image signal into a DP image signal after a DP image conversion start command is received. The present invention can detect the quality of LVDS video signal and the validity of image data, has high reliability, excludes false judgment, and features simple operation, high detection efficiency and low cost.

Description

Method and system for converting LVDS video signal to DP video signal

The present invention relates to the generation of DP image signals, and more particularly, to a method and system for converting LVDS image signals belonging to the field of display and test of a liquid crystal module into DP image signals.

A liquid crystal display module (hereinafter referred to as a liquid crystal module) is a key component that a liquid crystal display device can display normally, and is composed of a liquid crystal display, a backlight component, a display processing chip, and a circuit. Liquid crystal modules have precision structures, complex manufacturing processes, and demanding manufacturing processes. In order to secure production yield, it is necessary to produce a variety of test video signals through a special liquid crystal module test apparatus, and the test video signals are input to the liquid crystal module for display to test strict and comprehensive display effects. Currently, the display interface and internal display processing circuits of general liquid crystal modules used in TVs and display products operate using low-voltage differential signaling (LVDS) signals, but conventional liquid crystal module test devices use LVDS imaging to test the module. Module test equipment is also widely used because it outputs signals and general liquid crystal modules have long production times and have amazing output levels.

However, as people continue to pursue higher clarity and more realistic display effects on liquid crystal display modules, and the demand for bandwidth transmission increases significantly, the number of LVDS lines used to support these bandwidths has increased significantly, leading to TV producers' high production. The cost and complexity has been incurred, so that conventional liquid crystal modules cannot gradually meet these requirements. As a result, new high-resolution and ultra-high density liquid crystal modules exist to meet people's needs.These liquid crystal modules have a DP signal interface (DisplayPort display) with faster transmission speed, longer transmission distance, better EMI compatibility, and better price. Interface), and in this way, the liquid crystal module having the DP interface became a trend.

However, although the test apparatus of the DP liquid crystal module needs to output the same DP test signal, the existing conventional liquid crystal module test apparatus does not have this function, and the normal liquid crystal module is continuously manufactured, and the test apparatus is It continues to be used without entering the replacement cycle. Module manufacturers also produce DP liquid crystal modules, but do not repurchase expensive, dedicated test equipment for DP modules without removing existing equipment to protect investments and reduce production costs. In order to manufacture a large amount of DP liquid crystal modules at low cost in a short time and to secure a yield, it is possible to reuse the existing common module test apparatus on a large scale.

Therefore, it is necessary to develop a conversion device capable of converting LVDS video signals into DP video signals, and the general liquid crystal module test device can test the DP module through the conversion device, while at the same time the conversion device is reliable, integrated and Not only is it efficient, it is inexpensive and easy to operate.

The present invention is directed to overcoming the drawbacks of the prior art described above and to providing a method and system for converting an LVDS video signal into a DP video signal. The present invention is characterized by being capable of detecting the quality of LVDS video signals and the validity of image data, having high reliability, reducing false positives, and having simple operation, high detection efficiency and low cost.

One technical solution for achieving the object of the present invention is a method for converting an LVDS video signal into a DP video signal, which method transmits the LVDS video signal in one of a single LINK mode, a dual LINK mode, and a quad LINK mode. Converting into an RGB image signal; Controlling configuration and conversion for DP conversion according to a DP conversion configuration command and a DP conversion start command.

The present invention also provides a system for converting an LVDS video signal into a DP video signal, the system comprising: an LVDS video signal conversion unit for converting an LVDS video signal into an RGB video signal; And a DP image signal conversion unit for controlling configuration and conversion for DP conversion according to a DP conversion configuration command and a DP conversion start command.

The present invention also provides a method for converting an LVDS video signal into a DP video signal, the method comprising: converting an LVDS video signal into an RGB video signal; Outputting the processed signal after performing buffering and frequency multiplication processing on the RGB image signal; And performing a configuration and conversion for DP conversion on the output frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a DP image signal.

The present invention also provides a system for converting an LVDS video signal into a DP video signal, the system comprising: an LVDS video signal conversion unit for converting an LVDS video signal into an RGB video signal; A buffering and frequency multiplication unit configured to output a processed signal after performing buffering and frequency multiplication processing on the RGB image signal; And a DP image signal conversion unit configured to perform DP configuration and conversion on the output frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a DP image signal.

The present invention has the following advantages.

(1) The present invention can detect 1, lane, and 4 lane DP image signals generated from an image source. After setting, the present invention can be well adapted to different DP transmission characteristics and different characteristics such as color scale, transmission mode, coding scheme of video signal.

(2) The present invention can detect electrical characteristics of a DP video signal generated from an image source, obtain a detection result after comparison in the present invention by inputting a DP electrical parameter standard, and output the detection result to a display. Can be.

(3) The present invention detects image data of a DP video signal generated from an image source, pre-caches the image data of each frame, and compares it with the original video image to verify that each pixel is output correctly. Can be determined. Each frame image can be detected.

(4) The present invention can detect high DP image resolution, has high integration, reliable operation, strong anti-interference ability, and also has advantages of simple operation, economical and practicality. The present invention can improve the detection reliability and efficiency of the DP liquid crystal module, can reduce the device cost and manufacturing cost, as well as further improve the popularity of the related display device.

(5) The present invention can realize all functions using a field programmable gate array (FPGA) chip, a double date rate (DDR) memory chip, and an analog / digital (A / D) conversion chip. These devices are common chips that are stable and easy to implement, and also avoid problems such as cheap, complex designs, poor stability, and high design costs due to the use of various specialized chips.

(6) The data rate of each channel of the present invention is doubled to 5.4Gbps and the total bandwidth is up to 21.6Gbps, which greatly improves the display resolution (up to 3840x2160 @ 60hz), color depth, refresh rate and multi-display capability. .

(7) The present invention supports multiple streams and can transmit multiple independent and uncompressed video and audio streams using only data lines.

(8) The present invention supports bidirectional data transmission, and can transmit USB2.0 or Ethernet data on a standard DP data line.

(9) The present invention supports a daisy chain link and allows a DP input display device to copy input data and then output it to another display device through another DP.

1 is a block diagram of an apparatus for converting an LVDS video signal into a DP video signal according to an embodiment of the present invention.
FIG. 2 is a circuit block diagram of the LVDS video signal receiving unit and LVDS video signal decoding unit of FIG. 1.
3 is a circuit block diagram of the RGB image signal conversion unit, DP image signal conversion unit, and image conversion configuration unit of FIG.
4 is a flowchart illustrating a method of converting an LVDS video signal into a DP video signal according to an embodiment of the present invention.
5 is a block diagram of a system for converting an LVDS video signal into a DP1.2 video signal according to another embodiment of the present invention.

The invention will now be described in more detail with reference to the accompanying drawings and specific examples.

<Example 1>

1 to 3, a system for converting an LVDS video signal into a DP video signal according to the present embodiment includes an LVDS video signal converting unit, a DP video signal converting unit 4, and a LVDS video signal converting the LVDS video signal into an RGB video signal; And an image conversion configuration unit 5. The LVDS video signal conversion unit includes an LVDS video signal receiving unit 1, an LVDS video signal decoding unit 2, and; An RGB video signal conversion unit 3 is included.

The operation process of the system for converting an LVDS video signal into a DP video signal is shown in FIG. 4 and includes the following specific steps.

In S100, the LVDS video signal receiving unit 1 receives the LVDS video signal, demodulates the received LVDS video signal to generate the demodulated data and the LVDS pixel clock in LVDS parallel. The LVDS video signal receiving unit 1 of this embodiment includes an LVDS video signal interface 1-1, an LVDS video signal termination block 1-2, an LVDS clock signal demodulation block 1-3, and an LVDS data signal demodulation block ( 1-4) and LVDS demodulation dynamic correction block 1-5. The LVDS video signal termination block 1-2 is connected to the LVDS video signal interface 1-1, and the LVDS clock signal demodulation block 1-3 and the LVDS data signal demodulation block 1-3 are respectively LVDS video signals. And an LVDS demodulation dynamic correction block 1-5 are connected to an LVDS clock signal demodulation block 1-3 and an LVDS data signal demodulation block 1-4, respectively. Detailed description of each block is as follows.

The LVDS video signal interface 1-1 receives an LVDS video signal, and the LVDS video signal includes LVDS video signals on one LINK, two LINKs, and four LINKs. LVDS video signal on one LINK means that LINK 1 transmits all video pixels; LVDS video signals on two LINKs represent two links, LINK 1 and LINK 2, which transmit odd and even video pixels, respectively. The LVDS image signals on the four LINKs mean four links that sequentially transmit the image pixels to the LINK 1, LINK 2, LINK 3, and LINK 4 in the order of the image pixels. The DP video signal of this embodiment includes a 1 lane type, a 2 lane type, and a 4 lane type DP display module. When the DP video signal to be converted is output to a 4 LANE single full-screen type DP display module, the LVDS video signal is transmitted in one of the single LINK mode, the dual LINK mode and the quad LINK mode; When the DP video signal to be converted is output to a DP liquid crystal display module of 8 LANE left and right split-screen type or 8 LANE odd and even split-screen type, the LVDS video signal is transmitted only in the quad LINK mode. The LVDS video signal for each link includes an LVDS receive clock and LVDS data. LVDS data is transmitted over the LVDS data bus. The LVDS data bus contains several signal lines, each carrying a serial code signal. The LVDS video signal interface 1-1 is connected to the LVDS transmission line interface and inputs an LVDS video signal. The interface includes two input connectors, namely an industrial standard horn connector and a small high density commercial connector, to allow the present embodiment to be applied to industrial and commercial environments. If one connector has an LVDS signal input, the interface can automatically output the signal from the corresponding connector. If both connectors have a signal input, the interface basically outputs the signal from a small high density commercial connector.

After the LVDS video signal termination block 1-2 performs a termination operation on the LVDS video signal received by the LVDS video signal interface 1-1, the LVDS video signal termination block 1-2 receives the LVDS reception clock and the LVDS data, respectively. 1-3) and the LVDS data signal demodulation block (1-4). Termination operations include LVDS termination resistor matching, LVDS signal level matching, LVDS signal equalization and de-emphasizing, signal buffering, and reconstruction, ensuring signal quality of the received LVDS signal while distorting the signal due to long-distance transmission. And compensate for attenuation, and reduce transmission interference. Termination is performed by electrostatic discharge (ESD) protection before receiving the LVDS signal to eliminate shock waves caused by instantaneous strong discharges, and then by performing common mode noise filtering to suppress transmission line noise and to resist electromagnetic interference. To improve. While receiving a signal, a termination impedance matching process is performed to remove distortion caused by signal transmission, and further interference of the signal is further removed. The signal is equalized and de-emphasizing process to remove signal attenuation due to transmission loss. The signal is then buffered and amplified and then judged to a reference level to produce a high quality LVDS video signal.

The LVDS clock signal demodulation block 1-3 demodulates the LVDS receive clock received at each LINK to generate a demodulation clock and a demodulation enable signal. The demodulation process inputs the LVDS receive clock into a phase locked loop (PLL) through a high-speed IO buffer to multiply the frequency of the LVDS receive clock by the LVDS data signal frequency, and performs a fast clock conversion process to perform the same as LVDS data. Produces LVDS demodulation strobe signal with frequency equal to LVDS demodulation clock and LVDS pixel clock and LVDS receive clock, and outputs signals and data to high speed clock network with very low delay, jitter and strong driving capability. Ensure stable and reliable demodulation in LVDS data. Once the LVDS receive clock is multiplied by the PLL, the clock from the LVDS demodulation dynamic correction block (1-5) de-jitters the correction signal and is also input to the PLL to provide anti-jitter control for operation. Anti-jitter control is performed to create a stable frequency multiply signal that is not affected by input jitter, ensuring that the demodulation operation is uninterrupted and error free.

The LVDS data signal demodulation block 1-4 demodulates the LVDS data of the corresponding LINK into parallel data by the demodulation clock and the demodulation enable signal of each LINK, and the LVDS receiving clock is demodulated simultaneously by the LVDS pixel clock. The process demodulates each bit of data on the LVDS serial data bus independently of each other. Since each bit of the LVDS data signal is buffered into a low-delay, low-jitter high-speed signal network and then delayed by half the period of the data bit, the data value can be accurately sampled at the center of each LVDS data bit by the LVDS demodulation clock, It is periodically truncated into serialized data according to the demodulation strobe signal, and then processed using a LVDS video source pixel clock to process serial-to-parallel conversion to obtain demodulated data in parallel of this bit LVDS signal output by the trigger buffer. To ensure that the signal is stable and reliable. Each LVDS signal line is synchronously demodulated in parallel, and a demodulation error occurs regardless of what happens to the data without all the signal lines interfering with each other.

When sampling the bit values of LVDS data by the LVDS demodulation clock, the data from the LVDS demodulation dynamic correction block (1-5) de-jitters the correction signal and at the same time is stable from input jitter. Perform anti-jitter control on the operation to generate reliable and demodulated data.

The phase delay processing of the data input is always controlled by the LVDS data stream phase correction signal of the LVDS demodulation dynamic correction block 1-5. If the demodulation clock and the LVDS data are out of phase, the phase correction signal is delay adjusted as opposed to the phase deviation based on the half cycle delayed data, so that the data center is always aligned with the sampling edge of the demodulation clock to ensure that the data is sampled correctly.

The demodulation strobe signal is controlled by the bit shift correction signal of the LVDS demodulation dynamic correction block 1-5 used for byte alignment demodulation while cutting the serial data so that the start bit of the divided parallel data moves to the next serial bit.

The LVDS demodulation dynamic correction block 1-5 performs dynamic correction on the serialized signal of the LVDS receive clock and LVDS data, respectively, in real time during the demodulation process.

S200, the LVDS video signal decoding unit 2 video-decodes the demodulated data in parallel with the LVDS in accordance with the LVDS video decoding control signal to generate the LVDS video source data and the LVDS video source synchronization signal. The LVDS video signal decoding unit 2 of the present embodiment includes an LVDS video synchronization and buffering block 2-1, an LVDS video signal sequencing block 2-2, an LVDS video synchronization signal decoding block 2-3, and LVDS video data. Decoding block 2-4. Detailed description of each block is as follows.

The LVDS image synchronization and buffering block (2-1) converts the LVDS pixel clock of LINK 1 to an LVDS image source pixel clock through the global clock path, and the data demodulated in parallel with each LVDS uses the input LVDS pixel clock of each LINK. Are written to DC-FIFO (First Input First Output) for caching, and are read one by one using the LVDS video source pixel clock, thus creating synchronization data to prevent read errors caused by delay mismatch between signals during transmission. . The cache depth is as large as possible so that all LINKs have enough data to be cached to offset the maximum delay between them.

Upon receiving the LVDS odd and even pixel inversion-control signals, the LVDS video signal sequencing block 2-2 exchanges data at LINK 1 and LINK 2 of the two links, and upon receiving the LVDS video signal sequential-control signal, Arrange the four links in the order of LINK 1, LINK 2, LINK 3, and LINK 4.

The LVDS video synchronizing signal decoding unit 2-3 converts the data demodulated in parallel to the LVDS of each LINK of the LINKs read synchronously according to the LVDS video decoding control signal received from the video converting configuration unit 5 into the LVDS video source synchronizing signal. Decode; LVDS video decoding control signals are ordered in sequential logic mode using LVDS video source pixel clock according to VESA and JEIDA transmission coding standards, then LINK 1 is decoded to recover LVDS video source sync signal, and then the signal The synchronization signal includes an image horizontal row synchronization signal Hsync, an image vertical field synchronization signal Vsync, and an image data valid signal DE.

The LVDS image data decoding block 2-4 decodes the demodulated data in parallel with the LVDS of each LINK read synchronously according to the LVDS image decoding control signal received from the image conversion configuration unit 5, and the LVDS of each LINK. The image source data signal is decoded.

S300, the RGB video signal conversion unit 3 converts the LVDS video source data and the LVDS video source synchronization signal into an RGB video signal according to the LVDS video conversion control signal, and converts the DP video conversion start signal after the conversion is completed to the video conversion configuration unit. Transfer to (5). The RGB image signal conversion unit 3 of the present embodiment includes an RGB image signal adaptation control block 3-1, an RGB image clock adaptation configuration block 3-2, an RGB image clock generation block 3-3, and an RGB image clock. Output Modification Block (3-4), Single Link Mode RGB Image Conversion Block (3-5), Dual Link Mode RGB Image Conversion Block (3-6), Quad Link Mode RGB Image Conversion Block (3-7), Left and Right split-screen mode RGB image conversion block 3-8, odd and even split-screen mode RGB image conversion block 3-9 and RGB video signal output block 3-10. The detailed description of each block is as follows.

The RGB video signal adaptive control block 3-1 generates a matched RGB video clock configuration signal in one of the single LINK mode, the dual LINK mode, and the quad LINK mode according to the LVDS video conversion control signal, and generates the RGB video clock configuration. Send the signal along with the LVDS image source pixel clock to the RGB image clock adaptive configuration block 3-2; A RGB conversion block selection signal is generated according to the LVDS image conversion control signal, and the RGB conversion block selection signal is converted into a single link mode RGB image conversion block together with an LVDS image source data signal and an LVDS image source synchronization signal and an RGB image clock of each link. (3-5), dual link mode RGB image conversion block (3-6), quad link mode RGB image conversion block (3-7), left and right split-screen mode RGB image conversion block (3-8), odd And transmit to the even-split-screen mode RGB image conversion block (3-9), detect the LVDS image synchronization signal to calculate the horizontal resolution value, and convert the horizontal resolution value to the single link mode RGB image conversion block (3-5). send.

The RGB image clock adaptation configuration block 3-2 comprises a single LINK mode, a dual LINK mode and a single LINK mode by the local clock signal according to the generated RGB image clock configuration signal of any one of the single LINK mode, the dual LINK mode and the quad LINK mode. A corresponding configuration parameter and a configuration enable signal of any one of the quadruple LINK modes are generated to perform a dynamic reconfiguration operation on the clock generation block. The RGB image clock generation block 3-3 generates an RGB image clock in accordance with the configuration clock and the enable signal, and converts the RGB image clock into an RGB image signal adaptive control block 3-1 and an RGB image clock output modification block 3. -4). The PLL is reconstructed using the PLL configuration parameters according to the dynamic reconstruction timing, allowing the frequency multiplication process to be performed on the LVDS pixel clock. When configured in a single LINK mode, the LVDS image source pixel clock is converted to an RGB image pixel clock (hereinafter referred to as an RGB clock) of the same frequency; When configured in the dual LINK mode, the LVDS image source pixel clock is converted to a double frequency RGB image pixel clock; When configured in quad LINK mode, the LVDS image source pixel clock is converted to a four times frequency RGB image pixel clock (each of the four LINKs transmits a quarter image of the full screen). When the RGB video signal is converted according to the left and right split-screen mode or odd and even split-screen mode in the quadrature LINK mode, the LVDS image source pixel clock is converted to its double frequency RGB image pixel clock. The resulting frequency multiplied signal is then phased to have exactly the same phase as the LVDS pixel clock (ensures that the LVDS data can be sampled accurately and reliably during subsequent sequential logic operations of the conversion process) and jitter processing And then enter a stable non-wobbling global clock path to generate an RGB image clock.

Since the RGB image source data signal is synchronized with the RGB image clock, the RGB image clock output modification block 3-4 delays the phase of the input RGB image clock by half clock cycles, and the RGB image clock after the phase delay is the RGB output clock. Acting as a signal and activating the effective edges can be at the center of the RGB image source data, so that the RGB data can be accurately sampled by the clock in subsequent conversion operations, and then the signal is de-jittered (de A jitter process and output through the high speed image buffering component to the RGB image signal output block 3-10 ensures that the output clock has higher stability and better signal quality.

LVDS image source sync signals and data are converted to RGB image sync signals and data using an RGB clock; When the DP liquid crystal display module is of 4 LANE full-screen type, LVDS image conversion of single LINK mode, dual LINK mode and quad LINK mode is performed separately according to the LINK conversion mode control signal; When the DP display block is of 8 LANE split-screen type, image conversion of the left and right split screen mode and odd and even split-screen mode is performed separately according to the conversion control signal.

The single link mode RGB image conversion block (3-5) converts the LVDS image source synchronization signal and LVDS image source data on the single link into an RGB image signal, and transmits the RGB image signal to the RGB image signal output block (3-10). do.

The dual link mode RGB image conversion block 3-6 converts the LVDS image source synchronization signal and LVDS image source data on the dual LINK into an RGB image signal and transmits the RGB image signal to the RGB image signal output block 3-10. .

The quad link mode RGB image conversion block 3-7 converts the LVDS image source synchronization signal and the LVDS image source data on the quad LINK into an RGB image signal and transmits the RGB image signal to the RGB image signal output block 3-10. ;

The left and right split-screen mode RGB image conversion blocks 3-8 convert the LVDS image source synchronization signal and LVDS image source data on the quad LINK into a left half screen RGB video signal and a right half screen RGB video signal, The signal is transmitted to the RGB video signal output block 3-10. The image conversion processing for performing the left and right split-screen modes is as follows. The left and right split-screen mode RGB image conversion blocks 3-8 generate LVDS data for four LINKs forming parallel data in the form of "LINK 1, LINK 2, LINK 3, LINK 4", Determine when the first complete image line begins according to the input LVDS sync signal, and sample the front and back half of the LINK parallel data using the LVDS clock according to the obtained line resolution value, each cache data being dual frequency RGB The sampled data is written to the left and right half screen DC-FIFOs for caching, respectively, while being read simultaneously using an image clock, separated into left half screen RGB data, right half screen RGB data and sync signal, and left Forming a half screen RGB video signal and a right half screen RGB video signal; Since the throughput of the data read and write operations is the same as the throughput of the read and write operations of the synchronization signal, the conversion operation can be performed continuously and stably.

The odd and even split-screen mode RGB image conversion block 3-9 converts the LVDS image source synchronization signal and LVDS image source data on the four LINKs into an odd pixel RGB image signal and an even pixel RGB image signal, and converts the RGB image. The signals are sent to the RGB image signal output block 3-10; The image conversion processing for performing the odd and even split-screen mode is as follows: The odd and even split-screen mode RGB image conversion block 3-9 is composed of two odd pixels LINK and 2 out of four LINK LVDS data. The first even pixel LINKs are first detected, and then the LVDS synchronization signal, the two odd and two even LINK data are composed of parallel data, and the parallel data is odd pixel and even pixel RGB image data, and odd pixel RGB image signal. And according to the dual LINK mode conversion method to generate an RGB synchronization signal forming an even pixel RGB video signal.

The RGB video signal output block 3-10 selects the corresponding RGB video signal in accordance with the RGB conversion block selection signal and transfers the RGB video signal to the DP video signal conversion unit 4 together with the RGB output clock. When synchronous mode control is generated, the video synchronous signal operates in the reverse direction; The phase is compared between the effective edge of the RGB output clock and the sampling center of the RGB data, and the output clock and data are subjected to fine delay processing by the signal delay component to eliminate the phase difference therebetween, so that the output clock is always at the sampling center of the data. To ensure that.

S400, after the image conversion configuration unit 5 receives the DP image conversion start command, the DP image signal conversion unit 4 converts the RGB image signal into a DP image signal and transmits the DP image signal to the DP display module. The DP video signal conversion unit 4 of this embodiment includes a DP register block 4-1, a left DP video signal conversion block 4-2, a right DP video signal conversion block 4-3, and a DP liquid crystal display module connector. (4-4), the detailed description of each block is as follows.

The DP register block 4-1 controls the left DP video signal conversion block 4-2 and the right DP video signal conversion block 4-3 according to the recorded DP register command, and configures and operates for DP conversion. At the same time. The DP register command includes a DP conversion configuration command and a DP conversion start command.

The left DP video signal conversion block 4-2 receives an RGB video signal, performs a configuration and conversion operation of converting an RGB video signal into a left channel DP video signal, and converts the converted left channel DP video signal into a DP liquid crystal display. When transferring to the module connector 4-4 and a DP conversion configuration command is received from the DP register configuration block 4-1, the corresponding configuration and conversion operation is completed, and the DP register block 4-1 is displayed in the DP display. Upon receiving the module initialization command, the DP display module initialization command is sent to the DP display module via the DP liquid crystal display module connector 4-4; When the DP conversion start command is received from the DP register block 4-1, the conversion operation is started.

The right DP video signal conversion unit 4-3 receives the RGB video signal, performs the configuration and conversion operation of converting the RGB video signal into the right channel DP video signal, and converts the converted right channel DP video signal into the DP liquid crystal display. When transferring to the module connector 4-4 and the DP conversion configuration command is received from the DP register block 4-1, the corresponding configuration and conversion operation is completed, and the DP register block 4-1 is the DP display module. Upon receiving the initialization command, the DP display module initialization command is sent to the DP display module via the DP liquid crystal display module connector 4-4; When the DP conversion start command is received from the DP register block 4-1, the conversion operation is started.

When the conversion block selection signal is in the single, double or quad LINK mode, its RGB data and synchronization signal (full screen signal) are copied to two paths output to the DP video signal conversion unit 4; When the left and right split-screen conversion modes are selected, the left half and right half in the left DP video signal conversion block 4-2 and the right DP video signal conversion block 4-3 are left in accordance with the screen data and the synchronization signal. A half screen RGB video signal and a right half screen RGB video signal are output, respectively; When the odd and even divisional-screen conversion mode is selected, the RGB odd-division-screen video signal and the RGB even-division-screen video signal are sent to the DP video signal conversion unit 4 according to the odd pixel parallel data, the even pixel parallel data and the synchronization signal. Are output respectively.

The DP liquid crystal display module connector 4-4 simultaneously receives the left channel DP video signal and the right channel DP video signal, and is connected to the DP display module 6 to DP display the left channel DP video signal and the right channel DP video signal. Send to module

The video conversion construction unit 5 sets the LVDS video signal decoding parameters according to the characteristics of the LVDS video signal to be received, generates the LVDS video decoding control signal, and sends the LVDS video decoding control signal to the LVDS video signal decoding unit 2. Transmit; Set the LVDS image conversion parameters, generate the LVDS image conversion control signal, and send the LVDS image conversion control signal to the RGB image signal conversion unit 3; Read a DP image conversion configuration parameter and issue a DP conversion configuration command and a DP display module initialization command to the DP image signal conversion unit 4; After receiving the DP video conversion start command from the RGB video signal conversion unit 3, a DP video conversion start command is issued, and the DP video signal conversion unit 4 is sent to the DP video conversion start command. The video conversion configuration unit 5 of this embodiment includes a passive DIP switch 5-1, a JTAG interface 5-2, and a DP video conversion configuration block 5-3. Detailed description of each block is as follows.

The manual DIP switch 5-1 sets the LVDS video signal decoding parameter and the LVDS video conversion parameter; JTAG interface 5-2 receives DP image conversion configuration parameters; The DP video conversion configuration block 5-3 converts the LVDS video signal decoding parameter into an LVDS video decoding control signal to transmit the LVDS video decoding control signal to the LVDS video signal decoding unit 2, and sends the LVDS video conversion parameter to the LVDS video. Converts into a conversion control signal and transmits the LVDS video conversion control signal to the RGB video signal conversion unit 3, reads the DP video conversion configuration parameters, and outputs a DP conversion configuration command and a DP display module initialization command to the DP video signal conversion unit 4; ), The RGB image signal conversion unit 3 receives the DP image conversion start signal, generates a DP image conversion start command, and sends the DP image conversion start command to the DP image signal conversion unit 4.

Before powering on, the DIP switch 5-1 is set for the LVDS video decoding and conversion configuration, and after powering on, the DP video conversion configuration block 5-3 performs the LVDS video decoding control signal and LVDS video according to the DIP state. The conversion control signal is generated, and then the DP video conversion configuration parameters are read from the JTAG interface 5-2 and written to the DP video signal conversion unit 4 one by one in the form of a register command. The DP conversion configuration command is written first. After confirming that the DP video signal conversion unit 4 has completed the configuration and started to operate properly, the DP display module initialization command is recorded. After each command is written, the status value of the register is read to confirm that the command completes execution, and then receiving a DP image conversion control signal, the DP conversion start command is written to the register to start the DP image conversion operation. have.

Each of the functional blocks of the present embodiment may be implemented by an FPGA, and the DP image conversion configuration block 5-3 may also be implemented by a conventional MCU. The DP video signal conversion unit 4 can also be implemented by using two dedicated DP bridge chips to achieve conversion of the DP signal.

<Example 2>

This embodiment describes the addition of a buffering and frequency multiplication unit 6 based on the first embodiment, and the conversion of the LVDS video signal into a DP1.2 video signal.

2 and 5, the system for converting the LVDS video signal of the present embodiment into a DP1.2 video signal includes an LVDS video signal conversion unit, a buffering and frequency multiplication unit, and a DP1.2 video signal conversion unit.

The LVDS video signal conversion unit is used to convert the LVDS video signal into an RGB video signal. The processing for converting the LVDS video signal into the RGB video signal in this embodiment may be the same as the processing of the Chinese patent "Method and system for converting the LVDS video signal to the 4 LANE DP video signal" (publication number CN104966477A). That is, the RGB video signal is obtained by the LVDS video signal receiving unit 1, the LVDS video signal decoding unit 2, the RGB video signal converting unit 3 and the video converting configuration unit 5, and the conversion process is conventional technology. And is not described here.

Compared with Chinese Patent Application Publication No. CN104966477A, the system for converting the LVDS video signal of the present embodiment into a DP1.2 video signal performs buffering and frequency multiplication processing on the obtained RGB video signal and outputs the processed signal. A multiplication unit 6 is further included. The buffering and frequency multiplication unit 6 includes a left channel RGB image signal buffering and frequency multiplication unit 6-1, a right channel RGB image signal buffering and frequency multiplication unit 6-2, and an RGB image signal synchronization unit 6-3. ). The input of the left channel RGB video signal buffering and frequency multiplication unit 6-1 is connected to the RGB video signal output block 3-10, and the output of the left channel RGB video signal buffering and frequency multiplication unit 6-1 is Connected to the left DP1.2 video signal conversion block 4-2; The input of the RGB image signal buffering and frequency multiplication unit 6-2 of the right channel is connected to the RGB image signal output block 3-10, and the output of the right channel RGB image signal buffering and frequency multiplication unit 6-2. Is connected to the right DP1.2 video signal conversion block 4-3; The left DP1.2 video signal conversion block 4-2 and the right DP1.2 video signal conversion block 4-3 are connected to the DP1.2 display module connector, respectively, and the left DP1.2 video signal conversion block 4-4 is connected. 2) and the right DP1.2 video signal conversion block 4-3 are connected to the DP1.2 register block 4-1, respectively.

The process of converting LVDS video signal to DP1.2 video signal in the above system is as follows.

1. Converting an LVDS video signal to an RGB video signal is a prior art and will not be described herein.

2, performing buffering and frequency multiplication processing on the obtained RGB image signal and outputting the processed signal, that is, the left channel RGB image signal buffering and frequency multiplication unit 6-1 outputs the left channel RGB image. Perform a data buffering and data frequency multiplication process on the signal to improve left channel data and clock frequency;

The right channel RGB image signal buffering and frequency multiplication unit 6-2 performs data buffering and data frequency multiplication processing on the output right channel RGB image signal to improve the right channel data and clock frequency;

The RGB image signal synchronization unit 6-3 synchronizes the obtained left channel data with the obtained right channel data so that two paths of the RGB data signal can be output at the same time.

The output frequency multiplication signal performs configuration and conversion for DP1.2 conversion according to a DP1.2 conversion configuration command for obtaining a DP1.2 video signal and a DP1.2 conversion start command. That is, the DP1.2 register block 4-1 controls the configuration and operation for DP1.2 conversion in accordance with the recorded DP1.2 register command;

The left DP1.2 signal conversion block 4-2 receives the left channel RGB video signal after being synchronized by the left channel RGB video signal buffering and frequency multiplication unit 6-1, and receives the synchronized left channel RGB video signal. Perform a configuration and conversion operation of converting to a left channel DP1.2 video signal;

The right DP1.2 signal conversion block 4-3 receives the right channel RGB video signal after being synchronized by the right channel RGB video signal buffering and frequency multiplication unit 6-2, and receives the synchronized right channel RGB video signal. Performs a configuration and conversion operation of converting the right channel DP1.2 video signal;

The DP1.2 display module connector 4-4 simultaneously receives the acquired left channel DP1.2 video signal and right channel DP1.2 video signal, and receives the left channel DP1.2 video signal and the right channel DP1.2 video signal. It is connected to the DP display module for transmission to the DP display module.

The present invention includes, but is not limited to, the field of display and testing of liquid crystal modules. Since signal interfaces of flat panel display modules such as OLED display modules and plasma display modules have universal characteristics, the present invention can also be applied to the field of display and testing of flat panel display modules such as OLED display modules and plasma display modules. In addition, since the signal interface standard of the flat panel display module is frequently updated and upgraded, the present invention includes, but is not limited to, the existing DP 1.0 / DP 1.1 / DP1.2 / DP 1.3 interface standard signal conversion, the DP interface standard signal It is compatible with new DP interface standard signals that are released continuously by the Association of Image Electronics Standards and other types of image interface standard signals with similar effects.

The present invention is not limited to the above-described embodiments, and several improvements, changes, modifications, variations and substitutions made by those skilled in the art according to the technical principles and schemes of the present invention or according to the teachings of the present invention are considered within the scope of the present invention. do.

1- LVDS video signal receiving unit; 1-1- LVDS video signal interface; 1-2- LVDS video signal termination block, 1-3- LVDS clock signal demodulation block, 1-4- LVDS data signal demodulation block, 1-5- LVDS demodulation dynamic correction block;
2- LVDS video signal decoding unit; 2-1- LVDS video synchronization and buffering block; 2-2- LVDS video signal sequencing block; 2-3- LVDS video synchronization signal decoding block; 2-4- LVDS image data decoding block;
3- RGB video signal conversion unit; 3-1- RGB video signal adaptive control block; 3-2- RGB video clock adaptive configuration block; 3-3- RGB video clock generation block; 3-4- RGB video clock output modification block; 3-5- single link mode RGB image conversion block; 3-6- dual link mode RGB image conversion block; 3-7- quad link mode RGB video conversion block; 3-8- left and right split-screen mode RGB image conversion block; 3-9- odd and even split screen mode RGB image conversion block; 3-10- RGB video signal output block;
4-DP video signal conversion unit; 4-1- DP register block; 4-2- left DP video signal conversion block; 4-3- right DP video signal conversion block; 4-4- DP liquid crystal display module connector;
5-image conversion configuration unit; 5-1- manual DIP switch; 5-2- JTAG interface; 5-3- DP image conversion configuration block;
6-buffering and frequency multiplication unit; 6-1- left channel RGB image signal buffering and frequency multiplication unit; 6-2- right channel RGB image signal buffering and frequency multiplication unit; 6-3- RGB video signal synchronization unit.

Claims (14)

A method for converting an LVDS video signal into a DP video signal,
First step; Demodulating the received LVDS video signal to receive an LVDS video signal and to generate demodulated data and an LVDS pixel clock in LVDS parallel;
Second step; Generating LVDS image source data and an LVDS image source synchronization signal by performing image decoding on the LVDS parallel demodulated data according to an LVDS image decoding control signal and an LVDS pixel clock;
Third step; Converting the LVDS image source data and the LVDS image source synchronization signal into an RGB image signal according to an LVDS image conversion control signal; And
Fourth step; And performing a DP conversion configuration and a DP conversion operation on the RGB video signal according to a DP conversion configuration command and a DP conversion start command to obtain a DP video signal.
The output object of the DP video signal comprises a DP liquid crystal display module of 1 LANE, and / or 2 LANE, and / or 4 LANE, and / or 8 LANE type;
When the DP liquid crystal display module is of 4 LANE full-screen type, image conversion of LVDS single LINK mode, dual LINK mode or quad LINK mode is performed according to the LINK conversion mode control signal, and the LVDS video signal is a single LINK. Mode, or a corresponding type of dual LINK mode or quad LINK mode;
When the DP liquid crystal display module is of 8 LANE split-screen type, image conversion of left and right split-screen mode and odd and even split-screen mode is performed according to a LINK conversion mode control signal, and the LVDS video signal is quadruple. Method, which is transmitted in the type of LINK mode. The method of claim 1,
The first step,
Receiving the LVDS video signal comprising an LVDS receive clock and LVDS data;
Performing termination on the received LVDS video signal and outputting the LVDS reception clock and the LVDS data;
Demodulating the LVDS receive clock for each LINK to generate a demodulation clock and a demodulation enable signal; And
And demodulating the LVDS data of the corresponding LINK into data demodulated in parallel with the LVDS by the demodulation clock and the demodulation enable signal of each LINK, and simultaneously demodulating the LVDS receiving clock into the LVDS pixel clock. Way. The method of claim 1,
The second step,
A global clock path converts the LVDS pixel clock into an LVDS image source pixel clock and uses each of the LINK's LVDS pixel clocks for each LINK before reading one by one using the LVDS image source pixel clock to make synchronous data. Simultaneously writing demodulated data in parallel with the LVDS to a caching DC-FIFO;
When receiving the LVDS odd-even pixel reverse-control signal, the data of LINK1 and LINK2 of the two links are exchanged.When receiving the LVDS video signal sequential-control signal, the four links are arranged in the order of LINK1, LINK2, LINK3, and LINK4. Making;
Decoding the LVDS parallel demodulated data of each LINK that is simultaneously read into the LVDS image source synchronization signal according to the received LVDS image decoding control signal; And
Decoding the LVDS parallel demodulated data of each LINK to be read simultaneously into the LVDS image source data signal of each LINK according to the received LVDS image decoding control signal. The method of claim 3, wherein
The third step,
Generating a matched RGB image clock configuration signal in accordance with the LVDS image conversion control signal;
Generating a corresponding configuration parameter and a configuration enable signal by a local clock signal in accordance with the RGB image clock configuration signal;
Generating an RGB image clock according to the configuration parameter and the configuration enable signal and performing a frequency multiplication operation corresponding to the LVDS pixel clock;
Converting the LVDS image source pixel clock to an RGB image pixel clock having the same frequency when configured in a single LINK mode; or
Converting the LVDS image source pixel clock to an RGB image pixel clock having a double frequency when configured in the dual LINK mode; or
Converting the LVDS image source pixel clock to an RGB image pixel clock having four times the frequency when configured in the quad LINK mode;
Using an input RGB image clock with a phase delayed by half a clock cycle as an RGB output clock signal;
Converting the LVDS image source synchronization signal and the LVDS image source data on one LINK into an RGB image signal output; or
Converting the LVDS image source synchronization signal and the LVDS image source data on two LINKs into an RGB image signal output; or
Converting the LVDS image source synchronization signal and the LVDS image source data on four LINKs into an RGB image signal output; or
Converting the LVDS image source synchronization signal and the LVDS image source data on four LINKs into a left half screen RGB video signal and a right half screen RGB video signal output; or
Converting the LVDS image source synchronization signal and the LVDS image source data on four links into an odd pixel RGB image signal and an even pixel RGB image signal which are transmitted to an RGB image signal output;
Selecting a corresponding RGB image signal according to an RGB conversion block selection signal, and performing DP image signal conversion on the selected RGB image signal together with the RGB output clock output; The method of claim 1,
The DP conversion configuration command and the DP conversion start command are issued according to the recorded DP register command.
The fourth step,
Receiving a left channel RGB frequency multiplication signal and performing a DP conversion configuration and a DP conversion operation on the left channel RGB frequency multiplication signal according to the DP conversion configuration command and the DP conversion start command to obtain a left channel DP image signal ; And
Receiving a right channel RGB frequency multiplication signal and performing a DP conversion configuration and a DP conversion operation on the right channel RGB frequency multiplication signal according to the DP conversion configuration command and the DP conversion start command to obtain a right channel DP image signal; ;, Including. A system for converting an LVDS video signal into a DP video signal,
An LVDS video signal conversion unit; And a DP video signal conversion unit provided to the programmable logic device.
The LVDS video signal conversion unit converts the LVDS video signal into an RGB video signal,
The DP video signal conversion unit performs a DP conversion configuration and a DP conversion operation on an RGB video signal according to a DP conversion configuration command and a DP conversion start command for obtaining a DP video signal,
The output object of the DP video signal comprises a DP liquid crystal display module of 1 LANE, and / or 2 LANE, and / or 4 LANE, and / or 8 LANE type;
When the DP liquid crystal display module is of 4 LANE full-screen type, image conversion of LVDS single LINK mode, dual LINK mode or quad LINK mode is performed according to the LINK conversion mode control signal, and the LVDS video signal is a single LINK. Mode, or a corresponding type of dual LINK mode or quad LINK mode;
When the DP liquid crystal display module is of 8 LANE split-screen type, image conversion of left and right split-screen mode and odd and even split-screen mode is performed according to a LINK conversion mode control signal, and the LVDS video signal is quadruple. And is transmitted in the type of LINK mode. The method of claim 6,
The LVDS video signal conversion unit,
An LVDS video signal receiving unit for receiving the LVDS video signal and demodulating the received LVDS video signal to generate demodulated data and an LVDS pixel clock in LVDS parallel;
An LVDS video signal decoding unit for video decoding the demodulated data in parallel with the LVDS according to the LVDS video decoding control signal and the LVDS pixel clock to generate LVDS video source data and an LVDS video source synchronization signal; And
And an RGB image signal conversion unit converting the LVDS image source data and the LVDS image source synchronization signal into an RGB image signal according to an LVDS image conversion control signal. The method according to claim 6 or 7,
The DP video signal conversion unit,
A DP register block for issuing a DP conversion configuration command and a DP conversion start command according to the recorded DP register command;
A left DP signal that receives a left channel RGB frequency multiplication signal and performs a DP conversion configuration and a DP conversion operation on the left channel RGB frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a left channel DP image signal. Transform block;
A right DP signal which receives a right channel RGB frequency multiplication signal and performs a DP conversion configuration and a DP conversion operation on the right channel RGB frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a right channel DP image signal Transform block; And
A DP display module connector configured to simultaneously receive a left channel DP video signal and a right channel DP video signal, and to be connected to a DP display module to transmit the left channel DP video signal and the right channel DP video signal to the DP display module; System. A method for converting an LVDS video signal into a DP video signal,
Step S1: converting the LVDS video signal into an RGB video signal;
Step S2: sequentially performing data buffering and data frequency multiplication processing on the RGB image signal to obtain an RGB frequency multiplication signal;
Step S3: performing a DP conversion configuration and a DP conversion operation on the RGB frequency multiplication signal according to the DP conversion configuration command and the DP conversion start command to obtain a DP image signal;
The output object of the DP video signal comprises a DP liquid crystal display module of 1 LANE, and / or 2 LANE, and / or 4 LANE, and / or 8 LANE type;
When the DP liquid crystal display module is of 4 LANE full-screen type, image conversion of LVDS single LINK mode, dual LINK mode or quad LINK mode is performed according to the LINK conversion mode control signal, and the LVDS video signal is a single LINK. Mode, or a corresponding type of dual LINK mode or quad LINK mode;
When the DP liquid crystal display module is of 8 LANE split-screen type, image conversion of left and right split-screen mode and odd and even split-screen mode is performed according to a LINK conversion mode control signal, and the LVDS video signal is quadruple. The method of transmission in the type of LINK mode. The method of claim 9,
The RGB video signal includes a left channel RGB video signal and a right channel RGB video signal.
Step S2,
Step S21: sequentially performing data buffering and data frequency multiplication processing on the left channel RGB video signal to improve the data rate and clock frequency of the left channel; And simultaneously and sequentially performing data buffering and data frequency multiplication processing on the right channel RGB image signal to improve the data rate and clock frequency of the right channel.
Step S22: performing a synchronization process on the left channel data and the right channel data to obtain a left channel RGB frequency multiplication signal and a right channel RGB frequency multiplication signal transmitted simultaneously. The method of claim 10,
The DP conversion configuration command and the DP conversion start command are issued according to a recorded DP register command,
Step S3,
Receiving a left channel RGB frequency multiplication signal and performing a DP conversion configuration and a DP conversion operation on the left channel RGB frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a left channel DP image signal; And at the same time
Receiving a right channel RGB frequency multiplication signal and performing a DP conversion configuration and a DP conversion operation on the right channel RGB frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a right channel DP image signal; How to. A system for converting an LVDS video signal into a DP video signal,
An LVDS video signal conversion unit; Buffering and frequency multiplication units; And a DP video signal conversion unit provided to the programmable logic device.
The LVDS video signal conversion unit converts the LVDS video signal into an RGB video signal,
The buffering and frequency multiplication unit sequentially performs data buffering and data frequency multiplication processing on an RGB image signal to obtain an RGB frequency multiplication signal,
The DP image signal conversion unit performs a DP conversion configuration and a DP conversion operation on an RGB frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a DP video signal,
The output object of the DP video signal comprises a DP liquid crystal display module of 1 LANE, and / or 2 LANE, and / or 4 LANE, and / or 8 LANE type;
When the DP liquid crystal display module is of 4 LANE full-screen type, image conversion of LVDS single LINK mode, dual LINK mode or quad LINK mode is performed according to the LINK conversion mode control signal, and the LVDS video signal is a single LINK. Mode, or a corresponding type of dual LINK mode or quad LINK mode;
When the DP liquid crystal display module is of 8 LANE split-screen type, image conversion of left and right split-screen mode and odd and even split-screen mode is performed according to a LINK conversion mode control signal, and the LVDS video signal is quadruple. System to be transmitted in the type of LINK mode. The method of claim 12,
The RGB video signal includes a left channel RGB video signal and a right channel RGB video signal.
The buffering and frequency multiplication unit,
A left channel RGB image signal buffering and frequency multiplication unit which sequentially performs data buffering and data frequency multiplication processing on the left channel RGB image signal to improve a data rate and a clock frequency of the left channel;
A right channel RGB video signal buffering and frequency multiplication unit which sequentially performs data buffering and data frequency multiplication processing on the right channel RGB video signal to improve the data rate and clock frequency of the right channel;
And an RGB image signal synchronization unit configured to perform synchronization processing on the left channel data and the right channel data to obtain a left channel RGB frequency multiplication signal and a right channel RGB frequency multiplication signal transmitted simultaneously. The method of claim 12,
The DP video signal conversion unit,
A DP register block for issuing the DP conversion configuration command and the DP conversion start command according to a recorded DP register command;
Receiving the left channel RGB frequency multiplication signal, and performing the DP conversion configuration and the DP conversion operation on the left channel RGB frequency multiplication signal according to the DP conversion configuration command and the DP conversion start command to obtain the left channel DP image signal. block;
Receiving a right channel RGB frequency multiplication signal, and performing a DP conversion configuration and a DP conversion operation on the right channel RGB frequency multiplication signal according to a DP conversion configuration command and a DP conversion start command to obtain a right channel DP image signal. block;
And a DP display module connector which simultaneously receives a left channel DP video signal and a right channel DP video signal, and is connected to the DP display module to transmit a left channel DP video signal and a right channel DP video signal to the DP display module.

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