KR102027949B1 - Error check and correction circuit and semiconductor memory - Google Patents

Abstract

The present invention relates to an error detection correction circuit. The error detection correction circuit of the present invention includes a Chien search unit. The Chien search unit calculates the first bit string by multiplying a predetermined value of (n-k) bits to a plurality of predetermined circles, and multiplies the second bit string by multiplying a predetermined value of k bits. A calculation circuit for calculating and a plurality of Chien search circuits which connect the first bit string and the second bit string to calculate an arbitrary circle and substitute the error position search equation.

Description

ERROR CHECK AND CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY}

The present invention relates to an error detection correction circuit and a semiconductor memory.

In a large memory such as a NAND flash memory, stored data may be lost due to various reasons during data holding. In addition, as the size of the memory and the size of the manufacturing process become smaller, the error rate tends to increase. In order to solve this problem, an error detection correction circuit (ECC) has been used to improve the performance of the flash memory. By mounting the ECC system on-chip, it is possible to provide a high reliability memory. On the other hand, since the data cannot be output to the outside until the correction process is completed in the ECC system, a technique for shortening this time is required.

In order to solve such a problem, the use of a Hamming code (Hamming code) with a fast processing time and a high speed (Bose-Chaudhuri-Hocquenghemcode) code capable of correcting a higher order (higher order) have been studied. The BCH code is one of block codes using a galloche operation. In block codes such as BCH code and RS (Reed-Solomon) code, the error position can be calculated using the error position search equation. The search for the error location is performed, for example, by sequentially substituting each circle of galloise other than zero into the error location search equation and searching the circles of the equation. The search for these circles is called Chien search. Techniques related to speeding up the search for Chien are described in Patent Document 1, Patent Document 2, and the like, for example.

In the techniques described in Patent Document 1, Patent Document 2, and the like, a Chien search circuit for implementing an error position search equation using a flip flop, a register, a multiplication circuit, or the like is described. Then, by inputting a signal indicating the position of the bit into the Chien search circuit, it is determined whether or not the corresponding bit has an error. By providing a plurality of Chien search circuits, it is determined in parallel whether there is an error of a plurality of bits.

Patent Document 1: Japanese Patent Application Laid-Open No. 2001-044853 Patent Document 2: Japanese Patent Application Laid-Open No. 2001-203587

In the techniques described in Patent Document 1, Patent Document 2, and the like, the number of bits to be processed in parallel increases, and the number of Chien search circuits increases. As the number of Chien search circuits increases, the number of wires for supplying a signal indicating a location of bits in the Chien search circuits also increases. Therefore, when the number of bits to be processed in parallel increases, the circuit size of the Chien search unit including the Chien search circuit and its peripheral circuits increases.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above problems, and an object of the present invention is to provide an error correction circuit and a semiconductor memory which suppress an increase in the circuit scale when an error determination process of a plurality of bits is performed in parallel.

Error detection according to an embodiment of the present invention having a Chien search unit for determining whether or not there is an error for each bit of a data string by using an arbitrary circle of galloche GF (2 ^ n) as an substitution value of an error location search equation. In the correction circuit, the Chien search unit calculates a first bit string by multiplying a predetermined value of (n-k) bits to a plurality of predetermined circles, and multiplies a predetermined value of k bits. A calculating circuit for calculating a second bit string; And a plurality of Chien search circuits for connecting the first bit string input from the calculation circuit and the second bit string to calculate an arbitrary circle, and substituting the error position search equation. The Chien search circuit is arranged in a matrix form in a row direction and a column direction, wherein the first bit string is supplied in either the row direction or the column direction, and the second bit string is the row direction or the column direction. Is fed in the other direction.

In an exemplary embodiment, a plurality of Chien search circuits may be provided in a plurality of bits or more of the data string.

In an embodiment, a semiconductor memory may include an error detection correction circuit; Memory cells; And a data storage section for temporarily holding a data string read from the memory cell and supplying it to the error detection correction circuit, wherein the error detection correction circuit includes any circle of galloche GF (2 ^ n). A Chien search unit for determining whether or not there is an error for each bit of the data string by using as a substitution value of an error position search equation, and the Chien search unit has a predetermined number of (n-k) bits for a plurality of predetermined circles. A computing circuit for calculating the first bit string by multiplying the values and calculating the second bit string by multiplying a predetermined value of k bits; And a plurality of Chien search circuits for connecting the first bit string input from the calculation circuit and the second bit string to calculate an arbitrary circle, and substituting the error position search equation. The Chien search circuit is arranged in a matrix form in a row direction and a column direction, wherein the first bit string is supplied in either the row direction or the column direction, and the second bit string is supplied in the row direction or the column direction. Is fed in the other direction.

In the present invention, when the n-th order vector representation of any circle of gallosome GF (2 ^ n) is regarded as an n-bit bit string, the bit string is multiplied by a predetermined value of (n-k) bits. The first bit string is calculated and the second bit string is calculated by multiplying a predetermined value of k bits. The Chien search circuit acquires a signal indicative of the position of the bit in accordance with the connection of the first bit string and the second bit string. In addition, since the first or second bit strings can be provided in common to the Chien search circuits arranged in the column direction and the row direction in the matrix field, each Chien search circuit has wiring for supplying a signal indicating a bit position. There is no need to do it. Therefore, the number of wirings for supplying a signal indicating a bit position to the Chien search circuit can be reduced, so that the circuit scale of the Chien search unit can be reduced.

1 is a block diagram illustrating a nonvolatile semiconductor memory (semiconductor memory) according to an embodiment of the present invention.
2A and 2B are block diagrams for explaining the error detection and correction circuit shown in FIG.
FIG. 3 is a block diagram illustrating the Chien search unit shown in FIG. 2A.
4 is a view for explaining the output signal of the S calculator, the output signal of the P calculator and the output signal of the Q calculator shown in FIG.
FIG. 5 is a block diagram illustrating the Chien search circuit shown in FIG. 3.
FIG. 6 is a block for explaining an error position search equation calculator shown in FIG. 5.
FIG. 7 is a table for describing the processing contents of the Chien search unit shown in FIG. 3.
8A and 8B are tables for explaining the processing contents of the Chien search unit shown in FIG. 3.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

FIG. 1 is a block diagram illustrating a NAND flash memory as a nonvolatile semiconductor memory device 10 according to an embodiment of the present invention. The nonvolatile semiconductor memory device 10 includes a memory cell array 11, a page buffer 12, an error detection correction circuit 13, a buffer 14, an I / O pad 15, a control circuit 16, and an address. Decoder 17 and row and block decoder 18 are included.

In the memory cell array 11, a plurality of stacked gate structure transistors, that is, NAND cells electrically connected to non-volatile memory cells (memory elements) that are electrically connected in series in a column direction (column direction) and provided for each bit line The string includes a plurality of blocks arranged in a row direction (array direction of bit lines). A plurality of blocks are arranged in the wiring direction of the bit line. The blocks are set in units of erasing data of the memory cells. In each block, a word line orthogonal to the bit line is connected to the gate of each of the nonvolatile memory cells arranged in the same row. The range of a nonvolatile memory cell selected by one word line is a page which is a unit of program and read.

The page buffer 12 includes a page buffer circuit provided for each bit line in order to program and read data in page units. Each page buffer circuit of the page buffer 12 includes a latch circuit connected to each bit line and used as a sense amplifier circuit for amplifying and determining the potential of the connected bit line.

The page buffer 12 (data storage section) is a cell that is data (data string) stored in memory cells of one page of the memory cell array 11 during a data read operation of the nonvolatile semiconductor memory device 10. The data Cell # Data is received, and the received data is amplified and output to the error detection correction circuit 13. On the other hand, the page buffer 12 stores the data supplied from the error detection and correction circuit 13 in the internal latch circuit during the data write (program) operation of the nonvolatile semiconductor memory device 10, and verifies the operation. While executing, all data is written into the memory cells of one page as code data Code # Data. The code data Code_Data includes parity data Parity generated by the error detection correction circuit 13.

In the embodiments of the present invention, the error detection and correction circuit 13 uses a galloche of GF (2 ^ 9) as a correction unit for a data string having 256 bits of information data length, and a 4-bit error correction BCH. Assume that you use signs. In this case, the length of parity data in each correction unit is 36 bits. Thus, the encoded data string has a data length equal to the sum of the bit lengths of 292 bits and other additional bits. In embodiments of the present invention, as an example, it is assumed that the data length of the encoded data string is 320 bits. In addition, the embodiments of the present invention are not limited to the BCH code, but may be utilized for a block code (BCH code, RS code, etc.) using a Galois operation.

In the data read operation of the nonvolatile semiconductor memory device 10, the error detection correction circuit 13 processes data read from the page buffer 12 for each sector to calculate the coefficient of the error position detection polynomial, and calculates the result. Latch and keep it inside. In addition, the error detection correction circuit 13 corrects an error of data of bits whose position is indicated by a column address during a read operation, and externally corrects the data as corrected data through the I / O pad 15. Will output

In addition, the error detection correction circuit 13 receives, via the buffer 14, information data (Information_Data) input from the I / O pad 15 during the data write operation of the nonvolatile semiconductor memory device 10. do. The error detection correction circuit 13 generates parity data from the received information data, and sends the received information data and the parity data to the page buffer 12. Output The page buffer 12 writes the received data as code data to memory cells connected to the selected page.

The control circuit 16 inputs various control signals to perform operations such as programming, reading, and erasing data and verifying operations of nonvolatile memory cells. For example, the control signal includes an external clock signal, a chip enable signal (/ CE), a read enable signal (/ RE), a program enable signal (WE), a command latch enable signal (CLE), and an address latch enable. Signal ALE, write prevention signal / WP, and the like.

The control circuit 16 outputs an internal control signal to each circuit in response to the operation mode indicated by the control signal and the command data input from the I / O pad 15. For example, the control circuit 16 responds to the command latch enable signal CLE from the low (L) level to the high (H) level at the first start of the program enable signal (/ WE), The command data is read from the I / O pad 15 and stored in an internal register.

The address decoder 17 holds an address (row address, block address, column address) input from the I / O pad 15 based on an internal control signal from the control circuit 16. In addition, the address decoder 17 transfers the held address to the row and block decoder 18, the page buffer 12, and the error detection correction circuit 13 based on an internal control signal from the control circuit 16. Output

For example, the control circuit 16 may respond to the address latch enable signal ALE from the low (L) level to the high (H) level at the first start of the program enable signal / WE. The address is read from the / O pad 15 and held in an internal register of the address decoder 17.

The row and block decoder 18 selects the block and the word line of the memory cell array 11 in response to the row address and the block address held and output by the address decoder 17 to select one page of memory cells. Choose. In addition, the address decoder 17 selects the bit line and the page buffer 12 of the memory cell array 11 in response to the column address held therein.

In embodiments of the present invention, in a data read operation, cell data in the page buffer 12 is transmitted to the error detection correction circuit 13, and coefficients of the error position search equation are calculated for each error correction unit. . Then, in response to the coefficient calculated for each error correction unit and a signal indicating an error position (that is, data representing each circle of galloche GF (2 ^ 9)), a bit whose position is specified by a signal indicating an error position is used. It is detected whether there is an error in the data, and if there is an error, the corresponding bit is corrected and output to the I / O pad 15 as corrected data. Details will be described later.

In the data write operation, cell data stored in the page buffer 12 is transferred to the buffer 14. The buffer 14 may be, for example, static random access memory (SRAM).

In the buffer 14, data of a portion of the cell data corresponding to the input column address may be updated with information from the I / O pad 15. In the error detection correction circuit 13, parity data corresponding to data corresponding to one correction unit including the data after the update of the buffer 14 is calculated. The encoded data including the parity data is written to the selected page through the page buffer 12 as code data.

2A shows a detailed configuration example of the error detection correction circuit 13. The error detection and correction circuit 13 includes a decoder 21 for decoding data and an encoder 22 for generating correction parity data Parity and adding correction parity data Parity to data written in a cell. Include.

The encoder section 22 includes a parity generation circuit 41. The parity generating circuit 41 generates parity data obtained by generating information data written in the buffer 14 and division (for example, dividing) into a polynomial. The parity generating circuit 41 adds the parity data generated to the information data to the page buffer 12. The output data is code data (Code # Data) written in one selected page when data is written in the nonvolatile semiconductor memory device 10. Embodiments of the present invention are characterized in that data correction processing is performed by using an effective configuration for reducing the layout size of the error detection and correction circuit 13 when reading data from the nonvolatile semiconductor memory device 10. . Hereinafter, the decoder unit 21 will be described in detail.

The decoder unit 21 includes a syndrome calculation circuit 31, an error coefficient calculation circuit 32, a Chien search unit 33, and an error correction circuit 34. The syndrome calculating circuit 31 receives a code data string (Code Data Y) for each correction unit and calculates a plurality of syndromes by dividing the received code data string by an independent minimum polynomial. In an embodiment of the present invention, a BCH code capable of error correction of 4 bits of data is used. Thus, the minimum independent polynomial is four. Therefore, the syndrome calculation circuit 31 calculates four syndromes S1, S3, S5, and S7.

The error coefficient calculating circuit 32 calculates coefficients e4, e3, e2, e1, e0 of the error position search equation Λ (x) for each correction unit by using the syndrome. The coefficients e4, e3, e2, e1, e0 are coefficients of the error position search equation "Λ (x) = e4x ^ 4 + e3x ^ 3 + e2x ^ 2 + e1x ^ 1 + e0" shown in FIG. 2B. . The error position search equation Λ (x) is used by the Chien search unit 33 when searching whether or not there is an error in the bit read from the page buffer 12 for each correction unit.

The Chien search unit 33 performs error detection for each of the correction units (e4, e3, e2, e1, e0) input from the error coefficient calculating circuit 32 for each correction unit, and if an error is detected, the corresponding bit. It outputs a signal indicating the position (Z [319: 0]). The signal Z [319: 0] is 320 bits of data representing the value of the error position search equation corresponding to each bit position. Signals Z [0], Z [1],... , Z [319] is 0th, 1st,... Indicates whether there is an error in the data at the 319th bit position. Here, the 0th bit is the least significant bit. In an embodiment of the present invention, it is assumed that the i th bit where the value of the signal Z [i] is '1' is an error bit, and the i th bit that becomes '0' is an error free bit.

The error correction circuit 32 performs the code data string when the error bit represented by the signal Z [319: 0] is within 4 bits, i.e., when there are 4 or less i whose "Z [i] = 1". Reverses the value of the bit at the position where the error is detected in (Code Data Y).

Next, with reference to FIG. 3, the structural example of the Chien search part 33 shown in FIG. 2A is demonstrated. As shown in FIG. 3, the Chien search unit 33 includes an S calculator 51, a P calculator 52, a P latch 53, and a Q calculator 54. Q latch 55, and Chien search circuit group 56. The Chien search circuit group 56 includes a plurality of Chien search circuits 57. The plurality of Chien search circuits 57 are arranged in a matrix form in the row and column directions with respect to the Chien search circuit group 56. For example, the plurality of Chien search circuits 57 are arranged in 16 rows and 32 columns (e.g., 16 grids in the vertical direction and 32 grids in the horizontal direction). However, the Chien search circuit 57 need not be provided at every intersection or intersection of rows and columns (e.g., 16 x 32 = 512 points), but the data length of the encoded data column (i.e. the number of bits used). Some may be omitted.

Each of the Chien search circuits 57 may be configured as shown in FIG. 5. FIG. 5 is a block diagram showing a configuration example of the Chien search circuit 57 shown in FIG. The Chien search circuit 57 shown in FIG. 5 includes a substitution value calculator 71 and an error position search equation calculator 72. The substitution value calculating section 71 supplies the bit string signal dpj (one of j = 0 to 31) supplied from the P latch 53 and the bit string signal dqk supplied from the Q latch 55 (k = 0). By receiving one of ˜15) and adding the received signals (i.e., calculating dpj + dqk), so that the circles α of the Galloche substituted for x in the error location search equation Λ (x) shown in FIG. 2B. ^ i) (i = 0, 1, 2, ..., 511 (= 2 ^ 9-1))

The error position search equation calculation unit 72 shown in FIG. 5 includes the coefficients e4 of the circle α ^ i supplied from the substitution value calculation unit 71 and the error position search equation supplied from the S calculator 51. Based on e3, e2, e1, e0), the circle α ^ i is substituted into the error position search equation Λ (x) and the value of the error position search equation Λ (x) is calculated. In other words, the error position search equation Λ (x) is calculated as "x = α ^ i". Here, the value Z [i] of the i-th bit of the signal Z [319: 0] is " 1, " " Λ (α ^ i) ≠ when " Λ (α ^ i) = 0 " 0 ", it is set to '0'.

In addition, the error position search equation calculation unit 72 may be configured, for example, as shown in FIG. 6. FIG. 6 is a block diagram showing an example of the configuration of the error position search equation calculation unit 72 shown in FIG. The error position search equation calculation unit 72 shown in FIG. 6 includes the "e1 (α ^ i) + e0" calculation unit 81, the "e2 (α ^ i) ^ 2" calculation unit 82, and "e3 (α) ^ i) ^ 3 "calculation unit 83," e4 (α ^ i) ^ 4 "calculation unit 84, and" Z [i] "calculation unit 85. The "e1 (α ^ i) + e0" calculation unit 81 calculates "e1 (α ^ i) + e0" using the circle α ^ i and the coefficients e1, e0. The "e2 (α ^ i) ^ 2" calculation unit 82 calculates "e2 (α ^ i) ^ 2" using the circle α ^ i and the coefficient e2. The "e3 (α ^ i) ^ 3" calculation unit 83 calculates "e3 (α ^ i) ^ 3" using the circle α ^ i and the coefficient e3. The "e4 (α ^ i) ^ 4" calculation unit 84 calculates "e4 (α ^ i) ^ 4" using the circle α ^ i and the coefficient e4. Then, the "Z [i]" calculation unit 85 includes "e1 (α ^ i) + e0" calculation unit 81, "e2 (α ^ i) ^ 2" calculation unit 82, and "e3 (α ^). i) ^ 3 "calculation unit 83 and" e4 (α ^ i) ^ 4 "calculation unit 84, using" e4 (α ^ i) ^ 4 + e3 (α ^ i) ^ 3 + e2 (α) ^ i) ^ 2 + e1 (α ^ i) + e0 "is calculated. The "Z [i]" calculation unit 85 determines whether the calculated value is 0 or not, and based on the determination result, determines the value Z [i] of the i-th bit of the signal Z [319: 0]. In the case of "Λ (α ^ i) = 0", it is set to "1" and in the case of "Λ (α ^ i) ≠ 0", the output is set. In addition, the "e2 (α ^ i) ^ 2" calculation unit 82, the "e3 (α ^ i) ^ 3" calculation unit 83, and the "e4 (α ^ i) ^ 4" calculation unit 84 For example, it may be composed of a plurality of multipliers. In this case, each calculation may be calculated for one clock period.

The S calculator 51 receives the coefficients e4, e3, e2, e1, e0 from the error coefficient calculating circuit 32 and outputs them to each Chien search circuit 57. In addition, the S calculator 51 uses galloaches GF (2 ^ 9) which are used when each Chien search circuit 57 generates a value substituted into the error position search equation Λ (x) during Chien search. Generate a portion of the circles and output as signals S1, S2, S3, S4, S5, S6, S7, S8.

Here, with reference to FIG. 7, the signal S1, S2, S3, S4, S5, S6, S7, S8 which the S calculator 51 outputs is demonstrated. FIG. 7 is a table describing some of the circles of galloche (GF (2 ^ 9)). As shown in FIG. 7, each circle may be represented by a Becky representation, a polynomial representation, and a vector representation. As shown in FIG. 7, in galloace (GF (2 ^ 9)) (m = 9), "1 (= α ^ 0), α ^ 1, α ^ 2, ..., α ^ ( The nine circles of "m-1) (= alpha 8)" have a value in which either bit of each bit of nine bits in the vector representation is '1'. As a Becky expression, the vector representation of nine circles with "α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8" is '000000001', '000000010', '000000100', '000001000', '000010000', '000100000', '001000000', '010000000' and '100000000'. Therefore, all the circles (α ^ i (i = 0, 1, 2, ..., 2 ^ (m-1) (= 511))) of galloace (GF (2 ^ 9)) are "α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8 "may be represented by a plurality of combinations of nine circles (for example, as a result of being added to each other).

For example, in the case of substitution into the error position search equation Λ (x), the circle α ^ 9 corresponding to bit 9 may be generated according to Equation (1).

Likewise, all values of "α ^ 10, ..., α ^ 511" can be calculated by combining the nine circles (α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8) described above.

The S calculator 51 generates values of nine circles α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8, as shown in Fig. 4A, and the signals S1, S2, S3. , S4, S5, S6, S7, S8). The signals S1, S2, S3, S4, S5, S6, S7, and S8 are 9-bit signals, respectively.

As described above, the Chien search circuit 57 according to the embodiment of the present invention calculates the substitution value α ^ i by the addition process of the substitution value calculation unit 57 and calculates an error position search equation. By substituting the value calculated using the section 72, the value of the position search equation Λ (x) is calculated. Therefore, each Chien search circuit 57, if a signal indicating nine circles α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8 is supplied, all the circles α ^ 0, ..., Any circle α ^ i can be calculated from α ^ 511). Thus, each Chien search circuit 57 can calculate the value of the error position search equation Λ (x) for any circle α ^ 0, ..., α ^ 511. However, all the signals indicating the nine circles α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8 must be supplied to each Chien search circuit 57. However, not all Chien search circuits 57 use all of the signals pointing to the nine circles α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8. Supplying unnecessary signals means installing unnecessary wiring. Here, in the configuration described with reference to FIG. 3, in order to reduce unnecessary wiring, a signal indicating nine circles (α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8) is selected as the base value. Group the selected base values into signal parts of 2 parts (P part and Q part), classify each signal part as 32 or 16 using quasi-base value (ie after 512 classification), and then Signals of one classification are supplied to each Chien search circuit 57. As a result, only one predetermined circle α ^ i can be calculated by each Chien search circuit 57.

If all of the signals indicating the nine circles (α ^ 0, α ^ 1, α ^ 2, ..., α ^ 8) are supplied, a signal line of 9 bits x 9 is used, while an 81-bit signal line is used. In the example, arbitrary circles α ^ i can be calculated only by using two 9-bit signal lines (total 18-bit signal lines) orthogonal to each other for the Chien search circuit 57.

The quasi-base value is the value (p0 to p31) and the Q part of 5 bits of the P part (i.e., 9-4 = 5 bits of galloise (GF (2 ^ 9))) and the Q part, as shown in Figs. 8A and 8B. It includes four bits of values q0 to q15. Herein, the P part is shown in Fig. 8A, '00000_0000', '00001_0000', '00010_0000',... , '11111_0000', and corresponds to base values (α ^ 4, α ^ 5, α ^ 6, α ^ 7, α ^ 8) corresponding to the upper 5 bits of 'x'. On the other hand, the Q part is a value corresponding to the base values α ^ 0, α ^ 1, α ^ 2, and α ^ 3 corresponding to the lower 4 bits of x of 9 bits.

In the embodiment of the present invention, by combining the two-part bit string signals dpj and dqk generated using quasi-base values, nine circles α0 and α1, for each Chien search circuit 57, are combined. In addition to α ^ 2, ..., α ^ 8, the remaining circles α ^ 9, ..., α ^ (t-1) (t = 2 ^ m) are generated. The bit string signals dpj and dqk of two parts are calculated by the P calculator 52 and the Q calculator 54.

The P calculator 52 is based on the nine-bit signals S4, S5, S6, S7 and S8, according to the calculation formula shown in Fig. 4B, the nine-bit bit string signals dp0, dp1, dp2, ..., dp30. , dp31) and print it. For example, the signal dp1 multiplies each bit of the signal S4 by the bit 4 ('1') of the quasi-base value p1 shown in Fig. 8A, and thus the bit 5 ('0') is the signal S5. As a result of multiplying each bit of), bit 6 ('0') by multiplying each bit of signal S6, bit 7 ('0') by multiplying each bit of signal S7, and bit 8 ( '0') is calculated as the result of adding the result of multiplying each bit of the signal S8.

Further, the signal dp2 is obtained by multiplying each bit of the signal S4 by the bit 4 ('0) of the quasi-base value p2 shown in FIG. 8A, and the bit 5 (' 1 ') of the signal S5. As a result of multiplying each bit, bit 6 ('0') by multiplying each bit of signal S6, as a result of multiplying bit 7 ('0') by each bit of signal S7, and bit 8 ('0) The result of multiplying ') by each bit of the signal S8 is calculated as the result of the addition.

The signals dp0, dp1, dp2,..., Dp30, and dp31 calculated by the P calculator 52 are stored in the P latch 53. The P latch 53 outputs the latched signals dp0, dp1, dp2, ..., dp30, dp31 in synchronization with a predetermined clock signal for clock skew adjustment. The signals dp0, dp1, dp2,..., Dp30, and dp31 output from the P latch 53 are supplied to the plurality of Chien search circuits 57 through 32 signal line parts of 9 bits each provided in the column direction.

The Q calculator 54 is based on each of the nine bits of signals S0, S1, S2, S3, according to the calculation formula shown in Fig. 4B, each of the nine bit bit string signals dq0, dq1, dq2, ..., dq14. , dq15). For example, the signal dq1 multiplies each bit of the signal S3 by bit 3 ('0') of the quasi-base value q1 shown in FIG. 8B, and thus bit 2 ('0') is multiplied by the signal S2. Multiply each bit of < RTI ID = 0.0 >), < / RTI > the result of multiplying each bit of signal S1 by the bit 1 ('0;) and the result of multiplying each bit of the signal S0 by the bit 0 (' 1 '). Calculate with the result.

Further, the signal dq2 is obtained by multiplying each bit of the signal S3 by the bit 3 ('0') of the quasi-base value q2 shown in FIG. 8B, and the bit 2 ('0') of the signal S2. As a result of multiplying each bit, bit 1 ('1') by multiplying each bit of signal S1, and bit 0 ('0') by multiplying each bit of signal S0, as a result Can be calculated

The calculated signals dq0, dq1, dq2, ..., dq14, dq15 calculated by the Q calculator 54 are input to the Q latch 55. The Q latch 55 outputs the latched signals dq0, dq1, dq2, ..., dq14, dq15 in synchronization with a predetermined clock signal for clock skew adjustment. The signals dq0, dq1, dq2, ..., dq14, dq15 output from the Q latch 55 are supplied to the plurality of Chien search circuits 57 through 16 signal line parts of each of 9 bits provided in the row direction.

The configuration of the bit string signal dpj and the bit string signal dqk is not limited to those described above (j = 0 to 31, k = 0 to 15). That is, it is possible to reverse the wiring direction of the bit column signal dpj and the bit column signal dqk in rows and columns, or to change the number of wirings of the bit column signal dpj and the bit column signal dqk. That is, in the embodiment of the present invention, the plurality of Chien search circuits 57 are arranged in a matrix form along the row direction and the column direction, and the bit column signal dpj is in one of the row direction or the column direction, The signal dqk may be supplied in the other direction of the row direction or the column direction.

In the case of using the galloace (GF (2 ^ m)), the circuit for correcting n errors is Chien search, and the error position search equation (Λ (x) = enx ^ n +… + e2x ^ 2 + e1x + Each circle (α ^ i) (i = 0, 1, 2, ..., 2 m-1) of galloace (GF (2 ^ m)) is substituted into the variable x of e0) and "Λ (x) = 0 It is determined whether or not. That is, the values of the error position search equation Λ (x) are calculated by substituting the respective values of the circles α ^ 0, α ^ 1, α ^ 2, ..., α ^ (t-1) (t = 2 m). do. In the conventional configuration, each circle α ^ i (i = 0, 1, 2, ..., 2 ^ (m-1)) is sequentially arranged in one circuit for calculating the error position search equation (Λ (x)). By substituting, the value of the error position search equation Λ (x) corresponding to one circle in one cycle is calculated. The configurations described in Patent Document 1 and Patent Document 2 cause Chien search to operate in parallel. For example, the values for two circles are calculated simultaneously in parallel.

On the other hand, the Chien search unit 33 according to the embodiment of the present invention described above, the plurality of circles (α ^ i) (i = 0, 1, 2, ..., 2 ^ (m-1)) a plurality of values It is supplied to any part of the Chien search circuit 57. That is, according to an embodiment of the present invention, an error position search equation Λ (x) when each circle α ^ i (i = 0, 1, 2, ..., 2 ^ (m-1)) is substituted ) Can be calculated collectively using the plurality of Chien search circuits 57.

In an embodiment of the present invention, a plurality of Chien search circuits 57 are arranged in a matrix form, a plurality of values that are substituted into the error location search equation Λ (x) are divided into two parts, and the value of each part is It is supplied separately from two directions orthogonal to the row and column directions. Therefore, by appropriately selecting the arrangement of the Chien search circuit 57 and the division of the values, the wirings supplying each substitution value can be wired linearly (ie, at the shortest distance).

Embodiments of the invention are not limited to those described above. For example, a change may be performed such that the number of information bits or the number of parity bits are changed, each block of the configuration shown in the block diagram is further divided, or a plurality of blocks are integrated.

In addition, the application range of the error detection and correction circuit according to the embodiment of the present invention is not limited to the semiconductor memory. For example, the error detection and correction circuit according to an embodiment of the present invention can be applied to the case of recording and reading information on various recording media.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

10; Nonvolatile semiconductor memory 11; Memory cell array
12; Page buffer 13; Error detection correction circuit
14; Buffer 15; I / O pad
16; Control circuit 17; Address decoder
18; Low and Block Decoder
21; Decoder section 31; Syndrome output circuit
32; Error coefficient calculating circuit 33; Chien Seeker
34; Error correction circuit 41; Parity generation circuit
51; S calculator 52; P calculator
53; P latch 54; Q calculator
55; Q latch 56; Chien Search Circuit Group
57; Chien search circuit 71; Substitution value calculator
72; Error position search equation calculation unit

Claims (3)

In an error detection correcting circuit having a Chien search unit for determining whether or not there is an error for each bit of a data string by using an arbitrary circle of gallosomes GF (2 ^ n) as an substitution value of an error position search equation:
The Chien search unit,
A calculating circuit that calculates a first bit string by multiplying a predetermined value of (n-k) bits for a plurality of predetermined circles, and calculates a second bit string by multiplying a predetermined value of k bits. ; And
A plurality of Chien search circuits for connecting the first bit string input from the calculation circuit and the second bit string to calculate an arbitrary circle, and substituting the error position search equation;
The plurality of Chien search circuits are arranged in a matrix form in a row direction and a column direction,
And the first bit string is supplied in either the row direction or the column direction, and the second bit string is supplied in the other direction in the row direction or the column direction. The method of claim 1,
An error detection correction circuit provided with a plurality of said Chien search circuits more than the number of bits of said data string. Error detection correction circuit;
Memory cells; And
A data storage section for temporarily holding a data string read from the memory cell and supplying it to the error detection correction circuit;
The error detection correcting circuit includes a Chien search unit for determining whether or not an error exists for each bit of the data string by using an arbitrary circle of gallosome GF (2 ^ n) as an substitution value of an error position search equation,
The Chien search unit,
A calculating circuit that calculates a first bit string by multiplying a predetermined value of (n-k) bits for a plurality of predetermined circles, and calculates a second bit string by multiplying a predetermined value of k bits. ; And
A plurality of Chien search circuits for connecting the first bit string input from the calculation circuit and the second bit string to calculate an arbitrary circle, and substituting the error position search equation;
The plurality of Chien search circuits are arranged in a matrix form in a row direction and a column direction,
And the first bit string is supplied in either the row direction or the column direction, and the second bit string is supplied in the other direction of the row direction or the column direction.

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