KR102034047B1 - Liquid crystal display device and method for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof that can improve image quality by preventing luminance deviation between an upper end portion and a lower end portion of a liquid crystal panel, and sequentially supplying data voltages to all pixels during each frame period. By temporarily storing the supplied data voltage, and then in the blank period after each frame period, all pixels simultaneously apply the stored data voltage to the pixel electrode, thereby reducing the vertical luminance deviation of the liquid crystal panel according to the AC driving of the common voltage. You can prevent it.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to a liquid crystal display device and a driving method thereof capable of improving image quality by preventing luminance deviation between an upper end portion and a lower end portion of a liquid crystal panel.

Recently, the liquid crystal display (Liquid Crystal Display) is the most used because of the excellent image quality, light weight, thin, low power characteristics of the display elements.

1 is a pixel equivalent circuit diagram of a general liquid crystal display device.

Referring to FIG. 1, a general liquid crystal display device defines a pixel at an intersection of a gate line GL and a data line DL, and each pixel is a thin film transistor (TFT) and a liquid crystal connected to a TFT. A capacitor Clc and a storage capacitor Cst are provided. The liquid crystal capacitor Clc includes a pixel electrode connected to the TFT, and a common electrode for applying an electric field to the liquid crystal together with the pixel electrode. The common voltage is supplied to the common electrode.

The liquid crystal display displays an image by driving the liquid crystal by the pixel voltage charged in the liquid crystal capacitor Clc and the storage capacitor Cst according to the data signal. However, when the pixel voltage always has the same polarity, that is, a positive value or a negative value, the liquid crystal is deteriorated. Accordingly, a data inversion method for changing the polarity of the data signal every frame has been introduced. In order to reduce the driving voltage of the data signal during data inversion, a common voltage AC driving method of changing the polarity of the common voltage Vcom every frame has been introduced.

However, when the polarity of the common voltage Vcom is changed every frame according to the common voltage alternating current driving, the pixel voltage is shifted together and the pixel voltage does not maintain the original voltage value during the shifted pixel voltage. As a result, the voltage between the pixel voltage and the common voltage, that is, the voltage applied to the liquid crystal is lowered, and as shown in FIG. 2, a luminance difference occurs at the upper end and the lower end of the liquid crystal panel 100. As such, the luminance deviation of the liquid crystal panel 100 is further increased from the upper end to the lower end, thereby degrading the luminance uniformity of the liquid crystal panel 100.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a liquid crystal display device and a driving method thereof capable of improving image quality by preventing luminance deviation between an upper end and a lower end of a liquid crystal panel.

In order to achieve the above object, the liquid crystal display according to the exemplary embodiment of the present invention includes a plurality of pixels connected to the first to third gate lines and the data line; Each pixel comprises: a first switching element for supplying a data voltage provided from the data line to the memory electrode in response to a scan signal applied to the first gate line; A first storage capacitor connected to the memory electrode to store the data voltage; A second switching element configured to supply a common voltage applied to the common electrode from the common line to the pixel electrode in response to a reset signal applied to the second gate line; A third switching element configured to supply the data voltage stored in the first storage capacitor to the pixel electrode in response to a write signal applied to a third gate line; A second storage capacitor connected to the pixel electrode to store the data voltage; In each frame period, as the scan signal is sequentially applied to the first gate lines, the data voltage is stored in the first storage capacitor for each pixel, and in the blank period after each frame period, the reset The common voltage is supplied to the pixel electrode for each pixel as a signal is simultaneously applied to the second gate lines, and the first storage for each pixel as the write signal is simultaneously applied to the third gate lines. After the data voltage stored in the capacitor is supplied to the pixel electrode, the polarity of the common voltage is inverted.

The common electrode may form a horizontal electric field or a vertical electric field together with the pixel electrode.

A memory electrode connected to the first switching element and overlapping a next common line with a first insulating layer interposed therebetween; And a common electrode connected to the next common line through a contact hole and overlapping the memory electrode with a second insulating layer interposed therebetween.

The polarity of the common voltage is opposite to the polarity of the data voltage.

In addition, in order to achieve the above object, the driving method of the liquid crystal display according to the embodiment of the present invention comprises a plurality of pixels connected to the first to third gate line and the data line; Each pixel comprises: a first switching element for supplying a data voltage provided from the data line to the memory electrode in response to a scan signal applied to the first gate line; A first storage capacitor connected to the memory electrode to store the data voltage; A second switching element configured to supply a common voltage applied to the common electrode from the common line to the pixel electrode in response to a reset signal applied to the second gate line; A third switching element configured to supply the data voltage stored in the first storage capacitor to the pixel electrode in response to a write signal applied to a third gate line; And a second storage capacitor connected to the pixel electrode to store the data voltage, wherein the scan signal is sequentially applied to the first gate lines in each frame period. Applying and storing the data voltage in the first storage capacitor for each pixel; In the blank period after each frame period, the reset signal is simultaneously applied to the second gate lines to supply the common voltage to the pixel electrode for each pixel, and then the write signal is applied to the third gate lines. And simultaneously applying the data voltage stored in the first storage capacitor to the pixel electrode for each pixel, and then inverting the polarity of the common voltage.

Inverting the polarity of the common voltage may be such that the polarity of the common voltage is opposite to the polarity of the data voltage.

The present invention sequentially supplies data voltages to all pixels during each frame period, and allows each pixel to temporarily store the supplied data voltages, and then, in the blank period after each frame period, all pixels simultaneously store the data voltages. By applying to the pixel electrode, it is possible to prevent the vertical brightness deviation of the liquid crystal panel due to the AC drive of the common voltage.

1 is a pixel equivalent circuit diagram of a general liquid crystal display device.
FIG. 2 is a diagram illustrating a problem in luminance variation of upper and lower ends of a liquid crystal panel according to common voltage AC driving.
3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. 4 is a driving waveform diagram of the liquid crystal panel 2 shown in FIG. 3.
5 is an equivalent circuit diagram illustrating a pixel structure of the present invention.
FIG. 6 is a plan view schematically illustrating the pixel illustrated in FIG. 5.
FIG. 7 is a cross-sectional view taken along line AA ′ of FIG. 6.

Hereinafter, a liquid crystal display and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. 4 is a driving waveform diagram of the liquid crystal panel 2 shown in FIG. 3.

The liquid crystal display shown in FIG. 3 includes a liquid crystal panel 2 having a plurality of pixels connected to first to third gate lines GL1, GL2, and GL3 and a data line DL, and first to third pixels. A gate driver 4 for driving the gate lines GL1, GL2, and GL3, a data driver 6 for driving the data lines DL, and a common line CL connected to each pixel of the liquid crystal panel 2; A common voltage supply unit 8 for supplying a common voltage Vcom to the common voltage Vcom, and a gate control signal GCS and a data control signal DCS for controlling the gate driver 4 and the data driver 6. The timing controller 10 is provided.

The present invention sequentially supplies data voltages to all pixels during each frame period, and allows each pixel to temporarily store the supplied data voltages, and then, in the blank period after each frame period, all pixels simultaneously store the data voltages. By applying to the pixel electrode, it is possible to prevent the vertical luminance deviation of the liquid crystal panel 2 caused by the AC drive of the common voltage Vcom. This invention will be described in detail later with reference to FIGS. 5 and 6.

The liquid crystal panel 2 has two substrates and a liquid crystal layer interposed therebetween. A TFT array (Thin Film Transistor Array) is formed on the lower substrate of the liquid crystal panel 2. The TFT array includes a plurality of data lines DL to which a data voltage is supplied, and a plurality of data signals DL to which a scan signal, a reset signal, and a write signal Write are supplied while crossing the data lines DL. The first and third gate lines GL1, GL2, and GL3, and pixels formed at intersections of the data lines DL and the first to third gate lines GL1, GL2, and GL3 are provided. The structure and driving method of each pixel will be described later in detail.

A color filter array is formed on the upper substrate of the liquid crystal panel 2. The color filter array includes a black matrix and a color filter. Meanwhile, the liquid crystal panel 2 includes a common electrode 34 that forms an electric field together with the pixel electrode 38, and the common electrode 34 is vertical such as a twisted nematic (TN) mode and a vertical alignment (VA) mode. In the electric field driving method, the substrate is formed on the upper substrate, and in the horizontal electric field driving method such as the IPS (In Plane Switching) mode and the FFS (Fringe Field Switching) mode, it is formed on the lower substrate together with the pixel electrode. The present invention can be applied to both a vertical electric field driving method and a horizontal electric field driving method. The upper polarizing film 16a is attached to the upper substrate of the liquid crystal panel 2, and the lower polarizing film 16b is attached to the lower substrate of the liquid crystal panel 2.

The gate driver 4 operates according to the gate control signal GCS provided from the timing controller 10. As illustrated in FIG. 4, the gate driver 4 sequentially supplies a scan signal Scan to the first gate lines GL1 in each frame period. In the blank period after each frame period, the reset signal Reset is simultaneously applied to the second gate lines GL2, and then the write signal Write is simultaneously applied to the third gate lines GL3.

The data driver 6 operates in accordance with the data control signal DCS provided from the timing controller 10. The data driver 6 latches the image data RGB provided from the timing controller 10 and converts the latched data into a data voltage using a gamma voltage. The converted data voltage is supplied to the plurality of data lines DL. The data driver 6 may convert the polarity of the data voltage into a line inversion scheme, a column inversion scheme, a dot inversion scheme, a vertical two-dot inversion scheme, and supply the data voltage to the data line DL.

The common voltage supply unit 8 generates a common voltage Vcom and supplies it to the common line CL of the liquid crystal panel 2. The common voltage supplying unit 8 supplies a common voltage Vcom to each pixel, but supplies a voltage opposite to the polarity of the data voltage supplied to each pixel. To this end, the common voltage supply unit 8 may generate the first and second common voltages Vcom1 and Vcom2 having polarities opposite to each other, as shown in FIG. 4. In this case, the common voltage supply unit 8 inverts the polarities of the first and second common voltages Vcom in the blank period after each frame period as the data voltage supplied to each pixel is inverted in units of frames. However, the common voltage supply unit 8 inverts the polarities of the first and second common voltages Vcom after the write signal Write is output in the blank period. Therefore, even if the polarity of the common voltage Vcom is varied, the vertical luminance deviation of the liquid crystal panel 2 can be prevented.

The timing controller 10 supplies the image data RGB provided from the system to the data driver 6 in alignment with the size and resolution of the liquid crystal panel 2. The timing controller 10 generates the gate control signal GCS and the data control signal DCS using the timing synchronization signal SYNC provided from the system, and supplies them to the gate driver 4 and the data driver 6, respectively. By controlling them. The timing synchronization signal SYNC may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, a dot clock DCLK, and the like. The gate control signal GCS may be a gate start pulse, a gate shift clock, a gate output enable, or the like. The data control signal DCS may be a source start pulse, a source sampling clock, a source output enable, or the like.

Hereinafter, the structure of each pixel according to the present invention will be described in detail.

5 is an equivalent circuit diagram illustrating a pixel structure of the present invention. FIG. 6 is a plan view schematically illustrating the pixel illustrated in FIG. 5. FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG. 6.

5 and 6, each pixel of the present invention includes first to third TFTs T1 to T3, first and second storage capacitors Cst2, and a liquid crystal capacitor Clc.

The first TFT T1 supplies a data voltage provided from the data line DL to the memory electrode 26 (FIG. 6) in response to a scan signal Scan applied to the first gate line GL1. To this end, as shown in FIG. 7, the first TFT T1 includes a gate electrode 14 connected to the first gate line GL1, a gate insulating film 12 covering the gate electrode 14, and a gate. The semiconductor layer 20 and the ohmic contact layer 30 formed on the insulating layer 12 and formed in an island shape in the region overlapping the gate electrode 14, and formed on the semiconductor layer 20 and the data line ( A source electrode 22 connected to the DL and a drain electrode 24 facing the source electrode 22 with the gate electrode 14 therebetween are provided.

The first storage capacitor Cst1 is connected to the memory electrode 26 to store the data voltage Vdata applied to the memory electrode 26. To this end, the first storage capacitor Cst1 is connected to the drain electrode 24 of the first TFT T1 and overlaps the protrusion 16 of the next common line CL with the gate insulating layer 12 therebetween. The next stage common electrode connected to the memory electrode 26 and the protrusion 16 of the next stage common line CL through the contact hole 36 and overlaps the memory electrode 26 with the protective layer 32 therebetween. 34 is provided. According to an exemplary embodiment of the present invention, the capacitance of the first storage capacitor Cst1 can be sufficiently secured by disposing the next common electrode 34 and the protrusion 16 of the common line CL on the upper and lower portions of the memory electrode 26. The reliability of the data voltage to be stored in the first storage capacitor Cst1 can be secured.

The second TFT T2 receives the common voltage Vcom applied from the common line CL to the common electrode 34 from the common line CL in response to the reset signal Reset applied to the second gate line GL2. To feed. The second TFT T2 initializes the pixel by setting the voltage difference between the common electrode 34 and the pixel electrode 38 to be '0' when the reset signal Reset is applied.

The third TFT T3 supplies the data voltage stored in the first storage capacitor Cst1 to the pixel electrode 38 in response to the write signal Write applied to the third gate line GL3.

The second storage capacitor Cst2 is connected to the pixel electrode 38 to stably maintain the voltage applied to the pixel electrode 38. The second storage capacitor Cst2 may be formed by overlapping the pixel electrode 38 and the common electrode 34 with the gate insulating layer 12 and the protective layer 32 interposed therebetween.

The liquid crystal capacitor Clc is formed of the pixel electrode 38 and the common electrode 34 and the liquid crystal therebetween. 6 and 7, the pixel electrode 38 and the common electrode 34 are provided on the lower substrate of the liquid crystal panel 2 to form a horizontal electric field. However, the pixel electrode 38 and the common electrode ( 34 may form a vertical electric field.

Hereinafter, the driving method of each pixel according to the present invention will be described in detail with reference to FIGS. 4 and 5.

First, in each frame period, the gate driver 4 sequentially supplies a scan signal Scan to the first gate lines GL1. The data driver 6 supplies a data voltage to the data lines DL in synchronization with the scan signal Scan. Then, in each of the plurality of pixels, the first TFT T1 is turned on so that the data voltage supplied to the data line DL is applied to the memory electrode 26 through the first TFT T1. The data voltage applied to the memory electrode 26 is temporarily stored in the first storage capacitor Cst1. At this time, the data voltage of the previous frame is maintained in the pixel electrode 38.

Subsequently, in the blank period after each frame period, the gate driver 4 simultaneously applies the reset signal Reset to the second gate lines GL2. Then, in each of the plurality of pixels, the second TFT T2 is turned on, and the common voltage Vcom supplied to the common electrode 34 is applied to the pixel electrode 38 through the second TFT T2. Then, the voltage of the pixel electrode 38 is initialized to the common voltage Vcom from the data voltage of the previous frame. As a result, the voltage difference between the common electrode 34 and the pixel electrode 38 becomes '0', so that an electric field is generated in the liquid crystal. Not formed (see 't1 period' in Fig. 4).

Subsequently, in the blank period after each frame period, the gate driver 4 simultaneously applies the write signal Write to the third gate lines GL3. Then, in each of the plurality of pixels, the third TFT T3 is turned on, and the data voltage stored in the first storage capacitor Cst1 is applied to the pixel electrode 38 through the third TFT T3. Then, the pixel electrode 38 forms a horizontal electric field or a vertical electric field with the common electrode 34 according to the data voltage to vary the liquid crystal movement (see 't2 period' in FIG. 4).

Then, in the blank period after each frame period, the common voltage supply unit 8 inverts the polarity of the first and second common voltages Vcom after the write signal Write is output from the gate driver 4. At this time, the voltage of the pixel electrode 38 for each pixel is coupled according to the change of the common voltage, but the time point at which the data voltage is applied to the pixel electrode 38 for each pixel is the same, so that the conventional liquid crystal panel 2 There is no luminance deviation between the upper end and the lower end ('t3 period' in Fig. 4).

As described above, the present invention sequentially supplies data voltages to all the pixels during each frame period, and allows each pixel to temporarily store the supplied data voltages, and then, in the blank period after each frame period, all the pixels By simultaneously applying the stored data voltage to the pixel electrode, it is possible to prevent the vertical brightness deviation of the liquid crystal panel caused by the AC drive of the common voltage.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

2: liquid crystal panel 4: gate driver
6: data driver 8: common voltage supply
10: timing controller 16: protrusion of common line
26: memory electrode 34: common electrode
38: pixel electrode 36: contact hole

Claims (7)

A plurality of pixels connected to the first to third gate lines and the data lines;
Each pixel is
A first switching element for supplying a data voltage provided from the data line to the memory electrode in response to a scan signal applied to the first gate line;
A first storage capacitor connected to the memory electrode to store the data voltage;
A second switching element configured to supply a common voltage applied to the common electrode from the common line to the pixel electrode in response to a reset signal applied to the second gate line;
A third switching element configured to supply the data voltage stored in the first storage capacitor to the pixel electrode in response to a write signal applied to a third gate line;
A second storage capacitor connected to the pixel electrode to store the data voltage;
In each frame period, as the scan signal is sequentially applied to the first gate lines, the data voltage is stored in the first storage capacitor for each pixel.
In the blank period after each frame period, as the reset signal is simultaneously applied to the second gate lines, the common voltage is supplied to the pixel electrode of each pixel to convert the voltage of each pixel electrode to the common voltage. And the data voltage stored in the first storage capacitor for each pixel is supplied to the pixel electrode of each pixel as the write signal is simultaneously applied to the third gate lines, and then the polarity of the common voltage is inverted. Liquid crystal display device characterized in that. The method according to claim 1,
The common electrode forms a horizontal electric field together with the pixel electrode. The method according to claim 2,
The first storage capacitor
A memory electrode connected to the first switching element and overlapping the next common line with a first insulating layer interposed therebetween;
And a common electrode connected to the next common line through a contact hole and overlapping the memory electrode with a second insulating layer interposed therebetween. The method according to claim 1,
The common electrode forms a vertical electric field together with the pixel electrode. The method according to claim 1,
The polarity of the common voltage is opposite to the polarity of the data voltage. A plurality of pixels connected to the first to third gate lines and the data lines; Each pixel comprises: a first switching element for supplying a data voltage provided from the data line to the memory electrode in response to a scan signal applied to the first gate line; A first storage capacitor connected to the memory electrode to store the data voltage; A second switching element configured to supply a common voltage applied to the common electrode from the common line to the pixel electrode in response to a reset signal applied to the second gate line; A third switching element configured to supply the data voltage stored in the first storage capacitor to the pixel electrode in response to a write signal applied to a third gate line; A method of driving a liquid crystal display device, comprising: a second storage capacitor connected to the pixel electrode to store the data voltage;
Sequentially applying the scan signal to the first gate lines in each frame period, and storing the data voltage in the first storage capacitor for each pixel;
In the blank period after each frame period, the reset signal is simultaneously applied to the second gate lines to supply the common voltage to the pixel electrode of each pixel to initialize the voltage of each pixel electrode to the common voltage. And simultaneously applying the write signal to the third gate lines to supply the data voltage stored in the first storage capacitor for each pixel to the pixel electrode of each pixel, and then reverse the polarity of the common voltage. Method of driving a liquid crystal display device comprising a. The method according to claim 6,
Inverting the polarity of the common voltage is such that the polarity of the common voltage is opposite to the polarity of the data voltage.

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