KR102031201B1 - Latency control circuit and semiconductor memory device including the same - Google Patents

Abstract

A circuit for controlling latency and a semiconductor memory device including the same, comprising: an internal command generator for generating an internal command in response to an external command, and an external clock delayed by an operation delay amount of the internal command generator; A clock delay unit for generating the command, a command synchronizer for generating a synchronization command by sequentially synchronizing an internal command with an internal clock and an external clock to compensate for an operation delay amount of the internal command generator, and a synchronization command based on an external clock. Provided is a latency control circuit having a latency shifting unit configured to shift by a set number of latency.

Description

LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a circuit for controlling latency and a semiconductor memory device including the same.

BACKGROUND OF THE INVENTION A semiconductor memory device used as a main memory in a computer system inputs data into or outputs data from a memory cell. The data input / output speed of a semiconductor memory device is a very important factor in determining the operating speed of a computer system. In order to improve the operation speed of the semiconductor memory device, a synchronous dynamic random access memory device (SDRAM) in which internal circuits are controlled in synchronization with a clock signal generated from a computer system has been used.

In general, a synchronous semiconductor memory device (SDRAM) uses a column address strobe (CAS) function to increase an operating frequency. The cas latency represents the number of cycles of an external clock until a data is output to the outside after a read command is applied to the synchronous semiconductor memory device. The synchronous semiconductor memory device reads data internally in response to a read command, and then outputs data after a clock cycle corresponding to cas latency. For example, when the cas latency is 8, data is output to the outside in synchronization with the external clock 8 clock cycles after the external clock to which the read command is applied.

The latency control circuit generates a latency control signal that is an output control signal in order to control the output data to be output after a set clock cycle in the synchronous semiconductor memory device. In other words, the latency control circuit serves as an output control circuit. The data output buffer of the synchronous semiconductor memory device outputs data in response to an output clock signal while the latency control signal is activated. Therefore, the latency control circuit must provide the latency control signal after a read command is applied, but before a predetermined cycle of the output clock signal according to the cas latency.

The latency control signal is generated because the internal read command signal generated by decoding the read command is latched by the output clock signal and the clock signals delaying the read command. Typically, the pulse width of the internal read command signal corresponds to one period of the external clock, and the output clock signal is generated in response to a delay locked loop (DLL) clock generated through a delay locked loop, and Have the same frequency.

1 is a block diagram illustrating a latency control circuit of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a latency control circuit of a semiconductor memory device according to the related art includes a delay locked loop 100, an internal command generator 110, a command variable delay unit 150, and a latency shifting unit 160. ), A buffer unit 170, and an output control unit 180. Here, the delay locked loop 100 includes a delay replication model unit 102, a phase comparison unit 104, a delay amount control unit 106, and a DLL variable delay unit 108. The internal command generating unit 110 also includes a command decoding unit 114 and an additional latency shifting unit 116. In addition, the buffer unit 170 includes a clock buffer unit 172 and a command buffer unit 174.

The buffer unit 170 generates an external clock ICLK and an external command ICMD by buffering the clock CLK and the command CMD applied from the outside. At this time, the clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1. Similarly, the externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1.

The delay lock loop 100 is configured to reflect the delay amount tD1 + tD6 of the clock delay path to the delay lock clock DLLCLK to achieve a delay lock between the feedback clock FBCLK and the external clock ICLK. Variable delay (ICLK) is output as a delay locked clock (DLLCLK).

The internal command generator 110 generates the internal command ICMD_A in response to the external command ICMD. In addition, the command decoding unit 114 of the components of the internal command generating unit 110 decodes the external command ICMD to generate the decoding command ICMD_C. In addition, the additional latency shifting unit 116 among the components of the internal command generator 110 may shift the internal command (Additive Latency AL) by shifting the decoding command ICMD_C to the decoding command ICMD_C based on the external clock ICLK. ICMD_A). At this time, the external command ICMD and the internal command ICMD_A have a phase difference equal to the operation delay amount tD2 of the internal command generator 110.

The command variable delay unit 150 delays the internal command ICMD_A by the variable delay amount tD3 of the delay locked loop 100 and outputs it as the variable delay command ICMD_R.

The latency shifting unit 160 shifts the variable delay command ICMD_R by the CAS latency (CL) or the CAS write latency (CWL) based on the delay lock clock (DLLCLK). LT_CON).

The output controller 180 controls the data output IN_DATA-> TX_DATA in response to the latency control signal LT_CON and the delay lock clock DLLCLK.

FIG. 2 is a timing diagram illustrating an operation and a problem of a latency control circuit of the semiconductor memory device according to the related art shown in FIG. 1.

Referring to FIG. 2, the latency control circuit of the semiconductor memory device according to the related art decreases the latency margin as the operating frequency of the clock CLK applied from the outside increases.

First, the operation of a latency control circuit of a semiconductor memory device according to the related art in a state where an operating frequency of an external clock CLK is relatively low is as follows.

The clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1.

The externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1.

The external clock ICLK and the delay locked clock DLLCLK have a phase difference by the variable delay amount tD3.

The external command ICMD and the internal command ICMD_A have a phase difference by the operation delay amount tD2 of the internal command generation unit 110. In this case, the internal command generation unit 110 includes a command decoding unit 114 and an additional latency shifting unit 116. However, since the additional latency AL is assumed to be 0 in the drawing, the internal command generation unit 110 may be used. The operation delay amount tD2 may be regarded as a delay amount caused by the decoding operation of the command decoding unit 114.

The internal command ICMD_A and the variable delay command ICMD_R have a phase difference by the variable delay amount tD3.

The latency control signal LT_CON is generated by shifting the variable delay command ICMD_R by the CAS latency CL or the CAS write latency CWL based on the delay lock clock DLLCLK. At this time, shifting the variable delay command ICMD_R based on the delay locked clock DLLCLK detects and transmits the logic level of the variable delay command ICMD_R in the logic 'high' section of the delay locked clock DLLCLK. It means the way.

Accordingly, as shown in the drawing, the frequency of the clock CLK applied from the outside becomes a low frequency so that the logic 'high' section of the delay lock clock DLLCLK and the variable delay command ICMD_R In a state where logic 'low' sections overlap sufficiently, a latency shift operation may be performed without any problem.

The operation of the latency control circuit of the semiconductor memory device according to the related art in the state in which the operating frequency of the clock CLK applied from the outside is relatively high is as follows.

The clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1.

The externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1.

The external clock ICLK and the delay locked clock DLLCLK have a phase difference by the variable delay amount tD3.

The external command ICMD and the internal command ICMD_A have a phase difference by the operation delay amount tD2 of the internal command generation unit 110. In this case, the internal command generation unit 110 includes a command decoding unit 114 and an additional latency shifting unit 116. However, since the additional latency AL is assumed to be 0 in the drawing, the internal command generation unit 110 may be used. The operation delay amount tD2 may be regarded as a delay amount caused by the decoding operation of the command decoding unit 114.

The internal command ICMD_A and the variable delay command ICMD_R have a phase difference by the variable delay amount tD3.

The latency control signal LT_CON is generated by shifting the variable delay command ICMD_R by the CAS latency CL or the CAS write latency CWL based on the delay lock clock DLLCLK. At this time, shifting the variable delay command ICMD_R based on the delay locked clock DLLCLK detects and transmits the logic level of the variable delay command ICMD_R in the logic 'high' section of the delay locked clock DLLCLK. It means the way.

However, as shown in the drawing, the frequency of the clock CLK applied from the outside becomes high frequency, so that the logic 'high' section of the delay lock clock DLLCLK and the variable delay command ICMD_R In a state where logic 'low' sections do not overlap sufficiently, a latency shift operation may not be performed normally.

As described above, as the frequency of the clock CLK applied from the outside increases, the margin between the variable delay command ICMD_R applied to the latency shifting unit 160 and the delay locked clock DLLCLK decreases. You lose. That is, when the frequency of the clock CLK applied from the outside increases, in general, the pulse width of the variable delay command ICMD_R corresponding to one cycle 1tck of the clock CLK also decreases, thereby delaying fixed. A problem may occur in which the phase of the clock DLLCLK is earlier than the variable delay command ICMD_R. Also, considering that the variable delay command ICMD_R is a clock (CLK) domain and a delay locked clock (DLLCLK) domain, skew occurs between each other depending on frequency, ambient pressure, and temperature. The likelihood of the same problem occurring can also increase significantly.

In this way, if the margin between the variable delay command ICMD_R and the delay locked clock DLLCLK becomes small or the phase of the delay locked clock DLLCLK is earlier than the pulse width of the variable delay command ICMD_R, the variable delay command Since the ICMD_R is not normally latched, a problem may occur in which proper shifting may not be performed according to the CAS latency or the CAS write latency CWL.

The present invention relates to a circuit for controlling latency that can stably perform a latency shifting operation regardless of a change in frequency, and a semiconductor memory device including the same.

That is, the present invention relates to a circuit for controlling latency that can stably perform a latency shifting operation even when a clock frequency is relatively low as well as a relatively high frequency, and a semiconductor memory device including the same.

According to an aspect of the present invention for achieving the above object, an internal command generation unit for generating an internal command in response to an external command; A clock delay unit configured to delay an external clock by an operation delay amount of the internal command generator to generate an internal clock; A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator; And a latency shifting unit configured to shift the synchronization command by a set number of times of latency based on the external clock.

According to another aspect of the present invention for achieving the problem to be solved, variable delay the external clock to achieve a delay between the clock and the external clock generated by reflecting the delay amount of the clock delay path in the delay lock clock A delay lock loop outputting the delay lock clock as the delay lock clock; An internal command generator for generating an internal command in response to the external command; A clock delay unit configured to delay the external clock by an operation delay amount of the internal command generator to generate an internal clock; A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator; A command variable delay unit for delaying the synchronization command by a variable delay amount of the delay locked loop; A latency shifting unit configured to generate a latency control signal by shifting the output command of the variable delay unit based on the delay locked clock by a set latency; And an output controller configured to control data output in response to the latency control signal and the delay locked clock.

According to another aspect of the present invention for achieving the above object, the external clock is variable to achieve a delay between the external clock and the feedback clock generated by reflecting the delay amount of the clock delay path in the delay lock clock A delay locked loop for delaying and outputting the delay locked clock; A duty compensator for correcting the duty ratio of the delay locked clock and outputting the duty ratio as a duty correction clock; An internal command generator for generating an internal command in response to the external command; A command variable delay unit generating a variable delay command by delaying the internal command by a variable delay amount of the delay locked loop; A clock delay unit configured to delay the duty compensation clock by an amount of a delay obtained by subtracting an operation delay amount of the duty correction unit from an operation delay amount of the internal command generator; A command synchronizing unit generating a synchronizing command by sequentially synchronizing the variable delay command with the internal clock and the duty compensation clock to compensate for an operation delay amount of the internal command generating unit; A latency shifting unit configured to generate a latency control signal by shifting the synchronization command by a set latency based on the duty compensation clock; And an output controller configured to control data output in response to the latency control signal and the duty cycle correction clock.

The present invention described above adds a circuit for compensating for the delay amount of the command decoder which is an asynchronous element to the clock during the command transfer path, so that the interval between the clock and the command used for latency shifting is always based on the clock period. It is effective to maintain a constant interval.

Accordingly, there is an effect that the latency shifting operation can be stably performed regardless of the frequency of the clock, that is, the clock frequency is relatively low as well as relatively high.

1 is a block diagram illustrating a latency control circuit of a semiconductor memory device according to the prior art.
FIG. 2 is a timing diagram illustrating an operation and a problem of a latency control circuit of the semiconductor memory device according to the related art shown in FIG. 1.
3 is a block diagram illustrating a latency control circuit according to an embodiment of the present invention.
4 is a diagram illustrating in detail a clock delay unit and a command synchronizer among components of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.
FIG. 5 is a timing diagram illustrating an operation of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.
6 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a first embodiment of the present invention.
FIG. 7 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.
FIG. 8 is a timing diagram illustrating an operation of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.
9 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention.
FIG. 10 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention illustrated in FIG. 9.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

3 is a block diagram illustrating a latency control circuit according to an embodiment of the present invention.

Referring to FIG. 3, a latency control circuit according to an embodiment of the present invention may include an internal command generator 310, a clock delay unit 320, a command synchronizer 340, a latency shifting unit 360, And a buffer unit 370. Here, the buffer unit 370 includes a clock buffer unit 372 and a command buffer unit 374. In addition, the internal command generator 310 includes a command decoder 314 and an additional latency shifting unit 316.

The buffer unit 370 buffers the clock CLK and the command CMD applied from the outside to generate the external clock ICLK and the external command ICMD. In detail, the buffer unit 370 may include the clock delay unit 320, the additional latency shifting unit 316, and the latency shifting unit 360 generated from the external clock ICLK generated by buffering an externally applied clock CLK. Clock buffer unit 372 for transmitting to the internal command generation unit 310 and an external command ICMD generated by buffering an external command CMD. . At this time, the clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1. Similarly, the externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1. That is, the clock buffer unit 372 and the command buffer unit 374 each have an operation delay amount equal to the buffering delay amount tD1.

The command generator 310 generates the internal command ICMD_A in response to the external command ICMD. The command decoding unit 314 of the components of the command generating unit 310 decodes the external command ICMD to generate the decoding command ICMD_C. In addition, the additional latency shifting unit 316 among the components of the command generator 310 may shift the internal command ICMD_A by shifting the decoding command ICMD_C by an additional latency AL based on the external clock ICLK. ) At this time, the external command ICMD and the internal command ICMD_A have a phase difference equal to the operation delay amount tD2 of the command generator 310. For reference, the additional latency AL generally refers to the time from the input of the row address to the timing at which the column address is input in the semiconductor memory device. However, the latency control circuit according to the embodiment of the present invention can be applied to not only a general semiconductor memory device but also a semiconductor device that operates synchronously. Therefore, the additional latency shifting unit 316 disclosed in FIG. 3 is only a configuration for applying a latency value, which can be arbitrarily added by the designer according to the operation of the semiconductor device, to the operation of the latency control circuit. You can choose.

The clock delay unit 320 generates the internal clock DCLK [1: N] by delaying the external clock ICLK by the operation delay amount tD2 of the internal command generator 310. Here, although there is only one external clock applied to the clock delay unit 320, it can be seen that there are N internal clocks DCLK [1: N] output from the clock delay unit 320. This is because the clock delay unit 320 sequentially delays the external clock ICLK to generate N internal clocks DCLK [1: N]. For example, if the external clock ICLK is the same clock as the first internal clock DCLK [1], the first internal clock DCLK [1] is delayed by a set first delayed amount, so that the second internal clock DCLK [ 2]) and delay the second internal clock DCLK [2] by the set second delay amount to generate the third internal clock DCLK [3]. Will be generated). In this case, N is set to a natural number larger than 2, and the phase difference between the external clock ICLK and the Nth internal clock DCLK [N] is determined by the internal command generator 310 regardless of the value of N. It should correspond to the operation delay amount tD2. That is, the delay amount of the clock delay unit 320 should be in the same state as the operation delay amount tD2 of the internal command generator 310.

The command synchronizer 340 sequentially processes the internal command ICMD_A to the internal clock DCLK [1: N] and the external clock ICLK to compensate for the operation delay amount tD2 of the internal command generator 310. To generate a synchronization command ICMD_S. At this time, the command synchronizer 340 synchronizes the internal command ICMD_A to the Nth internal clock DCLK [N] of the N internal clocks DCLK [1: N], and then the Nth internal clock DCLK [ N]) and the first internal clock DCLK [1 having the same phase as the external clock ICLK in such a manner that the internal command ICMD_A synchronized to the N-1 th internal clock DCLK [N-1] is synchronized again. : N]) generates a synchronization command ICMD_S by sequentially synchronizing.

The latency shifting unit 360 generates the latency control signal LT_CON by shifting the synchronization command ICMD_S by a set latency number LASHIFT based on the external clock ICLK. At this time, the set latency count LASHIFT is the number of times TTGSHIFT minus N (TGSHIFT-N). Here, the target latency count TGSHIFT means a target latency value to be latency shifted by the latency control circuit. For example, in the semiconductor memory device, this refers to a cas latency value CL or a cas write latency value CWL. The reason why the latency shifting unit 360 performs the latency shifting only by the set number of delays LASHIFT, that is, the number of times TTGSHIFT minus N (TGSHIFT-N) of the synchronization command ICMD_S is a command. This is because N latency shifting operations are performed while the synchronization unit 340 compensates for the delay amount of the internal command generator 310. That is, the internal command ICMD_A and the synchronization command ICMD_S have a phase difference of N periods based on the external clock ICLK, and the latency shifting unit 360 compensates for the phase difference as much as the final phase. The latency control signal LT_CON generated as described above is in a state of shifting latency by a target latency count TGSHIFT compared to the external command ICMD.

4 is a diagram illustrating in detail a clock delay unit and a command synchronizer among components of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.

Referring to FIG. 4, the clock delay unit 320 of the components of the latency control circuit according to an exemplary embodiment of the present invention delays the external clock ICLK stepwise to N internal clocks DCLK [1: N]. You can see that it produces

Specifically, since the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is assumed to be the same clock as the external clock ICLK, the delay element included in the clock delay unit 320 is included. The number of (322 <1: N-1>) becomes N-1.

In this case, the N-1 delay elements 322 <1: N-1> included in the clock delay unit 320 may have the same delay amount or may have different delay amounts, respectively, by the designer's selection. have. but. The sum of the delay amounts of the N-1 delay elements 322 <1: N-1> included in the clock delay unit 320 should be the size of the operation delay amount tD2 of the command generator 310. do.

The command synchronizer 340 includes N flip-flops 342 <1: N>. Here, the first flip-flop 342 <1> signals the internal command ICMD_A applied to the signal input terminal D in response to the Nth internal clock DCLK [N] applied to the clock input terminal C. To the output (Q). Subsequently, the second flip-flop 342 <2> receives the first flip applied to the signal input terminal D in response to the N-1 th internal clock DCLK [N-1] applied to the clock input terminal C. The command FCM [1] carried on the signal output terminal Q of the flop 342 <1> is transmitted to the signal output terminal Q. The N-th flip-flop 342 <N> is connected to the N-th flip-flop 342 <N> in the same manner as the first flip-flop 342 <1> and the second flip-flop 342 <2>. The synchronizing command ICMD_S is output to the signal output terminal Q of.

FIG. 5 is a timing diagram illustrating an operation of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.

Referring to FIG. 5, in the latency control circuit according to an exemplary embodiment of the present invention, the interval between the synchronization command ICMD_S and the external clock ICLK applied to the latency shifting unit 360 is always based on the external clock ICLK. It can be seen that it becomes a half clock cycle (1/2 tck). For reference, in the timing diagram illustrated in FIG. 5, it can be seen that the operation of the latency control circuit is performed under the assumption that N is 3.

It can be seen that the external clock ICLK is delayed in steps to generate a total of three internal clocks DCLK [1: 3] at intervals equal to the operation delay amount tD2 of the command generator 310. That is, the first internal clock DCLK [1] having the same phase as the external clock ICLK, the second internal clock DCLK [2] and the second internal clock DCLK [which delay the external clock ICLK are delayed. A second internal clock DCLK [3] is generated, which delays 2]). At this time, the phase difference between the first internal clock DCLK [1] and the third internal clock DCLK [3] having the same phase as that of the external clock ICLK is determined by the operation delay amount tD2 of the command generator 310. Corresponds to.

The internal command ICMD_A output from the command generator 310 is output as the first synchronization command FCM [1] in response to the third internal clock DCLK [3]. That is, during the period in which the internal command ICMD_A is input, it is output as the first synchronization command FCM [1] for one period 1tck at the time corresponding to the rising edge of the third internal clock DCLK [3].

Subsequently, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, in the period in which the first synchronization command FCM [1] is input, the second synchronization command FCM [2] for one period 1tck at the time corresponding to the rising edge of the second internal clock DCLK [2]. Is output as

Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, during the period in which the second synchronization command FCM [2] is input, the third synchronization command ICMD_S is output for one period 1tck at the time corresponding to the rising edge of the first internal clock DCLK [1]. do.

In this case, since the first internal clock DCLK [1] has the same phase as the external clock ICLK, it can be seen that the third synchronization command ICMD_S is synchronized with the external clock ICLK.

Accordingly, it can be seen that the interval between the synchronization command ICMD_S applied to the latency shifting unit 360 and the external clock ICLK is always a half clock period (1/2 tck) based on the external clock ICLK. It can be seen that the characteristic remains constant even when the frequency of the external clock ICLK becomes faster or slower.

In summary, in the latency control circuit according to the embodiment of the present invention, an operation for compensating an operation delay amount of the command generator 310, which can be regarded as an asynchronous element of the clock, in the command transfer path is latency. By controlling the shifting operation to be performed before the shifting operation, a constant interval may be maintained based on the clock cycle between the latency shifting clock and the command at the time when the latency shifting operation is performed. Therefore, the latency shifting operation can be stably performed regardless of whether the frequency of the clock is changed, that is, not only when the clock frequency is relatively low but also when the clock is relatively high.

6 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a first embodiment of the present invention.

Referring to FIG. 6, a semiconductor memory device including a latency control circuit according to a first embodiment of the present invention may include a delay locked loop 600, an internal command generator 610, a clock delay unit 620, and a delay delay loop 600. And a command synchronization unit 640, a command variable delay unit 650, a latency shifting unit 660, a buffer unit 670, and an output control unit 680. Here, the delay locked loop 600 includes a delay replication model unit 602, a phase comparison unit 604, a delay amount control unit 606, and a DLL variable delay unit 608. The buffer unit 670 also includes a clock buffer unit 672 and a command buffer unit 674. In addition, the internal command generator 610 includes a command decoder 614 and an additional latency shifting unit 616.

The buffer unit 670 buffers the clock CLK and the command CMD applied from the outside to generate the external clock ICLK and the external command ICMD. In detail, the buffer unit 670 may include the clock delay unit 620, the additional latency shifting unit 616, and the latency shifting unit 660 to generate the external clock ICLK generated by buffering an externally applied clock CLK. Clock buffer unit 672 for transmitting to the internal command generating unit 610, and a command buffer unit 672 for transmitting the external command ICMD generated by buffering an external command CMD. . At this time, the clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1. Similarly, the externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1. That is, the clock buffer unit 672 and the command buffer unit 674 each have an operation delay amount equal to the buffering delay amount tD1.

The delay lock loop 100 is configured to reflect the delay amount tD1 + tD6 of the clock delay path to the delay lock clock DLLCLK to achieve a delay lock between the feedback clock FBCLK and the external clock ICLK. Variable delay (ICLK) is output as a delay locked clock (DLLCLK). That is, the external clock ICLK and the delay locked clock DLLCLK have a phase difference equal to the variable delay amount tD3. For reference, the detailed configuration and operation of the delay lock loop 600 is already known and will not be described in more detail herein.

The command generator 610 generates the internal command ICMD_A in response to the external command ICMD. The command decoding unit 614 of the components of the command generating unit 610 decodes the external command ICMD to generate the decoding command ICMD_C. In addition, the additional latency shifting unit 616 among the components of the command generator 610 may shift the internal command ICMD_A by shifting the decoding command ICMD_C by an additional latency AL based on the external clock ICLK. ) At this time, the external command ICMD and the internal command ICMD_A have a phase difference equal to the operation delay amount tD2 of the command generator 610. For reference, the additional latency AL generally refers to the time from the input of the row address to the timing at which the column address is input in the semiconductor memory device.

The clock delay unit 620 generates the internal clock DCLK [1: N] by delaying the external clock ICLK by the operation delay amount tD2 of the internal command generator 610. Here, it can be seen that there is only one external clock ICLK applied to the clock delay unit 620, but there are N internal clocks DCLK [1: N] output from the clock delay unit 620. This is because the clock delay unit 620 gradually delays the external clock ICLK to generate N internal clocks DCLK [1: N]. For example, if the external clock ICLK is the same clock as the first internal clock DCLK [1], the first internal clock DCLK [1] is delayed by a set first delayed amount, so that the second internal clock DCLK [ 2]) and delay the second internal clock DCLK [2] by the set second delay amount to generate the third internal clock DCLK [3]. Will be generated). At this time, N is set to a natural number greater than 2, and the phase difference between the external clock ICLK and the Nth internal clock DCLK [N] is determined by the internal command generator 610 regardless of the value of N. It should correspond to the operation delay amount tD2. That is, the delay amount of the clock delay unit 620 should be equal to the operation delay amount tD2 of the internal command generator 610.

The command synchronizer 640 sequentially processes the internal command ICMD_A to the internal clock DCLK [1: N] and the external clock ICLK to compensate for the operation delay amount tD2 of the internal command generator 610. To generate a synchronization command ICMD_S. At this time, the command synchronizer 640 synchronizes the internal command ICMD_A to the Nth internal clock DCLK [N] of the N internal clocks DCLK [1: N], and then the Nth internal clock DCLK [ N]) and the first internal clock DCLK [1 having the same phase as the external clock ICLK in such a manner that the internal command ICMD_A synchronized to the N-1 th internal clock DCLK [N-1] is synchronized again. : N]) generates a synchronization command ICMD_S by sequentially synchronizing.

The command variable delay unit 650 delays the synchronization command ICMD_S by the variable delay amount tD3 of the delay lock loop 600 and outputs it as the variable delay command ICMD_R. That is, in order to correspond to the delay locked clock DLLCLK generated by delaying the external clock ICLK through the delay locked loop 600 by the variable delay amount tD3, the synchronization command ICMD_S is converted into the variable delay amount tD3. It delays by and outputs it as a variable delay command (ICMD_R).

The latency shifting unit 660 shifts the variable delay command ICMD_R by a set latency number LASHIFT based on the delay lock clock DLLCLK to generate the latency control signal LT_CON. At this time, the set latency number LASHIFT is the number of subtractions N (CLSHIFT-N or CWLSHIFT-N) from the target latency number CLSHIFT or CWLSHIFT. Here, the target latency number CLSHIFT or CWLSHIFT means a target latency value that should be shifted by the latency control circuit. In other words, it refers to the cascade latency CL value CLSHIFT or the caswrite latency CWL value CWLSHIFT used in the semiconductor memory device. Then, the latency shifting unit 660 performs the latency shifting only by the number of times the internal command ICMD_A is subtracted from the set number of delays LASHIFT, that is, the number of times the target latency CLSHIFT or CWLSHIFT is subtracted from N (CLSHIFT-N or CWLSHIFT-N). The reason for performing this is because N latency shifting operations are performed in the process of compensating for the delay amount of the internal command generator 610 in the command synchronizer 640. That is, the internal command ICMD_A and the synchronization command ICMD_S have a phase difference of N periods based on the external clock ICLK, and the latency shifting unit 660 compensates for the phase difference as much as the final phase. The latency control signal LT_CON generated as described above is in a state of shifting latency by the target number of times CLSHIFT or CWLSHIFT compared to the external command ICMD.

The output control unit 680 controls the data output IN_DATA-> TX_DATA in response to the latency control signal LT_CON and the delay lock clock DLLCLK. That is, the internal data IN_DATA output from the inside of the semiconductor memory device starts to be output as the external data TX_DATA in response to the latency control signal LT_CON, and in response to the delay lock clock DLLCLK, the burst length: The number of internal data IN_DATA corresponding to BL is sequentially output as the external data TX_DATA.

FIG. 7 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.

Referring to FIG. 7, the clock delay unit 620 of the components of the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6 delays the external clock ICLK stepwise. It can be seen that N internal clocks DCLK [1: N] are generated.

Specifically, since the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is assumed to be the same clock as the external clock ICLK, the delay elements included in the clock delay unit 620 are included. The number of (622 <1: N-1>) becomes N-1.

In this case, the N-1 delay elements 622 <1: N-1> included in the clock delay unit 620 may have the same delay amount or may have different delay amounts, respectively, by the designer's selection. have. but. The sum of the delay amounts of the N-1 delay elements 622 <1: N-1> included in the clock delay unit 620 should be the size of the operation delay amount tD2 of the command generator 610. do.

The command synchronizer 640 includes N flip-flops 642 <1: N>. Here, the first flip-flop 642 <1> signals the internal command ICMD_A applied to the signal input terminal D in response to the Nth internal clock DCLK [N] applied to the clock input terminal C. To the output (Q). Subsequently, the second flip-flop 642 <2> is the first flip applied to the signal input terminal D in response to the N-1 th internal clock DCLK [N-1] applied to the clock input terminal C. The command FCM [1] loaded on the signal output terminal Q of the flop 642 <1> is transmitted to the signal output terminal Q. Nth flip-flop (642 <N>) is connected to N-th flip-flop (642 <N>) in the same way as the first flip-flop (642 <1>) and the second flip-flop (642 <2>). The synchronizing command ICMD_S is output to the signal output terminal Q of.

FIG. 8 is a timing diagram illustrating an operation of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.

Referring to FIG. 8, in the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention, an interval between the variable delay command ICMD_R and the delay locked clock DLLCLK applied to the latency shifting unit 660 is provided. It can be seen that a half clock cycle (1/2 tck) is always made based on the delay lock clock DLLCLK. For reference, the timing diagram shown in FIG. 8 shows that the operation of the latency control circuit is performed under the assumption that N is 3. FIG.

It can be seen that the external clock ICLK is delayed in steps to generate a total of three internal clocks DCLK [1: 3] at intervals equal to the operation delay amount tD2 of the command generator 610. That is, the first internal clock DCLK [1] having the same phase as the external clock ICLK, the second internal clock DCLK [2] and the second internal clock DCLK [which delay the external clock ICLK are delayed. A second internal clock DCLK [3] is generated, which delays 2]). At this time, the phase difference between the first internal clock DCLK [1] and the third internal clock DCLK [3] having the same phase as the delay locked clock DLLCLK is determined by the operation delay amount tD2 of the command generator 610. )

The internal command ICMD_A output from the command generator 610 is output as the first synchronization command FCM [1] in response to the third internal clock DCLK [3]. That is, during the period in which the internal command ICMD_A is input, it is output as the first synchronization command FCM [1] for one period 1tck at the time corresponding to the rising edge of the third internal clock DCLK [3].

Subsequently, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, in the period in which the first synchronization command FCM [1] is input, the second synchronization command FCM [2] for one period 1tck at the time corresponding to the rising edge of the second internal clock DCLK [2]. Is output as

Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, during the period in which the second synchronization command FCM [2] is input, the third synchronization command ICMD_S is output for one period 1tck at the time corresponding to the rising edge of the first internal clock DCLK [1]. do.

In this case, since the first internal clock DCLK [1] has the same phase as the external clock ICLK, it can be seen that the third synchronization command ICMD_S is synchronized with the external clock ICLK.

The delay lock clock DLLCLK is a clock generated by delaying the external clock ICLK by the variable delay amount tD3, and the variable delay command ICMD_R delays the third synchronization command ICMD_S by the variable delay amount tD3. The third synchronization command ICMD_S and the delay lock clock DLLCLK are also synchronized.

Accordingly, it can be seen that the interval between the variable delay command ICMD_R and the delay locked clock DLLCLK applied to the latency shifting unit 660 is always a half clock cycle (1/2 tck) based on the delay locked clock DLLCLK. It can be seen that this is a characteristic that is kept constant even when the frequency of the delay locked clock (DLLCLK) is faster or slower.

In summary, the latency control circuit according to the above-described embodiment of the present invention has an operation for compensating an operation delay amount of the command generator 610, which can be regarded as an asynchronous element of the clock, in the command transfer path. By controlling the shifting operation to be performed before the shifting operation, a constant interval may be maintained based on the clock cycle between the latency shifting clock and the command at the time when the latency shifting operation is performed. Therefore, the latency shifting operation can be stably performed regardless of whether the frequency of the clock is changed, that is, not only when the clock frequency is relatively low but also when the clock is relatively high.

9 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention.

Referring to FIG. 9, a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention includes a delay locked loop 900, an internal command generator 910, a clock delay unit 920, and a delay delay loop 900. And a command synchronizer 940, a command variable delay unit 950, a latency shifting unit 960, a buffer unit 970, an output control unit 980, and a duty cycle correction unit 990. Here, the delay locked loop 900 includes a delay replication model unit 902, a phase comparison unit 904, a delay amount control unit 906, and a DLL variable delay unit 908. In addition, the buffer unit 970 includes a clock buffer unit 972 and a command buffer unit 974. The internal command generator 910 also includes a command decoder 914 and an additional latency shifting unit 916. The duty compensator 990 also includes a duty ratio adjuster 992 and a clock driver 994.

The buffer unit 970 buffers the clock CLK and the command CMD applied from the outside to generate the external clock ICLK and the external command ICMD. In detail, the buffer unit 970 may convert the external clock ICLK generated by buffering an externally applied clock CLK into a clock delay unit 920, an additional latency shifting unit 916, and a latency shifting unit 960. Clock buffer unit 972 for transmitting to the internal command generation unit 910 and an external command ICMD generated by buffering an external command CMD. . At this time, the clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1. Similarly, the externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1. That is, the clock buffer unit 972 and the command buffer unit 974 each have an operation delay amount equal to the buffering delay amount tD1.

The delay lock loop 100 is configured to reflect the delay amount tD1 + tD6 of the clock delay path to the delay lock clock DLLCLK to achieve a delay lock between the feedback clock FBCLK and the external clock ICLK. Variable delay (ICLK) is output as a delay locked clock (DLLCLK). That is, the external clock ICLK and the delay locked clock DLLCLK have a phase difference equal to the variable delay amount tD3. For reference, the detailed configuration and operation of the delay lock loop 900 is already known and will not be described in more detail herein.

The internal command generator 910 generates the internal command ICMD_A in response to the external command ICMD. The command decoding unit 914 of the components of the internal command generation unit 910 decodes the external command ICMD to generate the decoding command ICMD_C. In addition, the additional latency shifting unit 916 among the components of the internal command generator 910 may shift the internal command by shifting the decoding command ICMD_C by an additional latency AL based on the external clock ICLK. ICMD_A). At this time, the external command ICMD and the internal command ICMD_A have a phase difference equal to the operation delay amount tD2 of the internal command generator 910. For reference, the additional latency AL generally refers to the time from the input of the row address to the timing at which the column address is input in the semiconductor memory device.

The command variable delay unit 950 delays the internal command ICMD_A by the variable delay amount tD3 of the delay lock loop 900 and outputs it as the variable delay command ICMD_R. That is, the internal command ICMD_A is assigned to the variable delay amount tD3 to correspond to the delay lock clock DLLCLK generated by the external clock ICLK being delayed by the variable delay amount tD3 while passing through the delay lock loop 900. It delays by and outputs it as a variable delay command (ICMD_R).

The duty cycle correcting unit 990 corrects the duty ratio of the delay locked clock DLLCLK and outputs it as a duty correction clock DCCCLK. At this time, the delay lock clock DLLCLK and the duty compensation clock DCCCLK have a phase difference equal to the operation delay amount tD5 of the duty cycle corrector 990.

When the external command ICMD output through the command buffer unit 974 included in the buffer unit 970 is a clock enable command CKE, the operation of the duty cycle correction unit 990 is turned on / on in response to the external command ICMD. Are controlled off.

That is, in the general semiconductor memory device, after determining that the clock enable command is CKE through the command decoding unit 914 included in the internal command generation unit 310, the operation of the duty cycle correction unit 990 is turned on in response to the determination. Control on / off. However, in the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention, the duty compensator in response to the external command ICMD output through the command buffer unit 974 included in the buffer unit 970 is provided. By controlling the on / off operation of 990, the operation of the duty compensator 990 can be controlled on / off faster than a general semiconductor memory device.

As such, the purpose of turning on / off the operation of the duty cycle corrector 990 faster than that of a general semiconductor memory device is to provide a clock delay which is a key component of a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention. The unit 920, the command synchronizer 940, and the latency shifting unit 960 operate in response to the duty compensation clock DCCCLK, and the command variable delay unit 950 is connected to the internal command generator 910. This is because they are disposed between the command synchronization units 940. That is, since the command variable delay unit 950 is disposed between the internal command generator 910 and the command synchronizer 940, when the operation of the duty compensator 990 is controlled as in a general semiconductor memory device, The operation of compensating for the operation delay amount tD2 of the internal command generator 910 in the clock delay unit 920 and the command synchronizer 940 may overlap with the operation period of the duty compensator 990. Therefore, an operation of controlling the duty correction unit 990 to be performed in the operation section of the internal command generator 910 is necessary.

In addition, the clock delay unit 920, the command synchronization unit 940, and the latency shifting unit 960, which are core components of the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention, are duty-corrected. The effect that can be expected because the command variable delay unit 950 is disposed between the internal command generator 910 and the command synchronizer 940 while operating in response to the clock DCCCLK is the clock delay unit 920. And the delay amount tD2 ?? tD5 obtained by subtracting the operation delay amount tD5 of the duty compensator 990 from the operation delay amount tD2 of the internal command generator 910. ). That is, the delay amount delayed until the external clock ICLK becomes the duty correction clock DCCCLK is determined by varying the variable delay amount tD3 of the delay lock loop 900 and the operation delay amount tD5 of the duty compensator 990. The combined delay amount tD3 + tD5 and the delay amount until the external command ICMD becomes the variable delay command ICMD_R are determined by the operation delay amount tD2 and the command variable delay unit of the internal command generator 910. Since the delay amount tD2 + tD3 is the sum of the delay amount tD3 of 950, the difference in the delay amount between the duty compensation clock DCCCLK and the variable delay command ICMD_R is determined by the operation delay amount of the internal command generator 910. It can be seen that (tD2) becomes a delay amount (tD2? tD5) obtained by subtracting the operation delay amount (tD5) of the duty cycle corrector (990). Therefore, the delay amount to be compensated for by the clock delay unit 920 and the command synchronization unit 940 is the operation delay amount tD5 of the duty compensator 990 from the operation delay amount tD2 of the internal command generator 910. Is the delayed amount (tD2 ?? tD5).

Referring to this matter, the clock delay unit 920 sets the duty cycle correction clock DCCCLK to the operation delay amount tD5 of the duty cycle correction unit 990 from the operation delay amount tD2 of the internal command generator 910. The internal clock DCLK [1: N] is generated by delaying the delayed amount (tD2 ?? tD5) by subtracting. Here, although the duty correction clock DCCCLK applied to the clock delay unit 920 is one, it can be seen that there are N internal clocks DCLK [1: N] output from the clock delay unit 920. This is because the clock delay unit 920 delays the duty compensation clock DCCCLK stepwise to generate N internal clocks DCLK [1: N]. For example, if the duty-correction clock DCCCLK is the same clock as the first internal clock DCLK [1], the first internal clock DCLK [1] is delayed by a set first delayed amount so that the second internal clock DCLK [2]) and delay the second internal clock DCLK [2] by the set second delay amount to generate the third internal clock DCLK [3]. ]). In this case, N is set to a natural number greater than 2, and the phase difference between the duty compensation clock DCCCLK and the N-th internal clock DCLK [N] is internal command generator 910 regardless of the value of N. It corresponds to the delay amount tD2 ?? tD5 subtracted from the operation delay amount tD5 of the duty cycle correcting unit 990 from the operation delay amount tD2. That is, the delay amount of the clock delay unit 920 is the delay amount tD2 ?? tD5 obtained by subtracting the operation delay amount tD5 of the duty compensator 990 from the operation delay amount tD2 of the internal command generator 910. Should be in the same state as

The command synchronizer 940 compensates for the delay amount tD2 ˜ tD5 obtained by subtracting the operation delay amount tD5 of the duty compensator 990 from the operation delay amount tD2 of the internal command generator 910. The variable delay command ICMD_R is sequentially synchronized with the internal clock DCLK [1: N] and the duty compensation clock DCCCLK to generate a synchronization command ICMD_S. At this time, the command synchronization unit 940 synchronizes the variable delay command ICMD_R to the Nth internal clock DCLK [N] of the N internal clocks DCLK [1: N], and then the Nth internal clock DCLK. The first internal clock DCLK having the same phase as the duty-correction clock DCCCLK in such a manner that the internal command ICMD_A synchronized to [N]) is synchronized to the N-1 th internal clock DCLK [N-1] again. A synchronization command ICMD_S is generated by sequentially synchronizing up to [1: N]).

The latency shifting unit 960 generates the latency control signal LT_CON by shifting the synchronization command ICMD_S by a set latency number LASHIFT based on the delay lock clock DLLCLK. At this time, the set latency number LASHIFT is the number of subtractions N (CLSHIFT-N or CWLSHIFT-N) from the target latency number CLSHIFT or CWLSHIFT. Here, the target latency number CLSHIFT or CWLSHIFT means a target latency value that should be shifted by the latency control circuit. In other words, it refers to the cascade latency CL value CLSHIFT or the caswrite latency CWL value CWLSHIFT used in the semiconductor memory device. In addition, the latency shifting unit 960 shifts the variable delay command ICMD_R only by the set number of delays LASHIFT, that is, the number of subtracting N from the target latency number CLSHIFT or CWLSHIFT (CLSHIFT-N or CWLSHIFT-N). The reason for performing the above operation is the delay amount tD2 ?? tD5 obtained by subtracting the operation delay amount tD5 of the duty cycle correcting unit 990 from the operation delay amount tD2 of the internal command generation unit 910 in the command synchronization unit 940. This is because N latency shifting operations are performed in the process of compensating). That is, the variable delay command ICMD_R and the synchronization command ICMD_S have a phase difference of N periods based on the duty compensation clock DCCCLK, and the latency shifting unit 960 compensates for the phase difference by the reverse shift compensation. The finally generated latency control signal LT_CON is in a state of shifting the latency by the target number of times CLSHIFT or CWLSHIFT compared to the external command ICMD.

The output controller 980 controls the data output IN_DATA-> TX_DATA in response to the latency control signal LT_CON and the duty cycle clock DCCCLK. That is, the internal data IN_DATA output from the inside of the semiconductor memory device starts to be output as the external data TX_DATA in response to the latency control signal LT_CON, and in response to the duty compensation clock DCCCLK, the burst length: The number of internal data IN_DATA corresponding to BL is sequentially output as the external data TX_DATA.

FIG. 10 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention illustrated in FIG. 9.

Referring to FIG. 10, the clock delay unit 920 of the components of the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention shown in FIG. 9 may step-by-step the duty correction clock DCCCLK. It can be seen that the delay generates N internal clocks DCLK [1: N].

Specifically, since the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is assumed to be the same clock as the duty correction clock DCCCLK, a delay included in the clock delay unit 920 is included. The number of elements 922 <1: N-1> is N-1.

In this case, the N-1 delay elements 922 <1: N-1> included in the clock delay unit 920 may have the same delay amount or may have different delay amounts, respectively, by the designer's selection. have. but. The sum of the delay amounts of the N-1 delay elements 922 <1: N-1> included in the clock delay unit 920 is equal to the duty correction unit in the operation delay amount tD2 of the command generator 910. It should be the size of the delay amount tD2 ?? tD5 minus the operation delay amount tD5 of 990.

The command synchronizer 940 includes N flip-flops 942 <1: N>. Here, the first flip-flop 942 <1> receives the variable delay command ICMD_R applied to the signal input terminal D in response to the Nth internal clock DCLK [N] applied to the clock input terminal C. Transfer to the signal output terminal (Q). Subsequently, the second flip-flop 942 <2> is the first flip applied to the signal input terminal D in response to the N-1 th internal clock DCLK [N-1] applied to the clock input terminal C. The command FCM [1] loaded on the signal output terminal Q of the flop 942 <1> is transmitted to the signal output terminal Q. N-th flip-flop 942 <N> is connected to N-th flip-flop 942 <N> in the same manner as the first flip-flop 942 <1> and the second flip-flop 942 <2>. The synchronizing command ICMD_S is output to the signal output terminal Q of.

FIG. 11 is a timing diagram illustrating an operation of a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention illustrated in FIG. 9.

Referring to FIG. 11, in a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention, an interval between a variable delay command ICMD_R and a duty compensation clock DCCCLK applied to the latency shifting unit 960 is provided. It can be seen that a half clock period (1/2 tck) is always made based on the duty correction clock DCCCLK. For reference, the timing diagram shown in FIG. 11 shows that the operation of the latency control circuit is performed under the assumption that N is 3. FIG.

The duty correction clock DCCCLK may be delayed in steps to generate a total of three internal clocks DCLK [1: 3] at intervals equal to the operation delay amount tD2 of the command generator 910. That is, the first internal clock DCLK [1] having the same phase as the duty correction clock DCCCLK, the second internal clock DCLK [2] and the second internal clock delaying the duty compensation clock DCCCLK A third internal clock (DCLK [3]) is generated which delays DCLK [2]). At this time, the phase difference between the first internal clock DCLK [1] and the third internal clock DCLK [3] having the same phase as the duty correction clock DCCCLK is determined by the operation delay amount tD2 of the command generator 910. ) Corresponds to the delay amount tD2 ˜ tD5 minus the operation delay amount tD5 of the duty compensator 990.

The variable delay command ICMD_R output from the command variable delay unit 950 is output as the first synchronization command FCM [1] in response to the third internal clock DCLK [3]. That is, during the period in which the variable delay command ICMD_R is input, it is output as the first synchronization command FCM [1] for one period 1tck at the time corresponding to the rising edge of the third internal clock DCLK [3]. .

Subsequently, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, in the period in which the first synchronization command FCM [1] is input, the second synchronization command FCM [2] for one period 1tck at the time corresponding to the rising edge of the second internal clock DCLK [2]. Is output as

Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, during the period in which the second synchronization command FCM [2] is input, the third synchronization command ICMD_S is output for one period 1tck at the time corresponding to the rising edge of the first internal clock DCLK [1]. do.

At this time, since the first internal clock DCLK [1] has the same phase as the duty correction clock DCCCLK, it can be seen that the third synchronization command ICMD_S is synchronized with the duty compensation clock DCCCLK.

Accordingly, it can be seen that the interval between the variable delay command ICMD_R applied to the latency shifting unit 960 and the duty correction clock DCCCLK always becomes a half clock period (1/2 tck) based on the duty compensation clock DCCCLK. It can be seen that this is a characteristic that remains constant even when the frequency of the duty-correction clock (DCCCLK) is faster or slower.

In summary, in the latency control circuit according to the embodiment of the present invention, an operation for compensating an operation delay amount of the command generator 910, which can be regarded as an asynchronous element of the clock, in the command transfer path is delayed. By controlling the shifting operation to be performed before the shifting operation, a constant interval may be maintained based on the clock cycle between the latency shifting clock and the command at the time when the latency shifting operation is performed. Therefore, the latency shifting operation can be stably performed regardless of whether the frequency of the clock is changed, that is, not only when the clock frequency is relatively low but also when the clock is relatively high.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

100, 600, 900: delay locked loop
110, 310, 610, 910: internal command generation unit
320, 620, 920: clock delay unit
340, 640, 940: command synchronization unit
150, 650, 950: command variable delay unit
160, 360, 660, 960: latency shifting part
170, 370, 670, 970: buffer part
180, 680, 980: output control unit
990: duty control unit

Claims (23)

An internal command generator for decoding an external command to generate an internal command;
A clock delay unit configured to delay an external clock by an operation delay amount of the internal command generator to generate an internal clock;
A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator; And
Latency shifting unit for shifting the synchronization command by a set number of latency based on the external clock
Latency control circuit having a.
Claim 2 has been abandoned upon payment of a set-up fee. The method of claim 1,
The clock delay unit,
Delaying the external clock stepwise to generate the internal clock of N, wherein N is a natural number greater than 2, wherein a phase difference between the external clock and the Nth internal clock corresponds to an amount of operation delay of the internal command generator; Latency control circuit.
Claim 3 has been abandoned upon payment of a set-up fee. The method of claim 2,
The command synchronization unit,
The first internal clock-the external in such a manner that the internal command is synchronized with the Nth internal clock of the N internal clocks, and the command synchronized with the Nth internal clock is synchronized with the N-1th internal clock again. A latency control circuit that generates a synchronization command by sequentially synchronizing to have the same phase as a clock.
Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 3,
The command synchronization unit,
In response to the Nth internal clock applied to the clock input terminal of the first flip-flop, the internal command applied to the signal input terminal is transmitted to the signal output terminal, and the N-1th internal clock applied to the clock input terminal of the second flip-flop is provided. And the N flip-flops are provided in such a manner as to transmit a command on the signal output terminal of the first flip-flop applied to the signal input terminal in response to the signal output terminal.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3,
The set latency count is
The latency control circuit, characterized in that the number of times the number is subtracted from the target latency.
Claim 6 has been abandoned upon payment of a setup registration fee. The method of claim 1,
The internal command generation unit,
A command decoding unit which generates the internal command by decoding the external command; And
And an additional latency shifting unit configured to shift the internal command decoded based on the external clock by an additional number of latency.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6,
A command buffer unit which buffers a command applied from the outside and transfers the command to the internal command generation unit as the external command; And
And a clock buffer unit configured to buffer an externally applied clock and provide the additional latency shifting unit, the clock delay unit, and the latency shifting unit as the external clock.
A delay lock loop that variably delays the external clock and outputs the delay lock clock as a delay lock between the feedback clock and the external clock generated by reflecting the delay amount of the clock delay path in the delay lock clock;
An internal command generator for decoding an external command to generate an internal command;
A clock delay unit configured to delay the external clock by an operation delay amount of the internal command generator to generate an internal clock;
A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator;
A command variable delay unit for delaying the synchronization command by a variable delay amount of the delay locked loop;
A latency shifting unit configured to generate a latency control signal by shifting the output command of the variable delay unit based on the delay locked clock by a set latency; And
An output control unit controlling data output in response to the latency control signal and the delay lock clock
A semiconductor memory device having a.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8,
The clock delay unit,
Delaying the external clock stepwise to generate the internal clock of N, wherein N is a natural number greater than 2, wherein a phase difference between the external clock and the Nth internal clock corresponds to an amount of operation delay of the internal command generator; A semiconductor memory device.
Claim 10 has been abandoned upon payment of a setup registration fee. The method of claim 9,
The command synchronization unit,
The first internal clock-the external in such a manner that the internal command is synchronized with the Nth internal clock of the N internal clocks, and the command synchronized with the Nth internal clock is synchronized with the N-1th internal clock again. And having the same phase as a clock to sequentially generate the synchronization command.
Claim 11 was abandoned upon payment of a set-up fee. The method of claim 10,
The command synchronization unit,
In response to the Nth internal clock applied to the clock input terminal of the first flip-flop, the internal command applied to the signal input terminal is transmitted to the signal output terminal, and the N-1th internal clock applied to the clock input terminal of the second flip-flop is provided. N flip-flops are provided in such a manner as to transmit a command on the signal output terminal of the first flip-flop applied to the signal input terminal in response to the signal output terminal.
Claim 12 was abandoned upon payment of a set-up fee. The method of claim 10,
The set latency count is
And a number of times the N is subtracted from a target latency number.
Claim 13 was abandoned upon payment of a set-up fee. The method of claim 8,
The internal command generation unit,
A command decoding unit which generates the internal command by decoding the external command; And
And an additional latency shifting unit configured to shift the internal command decoded based on the external clock by an additional number of latency.
Claim 14 was abandoned upon payment of a set-up fee. The method of claim 13,
A command buffer unit which buffers a command applied from the outside and transfers the command to the internal command generation unit as the external command; And
And a clock buffer unit configured to buffer an externally applied clock to provide the delay locked loop, the additional latency shifting unit, and the clock delay unit as the external clock.
A delay lock loop that variably delays the external clock and outputs the delay lock clock as a delay lock between the feedback clock and the external clock generated by reflecting the delay amount of the clock delay path in the delay lock clock;
A duty compensator for correcting the duty ratio of the delay locked clock and outputting the duty ratio as a duty correction clock;
An internal command generator for decoding an external command to generate an internal command;
A command variable delay unit generating a variable delay command by delaying the internal command by a variable delay amount of the delay locked loop;
A clock delay unit configured to delay the duty compensation clock by an amount of a delay obtained by subtracting an operation delay amount of the duty correction unit from an operation delay amount of the internal command generator;
A command synchronizing unit generating a synchronizing command by sequentially synchronizing the variable delay command with the internal clock and the duty compensation clock to compensate for an operation delay amount of the internal command generating unit;
A latency shifting unit configured to generate a latency control signal by shifting the synchronization command by a set latency based on the duty compensation clock; And
An output control unit controlling data output in response to the latency control signal and the duty cycle correction clock;
A semiconductor memory device having a.
Claim 16 was abandoned upon payment of a set-up fee. The method of claim 15,
The clock delay unit,
Delaying the duty-correction clock stepwise to generate the internal clocks of N, wherein N is a natural number greater than 2, wherein a phase difference between the duty-correction clock and the N-th internal clock is determined by an operation delay of the internal command generator. And a delay amount corresponding to a delay amount obtained by subtracting an operation delay amount of the duty corrector.
Claim 17 was abandoned upon payment of a set-up fee. The method of claim 16,
The command synchronization unit,
Synchronizing the variable delay command to the Nth internal clock of the N internal clocks, and synchronizing the command synchronized to the Nth internal clock to the N-1th internal clock again. And having the same phase as the duty-correction clock to sequentially synchronize to generate the synchronization command.
Claim 18 was abandoned when the set registration fee was paid. The method of claim 17,
The command synchronization unit,
In response to the N-th internal clock applied to the clock input terminal of the first flip-flop, the variable delay command applied to the signal input terminal is transmitted to the signal output terminal, and the N-th internal part is applied to the clock input terminal of the second flip-flop. N flip-flops are provided in such a manner as to transfer a command on the signal output terminal of the first flip-flop applied to the signal input terminal in response to a clock to the signal output terminal.
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The set latency count is
And a number of times the N is subtracted from a target latency number.
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The internal command generation unit,
A command decoding unit which generates the internal command by decoding the external command; And
And an additional latency shifting unit configured to shift the internal command decoded based on the external clock by an additional number of latency.
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A command buffer unit which buffers a command applied from the outside and transfers the command to the internal command generation unit as the external command; And
And a clock buffer unit configured to buffer an externally applied clock and provide the external clock to the delay locked loop and the additional latency shifting unit as the external clock.
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And in response to the external command buffered through the command buffer unit being a clock enable command, the operation of the duty compensator is controlled on / off.
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The duty compensator,
A duty ratio adjusting unit receiving the delay lock clock to adjust a duty ratio thereof, the duty ratio of which is controlled on / off in response to the clock enable command; And
And a clock driver configured to drive the output clock of the duty ratio controller as the duty compensation clock to transmit the clock delay unit, the command synchronizer, the latency shifting unit, and the output controller.

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