KR102106720B1 - Method of fabricating semiconductor structure and semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor structure having a fin shape and a semiconductor device using the same. A method of manufacturing a semiconductor structure according to an embodiment of the present invention includes preparing a substrate on which a mold layer is formed; Patterning the mold layer to form a plurality of mold pin structures spaced apart from each other; And epitaxially growing the semiconductor layer using the exposed surfaces of the plurality of mold pin structures as a seed surface to form a plurality of semiconductor structures defined between adjacent mold pin structures.

Description

Method of fabricating semiconductor structure and semiconductor device

The present invention relates to a semiconductor technology, and more particularly, to a method of manufacturing a semiconductor structure having a fin shape and a semiconductor device using the same.

The semiconductor market is expanding rapidly with the development of information and communication technology and the demand for portable digital application devices such as smart phones, digital cameras, and tablet PCs. Semiconductor technology has secured a driving force for growth in the semiconductor market through scaling of integrated circuits for the past several decades. However, it is a reality that it is difficult to secure technological competitiveness only with technologies that increase density or increase capacity through scaling, and currently, performance optimization of each device is also an important issue.

In the manufacture of integrated circuit devices, a tri-gate fin-field effect transistor (tri-gate finFET) or a dual-gate fin-field effect transistor (dual-) using a three-dimensionally shaped semiconductor active layer Multi-gate transistors, such as gate finFETs, are attracting more attention in terms of performance as scaling continues, compared to flat field effect transistors. The multi-gate transistor is generally manufactured on a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The bulk silicon substrate is preferred because it can manufacture a multi-gate transistor in a low cost and less complicated method. The SOI substrate has been actively researched as an alternative technique for suppressing the parasitic effect of a multi-gate transistor to further enhance performance.

However, the multi-gate transistor formed on the above-described bulk silicon substrate or SOI substrate basically has a physical limitation in performance because it uses a group 4 based crystalline silicon active layer. In particular, as the scaling down continues to an area of less than a nanometer, while increasing the ratio of the leakage current (I _off ) to the driving current (I _on ) while maintaining the stability of the threshold voltage, high electron mobility is required to obtain high performance. A high-performance multi-gate transistor using a II-VI or III-V compound semiconductor such as GaAs, InGaAs, InAs, and InSb having a lattice constant greater than that of silicon is required. Fet) structured semiconductor devices are being studied. However, it is difficult to obtain a single crystal while minimizing defects in the compound semiconductor active layer, which is a great barrier to application of the compound semiconductor device.

U.S. Patent No. 9,698,253 B2 (2017.07.04)

The technical problem to be solved by the present invention is to provide a method for manufacturing a high-quality semiconductor structure with high electron mobility applicable as an active layer of a high-performance semiconductor device using a low-cost semiconductor substrate such as a silicon substrate.

The technical problem to be solved by the present invention is to provide a semiconductor device using a semiconductor structure having the above advantages.

A method of manufacturing a semiconductor structure according to an embodiment of the present invention for solving the above technical problem includes preparing a substrate on which a mold layer is formed; Patterning the mold layer to form a plurality of mold pin structures spaced apart from each other; And epitaxially growing the semiconductor layer using the exposed surfaces of the plurality of mold pin structures as a seed surface to form a plurality of semiconductor structures defined between adjacent mold pin structures.

After the step of forming the plurality of semiconductor structures, the step of selectively removing the plurality of mold pin structures may be further performed. The substrate may include a base substrate or an insulating layer on the base substrate.

In one embodiment, the lattice constant of the plurality of mold fin structures may be greater than the lattice constant of the substrate and less than the lattice constant of the plurality of semiconductor structures. In one embodiment, the substrate may be a substrate containing silicon or silicon germanium. The mold layer may include germanium, and the semiconductor layer may include a II-VI or III-V compound semiconductor.

In one embodiment, the plurality of semiconductor structures may have a fin shape. The epitaxially grown semiconductor layer may be overgrown onto the top surfaces of the plurality of mold pin structures, in which case the step of removing a portion of the overgrown semiconductor layer may be further performed. The overgrown semiconductor layer may be removed through an etch back or a chemical mechanical polishing process to expose the upper surface of the plurality of mold pin structures.

In one embodiment, the step of forming a first capping layer on the upper surface of the plurality of mold pin structures may be further performed. The first capping layer may include an oxide layer or a nitride layer. In another embodiment, the method further includes forming a second capping film on the exposed surface of the substrate between the plurality of mold pin structures, and the second capping film may include an oxide film or a nitride film. In this case, the plurality of semiconductor structures are respectively formed on the second capping layer, and the plurality of semiconductor structures may be transferred onto another substrate.

A semiconductor device according to an embodiment of the present invention for solving the other technical problem, the substrate; An amorphous capping film formed on the substrate; And a fin-shaped single crystal semiconductor structure epitaxially grown on the capping film. In one embodiment, the capping layer includes oxide or nitride, and the single crystal semiconductor structure may include a II-VI or III-V compound semiconductor.

According to one embodiment of the present invention, by epitaxially growing a semiconductor layer with the exposed surface of the plurality of mold pin structures as a seed surface, it is possible to form a plurality of semiconductor structures between adjacent mold pin structures, resulting in high electron mobility. It is possible to provide a method for manufacturing a high-quality semiconductor structure having a degree.

In addition, according to another embodiment of the present invention, a semiconductor device using a semiconductor structure made of a compound semiconductor suitable for a high-performance device can be provided by using a low-cost semiconductor substrate that can be economically supplied.

1A and 1B are perspective views illustrating field effect transistors using a pin-shaped half-sail structure according to various embodiments of the present invention.
2 is a flowchart illustrating a method of manufacturing a fin-shaped semiconductor structure according to an embodiment of the present invention.
3A to 3H show the process results of each step of FIG. 2.
4A to 4E are diagrams for describing a method of manufacturing a fin-shaped semiconductor structure according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, and the scope of the present invention is as follows. It is not limited to the embodiment. Rather, these embodiments are provided to make the present disclosure more faithful and complete, and to fully convey the spirit of the present invention to those skilled in the art.

In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity of description, and the same reference numerals in the drawings refer to the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the listed items.

Terms used in this specification are used to describe specific embodiments, and are not intended to limit the present invention. As used herein, singular forms may include plural forms unless the context clearly indicates otherwise. Also, as used herein, “comprise” and / or “comprising” specifies the shapes, numbers, steps, actions, elements, elements and / or the presence of these groups. And does not exclude the presence or addition of one or more other shapes, numbers, actions, elements, elements and / or groups.

1A and 1B are perspective views illustrating field effect transistors using a fin-shaped semiconductor structure 30 according to various embodiments of the present invention.

Referring to FIG. 1A, tri-gate finFETs 100A according to an embodiment of the present invention are illustrated. Each tree-gate field effect transistor may include a fin-shaped semiconductor structure 30 formed on the substrate 10. The substrate 10 may be an SOI substrate including a base substrate 11 and an insulating layer 12 formed on the base substrate 11. The base substrate 11 may include silicon, silicon germanium, or germanium, and the insulating layer 12 may include silicon oxide, germanium oxide, or a mixed compound thereof. In another embodiment, the substrate 10 may be a bulk semiconductor substrate in which the insulating layer 12 is omitted. The bulk semiconductor substrate may include silicon, silicon germanium, or germanium.

The tri-gate field effect transistor 100A includes a fin-shaped semiconductor structure 30 formed on the insulating layer 12; It may include opposing side surfaces of the semiconductor structure 30 and a single continuous conductive layer 50 disposed on the top surface. A gate insulating film 40 is formed between the semiconductor structure 30 and the continuous conductive layer 50 to provide a MOS transistor having a three-sided channel region including both side surfaces and an upper surface of the semiconductor structure 30. You can. The continuous conductive layer 50 may adjust the bias voltage for the three-sided channel region as a gate electrode, thereby providing a larger driving current compared to a flat plate MOSFET by an effective channel width increased by a three-dimensional structure. In one embodiment, by a large driving current, the tri-gate field effect transistor 100A can be applied as a switching element of an I / O circuit of a semiconductor integrated circuit.

In one embodiment, the fin-shaped semiconductor structure 30 may be used as an active layer of an integrated circuit device, such as a channel region, as described above. In one embodiment, the semiconductor structure 30 is a single crystal group 4 semiconductor such as silicon, silicon carbide, silicon germanium, germanium, or a group II-VI or group III-V single crystal compound semiconductor such as GaAs, InGaAs, InAs, and InSb. can do. In one embodiment, the semiconductor structure 30 may be a modified single crystal group 4 semiconductor or a single crystal compound semiconductor having an increased lattice constant compared to a semiconductor material having the same composition.

The height (H) and width (W) of the semiconductor structure 30 may be in the range of 5 nm to 200 nm and 5 nm to 100 nm, respectively, as non-limiting examples, and may have a cuboid structure as shown. However, the shape of the semiconductor structure 30 is not limited to the rectangular parallelepiped structure and may be variously modified through adjustment of the shape of the mold pin structure described later. The semiconductor structure 30 may be a material separate from the semiconductor material constituting the substrate 10 by transversely epitaxially growing from the mold pin structure formed on the substrate 10, in which FIGS. 3A to 3H are described. It will be disclosed in detail with reference.

In one embodiment, the semiconductor structure 30 may further include impurities through an ion implantation process to control a threshold value of the transistor. For example, in the case of an N-type finpet element, boron (B) -containing impurities may be doped in the semiconductor structure 30. Conversely, in the case of a P-type finpet element, arsenic (As) or phosphorus (P) -containing impurities may be doped in the semiconductor structure 30.

The gate insulating layer 40 formed on the semiconductor structure 30 may be formed through in-situ steam-generated oxidation (ISSG) oxidation or rapid thermal oxidation (RTP) after the semiconductor structure 50 is formed. have. However, the present invention is not limited thereto, CVD (chemical vapor deposition), LPCVD (low pressure CVD), APCVD (atmospheric pressure CVD), LTCVD (low temperature CVD), PECVD (plasma enhanced CVD), ALCVD (atomic layer CVD) ) Or a dielectric layer may be directly formed on the surface of the semiconductor structure 30 by various deposition methods such as atomic layer deposition (ALD) or physical vapor deposition (PVD) to provide the gate insulating layer 40.

The continuous conductive layer 50 formed on the side surface and the top surface of one semiconductor structures is polysilicon, or tungsten (W), tantalum (Ta), titanium nitride (TiN), zirconium nitride (ZrN), hafnium nitride (HfN) ), Vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), tungsten nitride (WN), tantalum aluminium nitride (TiAlN), tantalum carbide (TaC), tantalum magnesium carbide (TaMgC) or tantalum carbon It may be a metal such as nitride (TaCN), a conductive carbide of metal, a conductive nitride, or a mixture or a stacked structure thereof, and the present invention is not limited thereto. The width L of the continuous conductive layer 50 may be about 5 nm to 50 nm, whereby the channel length can be limited. A gate electrode is provided by the continuous conductive layer 50, and both ends of the semiconductor structure 30 spaced by the gate electrode are source and drain, respectively.

Referring to FIG. 1B, dual-gate finFETs 100B according to another embodiment of the present invention are illustrated. Each dual-gate field effect transistor may include a substrate 10 and a semiconductor structure 30, similar to the tri-gate field effect transistors 100A described above. Unlike the tri-gate field effect transistor 100A of FIG. 1A, the dual gate field effect transistor 100B has an insulating portion 45 disposed on the upper surface of the semiconductor structure 30. Insulator 45 divides the gate electrode 50 into two independent gate electrodes 50_1 and 50_2 that are electrically separated, and the two independent gate electrodes 50_1 and 50_2 share one semiconductor structure 30. Do it.

In one embodiment, the insulating portion 45 may be formed on the upper surface of the semiconductor structure 30 to cover the upper surface. When the ISSG oxidation or thermal oxidation process as described above is performed on the semiconductor structure 30 on which the insulating portion 45 is formed, the gate insulating film 40 may be formed only on the exposed side surface of the semiconductor structure 30. After the gate insulating film 40 is formed, a conductive layer to be a gate electrode is formed on the insulating portion 45 and the gate insulating film 40. Subsequently, when a mechanical planarization process is performed on the conductive layer until the upper surface of the insulating portion 45 is exposed, the gate electrodes 50_1 and 50_2 divided into two by the insulating portion 45 have a semiconductor structure ( 30).

The independent gate electrodes 50_1 and 50_2 can control the field effect transistor so that the current size in the semiconductor structure and device characteristics such as threshold voltage and sub-threshold swing are suitable for a specific application. In some embodiments, the dual gate field effect transistor can be used to dynamically adjust the characteristics of the finpet device 100B by applying a signal received from an external circuit to any of the dual gates, so it can be applied to logic devices of integrated circuits. You can.

The transistors illustrated in FIGS. 1A and 1B may be formed of only one type or in combination with each other on the same substrate, and the present invention is not limited thereto. For example, in the case of a driving circuit, the tree-gate finpet shown in FIG. 1A may be formed, and in the case of a logic circuit, the dual-gate finpet shown in FIG. In addition, a dual-gate finpet may be formed in the core logic part in one substrate, and a tri-gate finpet may be formed in the peripheral driving part as a switching element. As another example, according to an embodiment of the present invention, since the free characteristics of the semiconductor structure 30 can be adjusted, the electron mobility of the semiconductor structure can be maximized, and thus a transistor of the High Electron Mobility Transistor Device (HEMT) device can also be used.

2 is a flowchart illustrating a method of manufacturing a fin-shaped semiconductor structure according to an embodiment of the present invention, and FIGS. 3A to 3H show process results of each step of FIG. 2.

Referring to FIGS. 3A to 3C together with FIG. 2, substrates 10A, 10B, and 10C on which mold layer 13 is formed are prepared (S10). In one embodiment, the substrate 10A may be an SOI substrate including a base substrate 11 and an insulating layer 12 formed on the base substrate 11, as shown in FIG. 3A. The base substrate 11 may include silicon, silicon germanium, or germanium, and the insulating layer 12 may include silicon oxide. In other embodiments, the base substrate 11 is not limited to a semiconductor substrate, and may be any ceramic substrate or a flexible polymer substrate.

In another embodiment, the substrate 10B may be a bulk semiconductor substrate 11 in which the insulating layer 12 is omitted, as shown in FIG. 3B. The bulk semiconductor substrate 11 may include silicon, silicon germanium, or germanium.

The mold layer 13 on the substrates 10A and 10B is a single crystal layer because it provides a seed surface layer for epitaxial growth of a semiconductor structure, which will be described later. The mold layer 13 of the single crystal structure may be transferred onto the base substrate 11 shown in FIG. 3A by a wafer bonding method, or may be directly formed by epitaxial growth on the substrate 11 as shown in FIG. 3B. have. In other embodiments, the mold layer 13 itself may function as a single bulk substrate, as shown in FIG. 3C.

The mold layer 13 may be silicon, silicon germanium, or germanium. Preferably, the mold layer 30 may be germanium having a lattice constant larger than that of silicon or silicon germanium and easy to manufacture into a single crystal. When the mold layer 13 is germanium, not only can the germanium mold layer 30 be easily obtained from the silicon or silicon germanium base substrate 11, but also when forming a semiconductor structure formed of a compound semiconductor as described below The germanium may act as a buffer element for obtaining a compound semiconductor of excellent quality with few defects due to a small difference in lattice constant from the compound semiconductor.

Referring again to FIGS. 2 and 3D, the mold layer 13 may be patterned to form a plurality of mold pin structures 13F spaced apart from each other (S20). The substrate 10 of FIG. 3D is a stacked structure of the base substrate 11 and the insulating film 12 shown in FIG. 3A, the bulk substrate 11 shown in FIG. 3B, or formed of the mold layer itself as shown in FIG. 3C. It may be a bulk substrate 13. The spacing S between the plurality of mold pin structures 13F may be the same as the width of the semiconductor structure to be formed later (see W in FIGS. 1A and 1B). In one embodiment, the spacing S may be in the range of 5 nm to 100 nm.

The formation of the mold fin structures 13F can be performed by reactive ion etching (RIE) or aspect-ratio trapping as a non-limiting example, and other dry processes capable of high quality anisotropic patterns instead of these processes The mold pin structures 13F may also be formed by. In one embodiment, a capping film having an amorphous structure such as an oxide film, a nitride film, or a mixture thereof on the surface of the substrate 10 exposed between the mold fin structures 13F (see the second capping film 14b in FIG. 4A) It is also possible to passivate the exposed surface of the substrate 10 by forming. The capping layer serves as a barrier layer for preventing the semiconductor layer 30L from epitaxially growing from the surface of the substrate 10 by acting as a seed surface where the surface of the exposed substrate 10 between the plurality of mold pin structures 13F is used. Works. When the difference in lattice constant or crystal structure between the substrate 10 and the semiconductor layer (see 30L in FIG. 3E) is large, a defect may be caused in the semiconductor layer 30L to be grown, thereby excluding the effect of the substrate 10 In order to do so, the application of the capping film is preferred.

Thereafter, using the exposed surface of the mold pin structures 13F as a seed surface, as shown in FIG. 3E, a monocrystalline semiconductor layer 30L by epitaxial growth from the seed surface in the direction of arrows k ₁ and K ₂ ) May be formed (S30). The growth direction of the arrow k ₁ is the transverse (y direction) epitaxial growth with the side surface of the mold pin structures 13F as the seed surface, and the growth direction of the arrow k ₂ is the upper surface of the mold pin structures 13F. Is the epitaxial growth in the longitudinal direction (z direction) with the seed surface. The growth rate of the semiconductor layer 30L in the direction of the arrow k ₁ and the arrow k ₂ may be different from each other by factors such as atomic packing density. In FIG. 3E, it is exemplified that both directions have the same growth rate.

Considering epitaxial growth in the direction of the arrows k ₁ and k ₂ , the formed semiconductor layer 30L does not have a crystallographic relationship with the underlying substrate 10, and has only a crystallographic relationship with the mold pin structures 13F. Can have According to an embodiment of the present invention, the crystallinity of the semiconductor layer 30L depends only on the crystallographic properties of the mold fin structures 13F, for example, the crystallographic structure, preferential orientation direction and lattice constant, the substrate 10 It has nothing to do with the crystallographic properties of or can be indirectly related to the formation of the mold pin structures 13F. Accordingly, the semiconductor layer 30L is a single crystal group 4 semiconductor such as silicon, silicon carbide, silicon germanium, or germanium that can be epitaxially grown from the exposed surfaces of the mold fin structures 13F or II- such as GaAs, InGaAs, InAs, and InSb. And a group VI or III-V single crystal compound semiconductor layer. Particularly, when the mold fin structures 13F are a group 4 crystalline semiconductor having a large lattice constant such as germanium, the II-VI group or III having a large lattice constant regardless of the crystallographic properties of the underlying substrate 10 -V group single crystal compound semiconductor layer can be formed.

The semiconductor layer 30L may be formed on the mold fin structures 13F by a method such as molecular beam epitaxy capable of epitaxial growth, chemical vapor deposition, or atomic layer deposition. When epitaxial growth of the semiconductor layer 30L continues, the semiconductor layer 30L fills all the space between the side surfaces of the mold fin structures 13F, as shown in FIG. 3F, and the mold pin structures Overgrowth may also occur on the top surface of (13F).

In one embodiment, a portion of the overly grown semiconductor layer 30L over the top surface of the mold fin structures 13F may be removed. For example, the overgrown semiconductor layer 30L can be removed until the top surface of the mold fin structures 13F is exposed, as shown in FIG. 3G. Thereby, the semiconductor layer 30L may remain in the space between the side surfaces of the mold fin structures 13F, that is, a region defined between adjacent mold fin structures. In one embodiment, removal of the overgrown semiconductor layer 30L may be performed through an etchback or chemical mechanical polishing process (CMP), and the present invention is not limited thereto.

Thereafter, the plurality of mold pin structures 13F on the substrate 10 may be selectively removed (S40). The selective removal of the plurality of mold pin structures 13F may be performed by wet etching using an etch ratio between the mold pin structures 13F and the semiconductor structures 30, and the present invention is not limited thereto. . As a result, fin-shaped semiconductor structures 30 may be formed on the substrate 10 as shown in FIG. 3H. As described above, the crystallinity of the semiconductor structures 30 depends only on the crystallographic properties of the removed mold pin structures 13F and may not have a relationship with the substrate 10. Therefore, it is not possible to obtain a high-quality compound semiconductor by epitaxial growth directly from a conventional silicon substrate, but according to the embodiment of the present invention, high-quality semiconductor structures 30 can be obtained according to the selection and quality of mold fin structures. .

In another aspect, according to an embodiment of the present invention, the mold pin structures 13F may function as a buffer layer to form semiconductor structures 30 while eliminating or minimizing the dependence of the substrate 11. Since the semiconductor structures 30 are not formed directly from the substrate 10 and the semiconductor structures 30 can be formed from the plurality of mold pin structures 13F, the material of the mold pin structures 13F which is a buffer layer The crystallinity and quality of the semiconductor structures 30 can be determined only by selecting.

In one embodiment, the lattice constant of the mold fin structures 13F may be greater than the lattice constant of the substrate 11 and less than the lattice constant of the semiconductor structures 30. In this case, the mold fin structures 13F can cancel the large difference between the lattice constant of the substrate 11 and the lattice constant between the semiconductor structures 30 to form crystalline semiconductor structures 30 without defects. Can act as a buffer element. For example, economically-supplied, for example, silicon substrate 10 and mold pin structures 13F of, for example, germanium, having a lattice constant greater than that of silicon substrate 10 as a buffer layer. Using the lower substrate, fin-shaped semiconductor structures 30 made of a compound semiconductor suitable for a high-performance device according to a larger lattice constant than the mold fin structures 13F may be formed.

4A to 4E are diagrams for describing a method of manufacturing a fin-shaped semiconductor structure according to another embodiment of the present invention. Among the illustrated components, the components having the same reference numerals as those of the above-mentioned drawings may be referred to the above-mentioned disclosure unless contradicted.

4A, a substrate 10 on which a plurality of mold pin structures 13F spaced apart from each other is formed is provided. Reference may be made to the foregoing disclosure regarding the substrate 10. In one embodiment, the upper surface of the plurality of mold pin structures 13F may be passivated by the first capping film 14a. Therefore, the upper surface of the plurality of mold pin structures 13F does not act as the seed surface of the semiconductor layer 30L to be epitaxially grown. The first capping film 14a may be an amorphous insulating film such as an oxide film, a nitride film, a mixture thereof, or a laminated structure thereof, and the present invention is not limited thereto.

In another embodiment, the second capping layer 14b may be formed on the surface of the exposed substrate 10 between the plurality of mold pin structures 13F. The second capping layer 14b blocks epitaxial growth of the semiconductor layer 30L from the substrate 10 between the plurality of mold pin structures 13F. Such epitaxial growth may cause defects in the semiconductor layer 30L when the difference in crystallographic properties between the substrate 10 and the semiconductor layer 30L is large, and thus may act as a barrier to these barriers. Both the first capping film 14a and the second capping film 14b may be implemented or only one of them may be selectively implemented.

Referring to FIG. 4B, only the exposed side surface of the mold pin structures 13F is limited to the seed surface by the first capping film 14a, and the arrow k ₁ direction from the seed surface, that is, the transverse epi. A monocrystalline semiconductor layer 30L may be formed by tactical growth). As shown in FIG. 3E, the growth of the semiconductor layer in the direction of the arrow k _{2 using} the upper surface of the mold fin structures 13F as a seed surface can be suppressed by the first capping film 14a.

The semiconductor layer 30L is continuously epitaxially grown on the mold fin structures 13F by a method such as molecular beam epitaxy capable of epitaxial growth, chemical vapor deposition, or atomic layer deposition, as shown in FIG. 4C. , The semiconductor layer 30L will fill all the spaces between the side surfaces of the mold fin structures 13F.

Thereafter, as illustrated in FIG. 4D, the first capping layer 14a formed on the mold pin structures 13F may be removed. When the semiconductor layer 30L is overgrown over the upper surface of the mold fin structures 13F, a planarization process such as the above-described etch-back or chemical mechanical polishing process for removing it may be performed, and during the planarization process, a first The capping film 14a may be removed.

Thereafter, the plurality of mold pin structures 13F on the substrate 10 may be selectively removed. The selective removal of the plurality of mold pin structures 13F may be performed by wet etching using an etch ratio between the mold pin structures 13F and the semiconductor structures 30, and the present invention is not limited thereto. . In the above-described embodiment, the first capping film 14a was removed through a planarization process as a non-limiting example before removing the mold pin structures 13F, but the embodiment of the present invention is not limited thereto. For example, through removal of the mold pin structures 13F without directly removing the first capping film 14a, the first capping film 14a is lifted-off with the mold pin structures 13F. It may be removed.

When the plurality of mold fin structures 13F are removed, fin-shaped semiconductor structures 30 may be formed on the substrate 10 as illustrated in FIG. 4E. When the second capping film 14b is applied, a second capping film 14b may be disposed between each semiconductor structure 30 and the substrate 10. The second capping layer 14b may insulate the semiconductor structures 30 from the substrate 10 to serve as an additional role of blocking the body effect from the substrate 10 or leakage current from the substrate 10. In another embodiment, the semiconductor structures 30 formed on the second capping film 14b are separated from the second capping film 14b by a wafer bonding method or between the second capping film 14b and the substrate 10 By separating, it can be transferred onto another substrate and utilized for device formation on a separate substrate.

Thereafter, as described with reference to FIGS. 1A and 1B, a gate insulating layer and a gate electrode may be sequentially formed on a side surface and / or an upper surface of the semiconductor structure 30. As a result, a semiconductor device using the above-described semiconductor structures 30 as a tri-gate transistor or a channel layer of a dual gate as an active layer can be provided.

As described above, according to an embodiment of the present invention, the crystallinity of the semiconductor structures 30 depends only on the crystallographic properties of the removed mold pin structures 13F and may not have a relationship with the substrate 10. have. Accordingly, the semiconductor structures 30 are not epitaxially grown directly from the substrate 11 but the semiconductor structures 30 from the plurality of mold pin structures 13F via the plurality of mold pin structures 13F. Since it is formed, it is possible to improve the selectivity and crystallinity of the feasible material of the semiconductor structures 30 only by selecting the material and quality of the mold fin structures 13F as the buffer layer.

Further, according to an embodiment of the present invention, economically supplyable, for example, silicon substrate 11 and buffer layer having a lattice constant greater than that of silicon substrate 11, for example, mold pin structures of germanium By using the lower substrate including (13F), pin-shaped semiconductor structures 30 made of a compound semiconductor suitable for a high-performance device may be formed because it has a larger lattice constant than the mold fin structures 13F.

In the above-described embodiments, the case where the mold pin structures 20 are removed is disclosed, but the embodiment of the present invention is not limited thereto, and the mold pin structures 20 may be integrated with or remain with the formed semiconductor structure, and thus It could be used as part.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the technical spirit of the present invention. It will be clear to those who have knowledge.

Claims (14)

Preparing a substrate on which a single crystal mold layer is formed;
Patterning the mold layer to form a plurality of mold pin structures spaced apart from each other;
Epitaxially growing a semiconductor layer comprising a single crystal compound semiconductor using the exposed surfaces of the plurality of mold fin structures as a seed surface to form a plurality of semiconductor structures having a fin shape defined between adjacent mold fin structures; And
And selectively removing the plurality of mold pin structures to remain at least a portion of the plurality of semiconductor structures between the plurality of mold pin structures.
A method of manufacturing a semiconductor structure in which a difference between the lattice constant of the substrate and the lattice constant of the plurality of remaining semiconductor structures is canceled by the lattice constant of the plurality of mold fin structures.
According to claim 1,
The plurality of semiconductor structures is a method of manufacturing a semiconductor structure that is utilized as a channel layer of a tri-gate transistor or a dual gate transistor. According to claim 1,
The substrate is a method of manufacturing a semiconductor structure including a base substrate or an insulating layer on the base substrate. According to claim 1,
A method of manufacturing a semiconductor structure in which the lattice constant of the plurality of mold fin structures is greater than the lattice constant of the substrate and less than the lattice constant of the plurality of semiconductor structures. According to claim 1,
The substrate is a method of manufacturing a semiconductor structure that is a substrate containing silicon or silicon germanium. The method of claim 5,
The mold layer includes germanium,
The semiconductor layer is a method of manufacturing a semiconductor structure comprising a II-VI or III-V compound semiconductor. delete According to claim 1,
The epitaxially grown semiconductor layer is overgrown on top surfaces of the plurality of mold pin structures,
And removing a portion of the overgrown semiconductor layer. The method of claim 8,
The overgrown semiconductor layer is a method of manufacturing a semiconductor structure that is removed through an etch back or a chemical mechanical polishing process so that the upper surface of the plurality of mold pin structures is exposed. According to claim 1,
Further comprising the step of forming a first capping film on the upper surface of the plurality of mold pin structures,
The first capping film is a method of manufacturing a semiconductor structure including an oxide film or a nitride film. According to claim 1,
Forming a second capping layer on the exposed surface of the substrate between the plurality of mold pin structures,
The second capping film is a method of manufacturing a semiconductor structure including an oxide film or a nitride film. The method of claim 11,
The plurality of semiconductor structures are respectively formed on the second capping film,
A method of manufacturing a semiconductor structure in which the plurality of semiconductor structures are transferred onto different substrates. As a semiconductor device,
Board;
An amorphous capping film formed on the substrate; And
It includes a semiconductor structure including a pin-shaped single crystal compound semiconductor epitaxially grown on the capping film,
The difference between the lattice constant of the substrate and the lattice constant of the fin-shaped single crystal semiconductor structure is canceled by the lattice constant of the plurality of mold fin structures. The method of claim 13,
The capping film includes oxide or nitride,
The single crystal semiconductor structure is a semiconductor device comprising a group II-VI or III-V compound semiconductor.

Images