KR102141015B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device capable of high-speed operation. In addition, a highly reliable semiconductor device is provided. A channel forming region, a source region and a drain region are formed in the semiconductor layer by using an oxide semiconductor having crystallinity in the semiconductor layer of the transistor. The source region and the drain region are formed by using a channel protective layer as a mask, and one or a plurality of elements of rare gas or hydrogen are applied to the semiconductor layer by ion doping or ion implantation.

Description

Semiconductor device and manufacturing method of semiconductor device {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

It relates to a semiconductor device having a circuit including a semiconductor element such as a transistor and a method of manufacturing the same. For example, a power device mounted on a power supply circuit, a semiconductor integrated circuit including a memory, a thyristor, a converter, an image sensor, etc., an electro-optical device typified by a liquid crystal display panel, a light emitting display device having a light emitting element, etc. are mounted as parts. It relates to an electronic device.

In addition, in the present specification, a semiconductor device refers to an overall device capable of functioning by using semiconductor characteristics, and all electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices are semiconductor devices.

As represented by a liquid crystal display device, a transistor formed on a glass substrate or the like is made of amorphous silicon, polycrystalline silicon, or the like. Transistors using amorphous silicon have low field effect mobility, but can cope with a large area of a glass substrate. Further, the mobility of the field effect of a transistor using polycrystalline silicon is high, but it has a drawback that it is not suitable for large-sized glass substrates.

With respect to transistors using silicon, a technique of manufacturing a transistor using an oxide semiconductor and applying it to an electronic device or an optical device has attracted attention. For example, a technique in which a transistor is manufactured using zinc oxide and an In—Ga—Zn-based oxide as an oxide semiconductor and used in a switching element of a pixel of a display device is disclosed in Patent Documents 1 and 2.

In Patent Document 3, in a staggered transistor using an oxide semiconductor, an oxide semiconductor containing nitrogen with high conductivity is formed as a buffer layer between a source region and a drain region and a source electrode and a drain electrode, thereby forming an oxide semiconductor and A technique for reducing contact resistance of source and drain electrodes has been disclosed.

In addition, in Non-Patent Document 1, an oxide semiconductor transistor is disclosed in which a resistivity of an oxide semiconductor in a portion thereof is reduced to a source region and a drain region by a self-matching process in which argon plasma treatment is performed on an exposed oxide semiconductor.

However, in this method, by performing an argon plasma treatment by exposing the surface of the oxide semiconductor, the oxide semiconductor of the portion to be the source region and the drain region is also etched at the same time to thin the source region and the drain region (Non-Patent Document 1). See Figure 8). As a result, the resistance of the source region and the drain region increases, and the probability of occurrence of defective products due to over etching accompanying thinning also increases.

This phenomenon becomes remarkable when the atomic radius of the ionic species used for plasma treatment of the oxide semiconductor is large.

Of course, if the oxide semiconductor layer has a sufficient thickness, it does not matter, but when the channel length is 200 nm or less, the thickness of the oxide semiconductor layer at the portion of the channel to prevent short-channel effects is 20 nm or less, preferably 10 nm or less. Is required. When such a thin oxide semiconductor layer is handled, plasma treatment as described above is not preferable.

Patent Document 1: Japanese Patent Publication No. 2007-123861 Patent Document 2: Japanese Patent Publication No. 2007-96055 Patent Document 3: Japanese Patent Publication No. 2010-135774

Non-Patent Document 1: S. Jeon et al. "180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application", IEDM Tech. Dig., p. 504, 2010.

Another object of the present invention is to provide a semiconductor device capable of high-speed operation.

Another object of the present invention is to provide a semiconductor device using a transistor in which fluctuations in electrical characteristics due to short-channel effects are unlikely to occur.

Another object of the present invention is to provide a semiconductor device that is easy to refine by forming a source region and a drain region by a self-matching process.

Another object of the present invention is to provide a semiconductor device in which the contact resistance between the source electrode and the drain electrode can be reduced and the on-state current is improved by forming the source region and the drain region having lower resistance than the channel portion.

Another object of the present invention is to provide a highly reliable semiconductor device.

An aspect of the present invention has a gate electrode, a gate insulating layer, an oxide semiconductor layer having crystallinity, a channel protective layer, a gate insulating layer is formed on the gate electrode, and an oxide semiconductor layer is formed on the gate insulating layer. A channel protective layer is formed on the oxide semiconductor layer, and the oxide semiconductor layer has a first oxide semiconductor region and a pair of second oxide semiconductor regions, and the pair of second oxide semiconductor regions comprises a first oxide semiconductor region. The semiconductor device is formed by interposing and overlapping the gate electrode with the gate insulating layer interposed therebetween and in contact with the channel protective layer.

In addition, an aspect of the present invention has an oxide semiconductor layer having a crystallinity, a gate insulating layer, and a gate electrode, and the oxide semiconductor layer has a first oxide semiconductor region and a pair of second oxide semiconductor regions, The pair of second oxide semiconductor regions is formed with the first oxide semiconductor region interposed therebetween, and the first oxide semiconductor region is a semiconductor device characterized by overlapping the gate electrode with the gate insulating layer interposed therebetween.

A non-single crystal semiconductor is used for the oxide semiconductor layer.

The first oxide semiconductor region has CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). CAAC-OS, while the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of CAAC-OS, and also has a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab plane. , has a crystal part in which metal atoms are arranged in a layer shape or metal atoms and oxygen atoms are arranged in a layer shape when viewed from a direction perpendicular to the c-axis.

The second oxide semiconductor region contains at least one element of rare gas or hydrogen (H) at a concentration of 5×10 ¹⁹ atoms/cm ³ or more and 1×10 ²² atoms/cm ³ or less.

The oxide semiconductor may include two or more elements selected from In, Ga, Sn and Zn.

The first oxide semiconductor region becomes the channel formation region of the transistor, and the pair of second oxide semiconductor regions becomes the source region and the drain region of the transistor.

In the transistor of the bottom gate structure, the source region and the drain region can be formed by adding a dopant to the oxide semiconductor layer using the channel protective layer as a mask. The channel protective layer is formed to protect the back channel portion of the active layer, and it is preferable to use a material selected from silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or the like in a single layer or by lamination.

In the transistor of the top gate structure, the source region and the drain region can be formed by adding a dopant to the oxide semiconductor layer using the gate electrode as a mask.

As the dopant for forming the source region and the drain region of the transistor, an ion doping method, an ion implantation method, or the like can be used. As the dopant, one kind or a plurality of elements of rare gas or hydrogen (H) can be used. In addition, when a dopant is added to the oxide semiconductor layer by ion doping or ion implantation, excess damage to the oxide semiconductor layer in addition of the dopant can be reduced by adding the dopant through the insulating layer to the oxide semiconductor layer. Can. In addition, since the interface between the oxide semiconductor layer and the insulating layer is kept clean, the characteristics and reliability of the transistor are improved. Further, the depth (addition region) of the dopant can be easily controlled, and the dopant can be accurately added to the oxide semiconductor layer.

When the concentration of the dopant to be added increases, the carrier density of the oxide semiconductor region can be increased, but if the concentration of the dopant to be added is too high, the movement of the carrier is inhibited and conductivity is reduced.

By using the oxide semiconductor to which the dopant is added to the source region and the drain region, the effect of reducing the curvature of the band end of the channel formation region where the dopant is not added is exhibited. On the other hand, when the source region and the drain region are formed of a metal material, the bending of the band end of the channel, which is the oxide semiconductor region, cannot be neglected, and the effective channel length may be shortened. This tendency is more pronounced as the channel length of the transistor is shorter.

The highly purified oxide semiconductor (purified OS) in which impurities such as moisture or hydrogen, which become an electron donor (donor) is reduced, then supplies oxygen to the oxide semiconductor, thereby reducing oxygen deficiency in the oxide semiconductor to form an i-type (intrinsic semiconductor). ) Or an i-type oxide semiconductor (substantially i-type). Therefore, a transistor using an i-type or substantially i-type oxide semiconductor in a semiconductor layer on which a channel is formed has a characteristic that the off current is remarkably low. Specifically, in the highly purified oxide semiconductor, a measurement value of hydrogen concentration by secondary ion mass spectrometry (SIMS) is less than 5×10 ¹⁸ /cm ³ , preferably 1×10 ¹⁸ /cm ³ Hereinafter, it is more preferably 5×10 ¹⁷ /cm ³ or less, and even more preferably 1×10 ¹⁶ /cm ³ or less. In addition, the carrier density of the i-type or substantially i-type oxide semiconductor layer that can be measured by Hall effect measurement is less than 1×10 ¹⁴ /cm ³ , preferably less than 1×10 ¹² /cm ³ , more preferably Is less than 1×10 ¹¹ /cm ³ . Further, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using an i-type or substantially i-type oxide semiconductor in the semiconductor layer on which the channel is formed, the off-state current of the transistor can be lowered.

Here, SIMS analysis of the hydrogen concentration in the oxide semiconductor is mentioned. SIMS analysis has been found to be difficult in principle to accurately obtain data in the vicinity of a sample surface or in the vicinity of a laminated interface with a film having a different material. Therefore, when the distribution in the thickness direction of the hydrogen concentration in the film is analyzed by SIMS, the average value in the region in which there is no extreme fluctuation in the value in the range where the target film is present and an almost constant value is obtained is adopted as the hydrogen concentration. do. In addition, when the thickness of the film to be measured is small, there may be cases where it is not possible to find a region where an almost constant value is obtained under the influence of the hydrogen concentration in the adjacent film. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film is present is adopted as the hydrogen concentration in the film. In addition, in the region where the film is present, when an acid peak having a maximum value and a curved peak having a minimum value do not exist, the value of the inflection point is adopted as the hydrogen concentration.

According to one aspect of the present invention, it is possible to provide a semiconductor device using an oxide semiconductor having good electrical properties and easy to refine.

Further, a semiconductor device in which fluctuations in electrical characteristics are unlikely to occur due to a short channel effect is provided.

Further, by adding a dopant in the oxide semiconductor through the insulating layer, the thinning of the oxide semiconductor is prevented, and the interface between the oxide semiconductor and the insulating layer is kept clean, thereby improving the characteristics and reliability of the semiconductor device.

1 is a top view and a cross-sectional view illustrating one aspect of the present invention.
2 is a top view and a cross-sectional view illustrating one aspect of the present invention.
3 is a cross-sectional view illustrating one aspect of the present invention.
4 is a cross-sectional view illustrating one aspect of the present invention.
5 is a top view and a cross-sectional view illustrating one aspect of the present invention.
6 is a top view and a cross-sectional view illustrating one aspect of the present invention.
7 is a cross-sectional view illustrating one aspect of the present invention.
8 is a cross-sectional view illustrating one aspect of the present invention.
It is a figure explaining the band structure of an oxide semiconductor and a metal material.
10 is a circuit diagram for explaining an aspect of the present invention.
11 is a circuit diagram for explaining an aspect of the present invention.
12 is a circuit diagram for explaining an aspect of the present invention.
13 is a circuit diagram for explaining an aspect of the present invention.
14 is a block diagram showing a specific example of the CPU and a circuit diagram of a part thereof.
It is a figure explaining the crystal structure of an oxide material.
It is a figure explaining the crystal structure of an oxide material.
It is a figure explaining the crystal structure of an oxide material.
It is a figure explaining the crystal structure of an oxide material.

EMBODIMENT OF THE INVENTION The embodiment of this invention is described in detail using drawing. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that various forms and details can be changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the contents described in the embodiments described below. In addition, in the structure of the present invention described below, the same reference numerals are commonly used between the same parts or parts having the same functions, and repeated descriptions thereof are omitted.

In addition, the position, size, range, and the like of each component shown in the drawings may not show actual positions, sizes, ranges, etc., for easy understanding. For this reason, the disclosed invention is not necessarily limited to positions, sizes, ranges, and the like disclosed in the drawings and the like.

In addition, the terms 1, 2, 3, etc. used in this specification are attached to avoid confusion of components, and are not limited in number. Therefore, it can be explained, for example, by appropriately replacing "first" with "second" or "third".

The transistor is a type of semiconductor device, and can realize amplification of current or voltage, switching operations for controlling conduction or non-conduction, and the like. The transistor in the present specification includes an insulated gate field effect transistor (IGFET) or a thin film transistor (TFT).

In addition, the function of the "source" or "drain" of the transistor can be replaced in the case of employing transistors of different polarities, or when the direction of the current changes in circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably.

In addition, the terms "electrode" and "wiring" in this specification and the like do not functionally limit these components. For example, "electrode" may be used as part of "wiring", and vice versa. In addition, the term "electrode" or "wiring" includes the case where a plurality of "electrodes" or "wiring" are formed integrally.

(Embodiment 1)

In this embodiment, a transistor using an oxide semiconductor as a channel and a method of manufacturing the same will be described with reference to FIGS. 1 to 4.

1(a) is a top view for explaining the structure of the transistor 100, which is a form of configuration of a semiconductor device, and FIG. 1(b) is a chain line A1-A2 in FIG. 1(a). It is a sectional view explaining the laminated structure of the site shown. In addition, in FIG. 1(a), the description of the substrate and the insulating layer is omitted.

In the transistor 100 shown in FIG. 1, the base layer 102 is formed on the substrate 101, and the oxide semiconductor layer 103 is formed on the base layer 102. Further, a gate insulating layer 104 is formed on the oxide semiconductor layer 103, and a gate electrode 105 is formed on the gate insulating layer 104. In addition, an insulating layer 107 and an insulating layer 108 are formed on the gate electrode 105, and a source electrode 110a and a drain electrode 110b are formed on the insulating layer 108. The source electrode 110a and the drain electrode 110b are electrically connected to the oxide semiconductor layer 103 through the contact hole 109 formed in the gate insulating layer 104, the insulating layer 107, and the insulating layer 108. It is done.

The oxide semiconductor layer 103 includes a channel formation region 103c overlapping the gate electrode 105 through the gate insulating layer 104, a source region 103a electrically connected to the source electrode 110a, and a drain It has a drain region 103b that is electrically connected to the electrode 110b.

Further, the gate electrode 105 has a gate electrode 105a contacting the gate insulating layer 104 and a gate electrode 105b stacked on the gate electrode 105a.

1(a) shows an example in which a plurality of contact holes 109 are formed on the source region 103a and the drain region 103b, respectively, but on the source region 103a and the drain region 103b. You may make it the structure which forms one each. Further, in order to reduce the contact resistance of the source electrode 110a and the source region 103a, and the contact resistance of the drain electrode 110b and the drain region 103b, the contact hole 109 is very large and also the contact hole 109 It is preferable to increase the number of ).

The transistor 140 shown in FIG. 2 has a sidewall 111 on the side of the gate electrode 105 in addition to the configuration of the transistor 100, and overlaps the sidewall 111 of the oxide semiconductor layer 103 In this, it has a low concentration region 103d and a low concentration region 103e. The low concentration region 103d is formed between the channel formation region 103c and the source region 103a, and the low concentration region 103e is formed between the channel formation region 103c and the drain region 103b. FIG. 2(a) is a top view for explaining the structure of the transistor 140, and FIG. 2(b) is a diagram for explaining a stacked structure of a portion indicated by a chain line B1-B2 in FIG. 2(a). It is a cross section.

By forming the low-concentration region 103d and the low-concentration region 103e, it is possible to reduce the negative shift of the threshold voltage due to the deterioration of transistor characteristics or the short-channel effect.

The transistor 100 and the transistor 140 are one type of a top-gate transistor.

Next, a method of manufacturing the transistor 100 shown in FIG. 1 will be described with reference to FIGS. 3 and 4. In addition, FIGS. 3 and 4 correspond to the cross section of the site indicated by the chain line A1-A2 in FIG. 1(a).

First, the base layer 102 is formed on the substrate 101 to a thickness of 50 nm or more and 300 nm or less, preferably 100 nm or more and 200 nm or less. In addition to the glass substrate and the ceramic substrate, the substrate 101 can be a plastic substrate or the like having a heat resistance that can withstand the processing temperature of the production process. In addition, when the substrate does not require light transmittance, an insulating layer may be used on the surface of a metal substrate such as stainless alloy. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, alumino borosilicate glass or aluminosilicate glass may be used. Besides, a quartz substrate, a sapphire substrate, or the like can be used. Further, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can also be applied, and a semiconductor element provided on these substrates may be used as the substrate 101. .

The base layer 102 may be formed of a material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, silicon nitride, silicon oxide, silicon nitride oxide or silicon oxynitride in a single layer or by lamination, and a substrate It has a function of preventing the diffusion of impurity elements from (101). In addition, in the present specification, the nitride oxide has a higher content of nitrogen than oxygen as its composition, and the oxynitride indicates a higher content of oxygen than nitrogen as its composition. In addition, the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

As the base layer 102, a sputtering method, a CVD method, a coating method, a printing method or the like can be suitably used. In this embodiment, a stack of silicon nitride and silicon oxide is used as the base layer 102. Specifically, silicon nitride is formed on the substrate 101 to a thickness of 50 nm, and silicon oxide is formed on the silicon nitride to a thickness of 150 nm. In addition, phosphorus (P) or boron (B) may be doped in the base layer 102.

In addition, by including a halogen element such as chlorine and fluorine in the base layer 102, the function of preventing diffusion of impurity elements from the substrate 101 can be further enhanced. The concentration of the halogen element included in the base layer 102 is 1×10 ¹⁵ /cm ³ or more and 1×10 ²⁰ /cm ³ or less in a concentration peak obtained by analysis using a SIMS (Secondary Ion Mass Spectrometer). You can do it.

In addition, the base layer 102 may be made of a material that releases oxygen by heating. "Oxygen released by heating" means, in TDS (Thermal Desorption Spectroscopy) analysis, the amount of released oxygen in terms of oxygen atoms is 1.0×10 ¹⁸ atoms/cm ³ or more, preferably 3.0×10 ²⁰ atoms /cm ³ or more.

Here, in the TDS analysis, a method for measuring the amount of released oxygen in terms of oxygen atoms will be described below.

The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. For this reason, the emission amount of gas can be calculated by the ratio between the integral value of the spectrum of the insulating layer and the reference value of the standard sample. The reference value of the standard sample is the ratio of the density of atoms to the integral value of the spectrum of a sample containing a given atom.

For example, from a TDS analysis result of a silicon wafer containing hydrogen having a predetermined density as a standard sample, and a TDS analysis result of an insulating layer, the emission amount of oxygen molecules (NO ₂ ) in the insulating layer can be obtained by Equation (1). . Here, it is assumed that all of the spectrums detected by the mass number 32 obtained from the TDS analysis are from oxygen molecules. There is CH ₃ OH as a mass number of 32, but it is not considered here as it is unlikely to exist. In addition, oxygen molecules containing an oxygen atom having a mass number of 17 and an oxygen atom having a mass number of 18, which is an equivalent of the oxygen atom, are not considered because the existence ratio in the natural system is extremely small.

<Equation 1>

N _O2 = N _H2 /S _H2 ×S _O2 ×α

N _H2 is a value obtained by converting hydrogen molecules released from a standard sample into density. S _H2 is an integral value of the spectrum when the standard sample is analyzed by TDS. Here, the reference value of the standard sample is referred to as N _H2 /S _H2 . S _O2 is the integral value of the spectrum when TDS analysis of the insulating layer. α is a coefficient that affects spectral intensity in TDS analysis. For details of Equation 1, see Japanese Patent Laid-Open Publication No. 6-275697. In addition, the release amount of oxygen of the insulating layer is a temperature rise and release analysis device EMD-WA100OS/W manufactured by Electronic Science Co., Ltd., and a silicon wafer containing 1×10 ¹⁶ atoms/cm ³ of hydrogen atoms is used as a standard sample. Was measured.

In addition, in TDS analysis, part of oxygen is detected as an oxygen atom. The ratio of the oxygen molecule and the oxygen atom can be calculated from the ionization rate of the oxygen molecule. In addition, since the above-mentioned α includes the ionization rate of oxygen molecules, it is possible to estimate the amount of oxygen atoms released by evaluating the amount of oxygen molecules released.

Further, NO ₂ is the amount of oxygen molecules released. In the insulating layer, the amount of oxygen released when converted to oxygen atoms is twice the amount of oxygen molecules released.

In the above configuration, the insulating layer that is released from oxygen by heating may be silicon oxide [SiO _X (X>2)] with excess oxygen. The silicon oxide [SiO _X (X>2)] with excess oxygen contains more than twice the number of oxygen atoms per unit volume of silicon atoms. The number of silicon atoms and the number of oxygen atoms per unit volume is a value measured by Rutherford backscattering.

By supplying oxygen from the base layer to the oxide semiconductor, the interface level between the base layer and the oxide semiconductor can be reduced. As a result, it is possible to suppress the electric charges and the like generated due to the operation of the transistor from being captured at the interface between the above-described base layer and the oxide semiconductor, so that a transistor with little deterioration in electrical characteristics can be obtained.

In addition, charge may be generated due to oxygen deficiency of the oxide semiconductor. In general, oxygen vacancies in oxide semiconductors partially form donors to generate electrons as carriers. As a result, the threshold voltage of the transistor is shifted in the negative direction. This tendency is remarkable in the oxygen deficiency occurring on the back channel side. In addition, the back channel in this specification means the vicinity of the interface of a base layer in an oxide semiconductor. When oxygen is sufficiently released from the base layer to the oxide semiconductor, oxygen deficiency of the oxide semiconductor, which is a factor in which the threshold voltage shifts in the negative direction, can be compensated.

That is, when an oxygen deficiency occurs in the oxide semiconductor, it is difficult to suppress the capture of charges at the interface between the base layer and the oxide semiconductor. By providing an insulating layer in which oxygen is released by heating to the base layer, the oxide semiconductor and the base By reducing the interface level of the layer and the oxygen deficiency of the oxide semiconductor, the influence of charge trapping at the interface of the oxide semiconductor and the base layer can be reduced.

Moreover, you may use the insulating material containing the component of the same type as the oxide semiconductor formed later, for the base layer 102. When the base layer 102 is made of a stack of different layers, the layer in contact with the oxide semiconductor may be an insulating material containing the same component as the oxide semiconductor. This is because such a material has good compatibility with an oxide semiconductor, and by using it for the base layer 102, the state of the interface with the oxide semiconductor can be maintained satisfactorily. Here, the term "component of the same type as the oxide semiconductor" means one or a plurality of elements selected from constituent elements of the oxide semiconductor. For example, when the oxide semiconductor is composed of an In-Ga-Zn-based oxide semiconductor material, gallium oxide or the like is an insulating material containing the same component.

Next, an oxide semiconductor is formed on the base layer 102. In addition, as a pre-treatment, in order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor as much as possible, the substrate 101 is preheated in the preheating chamber of the film forming apparatus, and adsorbed onto the substrate 101 or the base layer 102. It is desirable to exhaust impurities by removing impurities such as hydrogen and moisture. The cryo pump is preferably used as the exhaust means provided in the preheating chamber. In addition, the preheating treatment may be omitted. Moreover, the said preliminary heating may be performed similarly to the board|substrate 101 before film formation of the base layer 102.

It is preferable that an oxide semiconductor contains at least indium (In) or zinc (Zn). It is particularly preferable to include In and Zn. Further, as stabilizers for reducing fluctuations in electrical properties of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer.

In addition, as other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), You may have any one or multiple types of dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, an oxide of a binary metal, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg series Oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also referred to as IGZO), an oxide of ternary metal, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In- Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy- Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, and quaternary metal oxide In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide can be used.

The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and Ga.

Here, for example, the In-Ga-Zn-based oxide means an oxide having indium (In), gallium (Ga), and zinc (Zn), and the ratio of In, Ga, and Zn is irrelevant. Further, metal elements other than In, Ga, and Zn may be included.

Further, as the oxide semiconductor layer, a thin film represented by the formula InMO ₃ (ZnO) _m (m>0) can be used. Here, M represents one or more metal elements selected from Sn, Zn, Ga, Al, Mn, and Co. Further, as the oxide semiconductor, a material represented by In ₃ SnO ₅ (ZnO) _n (n>0) may be used.

For example, In:Ga:Zn=1:1:1(=1/3:1/3:1/3) or In:Ga:Zn=2:2:1(=2/5:2/5 An In-Ga-Zn-based oxide having an atomic ratio of :1/5) or an oxide near its composition can be used. Or, In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1 /2) or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), an atomic ratio of In-Sn-Zn-based oxide or an oxide near its composition may be used. .

However, the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics (mobility, threshold, gap, etc.). In addition, in order to obtain the required semiconductor properties, it is preferable to make the carrier density or impurity concentration, the defect density, the atomic ratio of the metal element and oxygen, the bonding distance between atoms, density, and the like to be appropriate.

For example, high mobility can be obtained relatively easily with In-Sn-Zn-based oxides. However, even in the In-Ga-Zn-based oxide, the mobility can be increased by reducing the defect density in the bulk.

In addition, for example, the composition of the oxide in which the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+c=1) has an atomic ratio of In:Ga:Zn= The vicinity of the composition of the oxide A:B:C (A+B+C=1) means that a, b, and c satisfy (aA) ² +(bB) ² +(cC) ² ≤ r ² In other words, r may be, for example, 0.05. The same is true for other oxides.

The oxide semiconductor may be single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. In addition, a structure containing a portion having crystallinity in the amorphous structure or a viamorphic structure may be used.

Since the oxide semiconductor in the amorphous state can obtain a relatively smooth flat surface, it is possible to reduce interfacial scattering when a transistor is fabricated using this, and relatively high mobility can be obtained relatively easily.

In addition, in the oxide semiconductor having crystallinity, defects in the bulk can be reduced more, and when the flatness of the surface is increased, mobility higher than that of the amorphous oxide semiconductor can be obtained. In order to increase the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface, specifically, an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. It is good to do. In addition, Ra can be evaluated with an atomic force microscope (AFM).

As the oxide semiconductor having crystallinity, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) is preferable. CAAC-OS is not a complete single crystal, nor is it completely amorphous. CAAC-OS is an oxide semiconductor having a crystal-amorphous mixed phase structure having a crystal part in an amorphous phase. In addition, the crystal part is often a size that one side fits into a cube of less than 100 nm. In addition, on observation with a transmission electron microscope (TEM), the boundary between the amorphous portion and the crystal portion included in CAAC-OS is not clear. In addition, grain boundaries (also referred to as grain boundaries) cannot be confirmed in CAAC-OS by TEM. Therefore, in CAAC-OS, the decrease in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface where the c-axis is formed of the CAAC-OS, and is also a triangular or hexagonal atom when viewed from a direction perpendicular to the ab plane. It has an arrangement, and a metal atom is arranged in a layer shape or a metal atom and an oxygen atom in a layer shape when viewed from a direction perpendicular to the c-axis. Further, the directions of the a-axis and the b-axis may be different between different crystal parts. In the present specification, when simply described as vertical, a range of 85° to 95° is also included. In addition, when simply describing as parallel, the range of -5 degrees or more and 5 degrees or less is also included.

In addition, in CAAC-OS, the distribution of crystal parts does not have to be the same. For example, in the process of forming CAAC-OS, when crystal growth is performed on the surface side of the oxide semiconductor film, the proportion of the crystal portion in the vicinity of the surface to be formed may increase. In addition, by adding an impurity to CAAC-OS, the crystal part may be amorphized in the impurity addition region.

Since the c-axis of the crystal part included in CAAC-OS is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of CAAC-OS, the shape of CAAC-OS (the cross-sectional shape of the surface to be formed or the surface of the surface) Depending on the cross-sectional shape), they may face different directions. In addition, the direction of the c-axis of the crystal part is a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface when CAAC-OS is formed. The crystal part is formed by forming a film or performing a crystallization process such as heat treatment after film formation.

CAAC-OS is a conductor, a semiconductor, or an insulator depending on its composition. Further, depending on the composition and the like, it is transparent or opaque to visible light. Moreover, a part of CAAC-OS may be substituted with nitrogen.

A transistor using CAAC-OS can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor is highly reliable.

An example of the crystal structure included in CAAC-OS will be described in detail with reference to FIGS. 15 to 17. In addition, unless otherwise specified, FIGS. 15 to 17 are referred to as the c-axis direction and the plane perpendicular to the c-axis direction is referred to as the ab surface. The upper half and lower half are simply referred to as the upper half and lower half when the ab surface is bounded. In Fig. 15, O surrounded by a circle represents O of a 4th coordinate, and O surrounded by a double circle represents O of a 3rd coordinate.

15(a), a structure having one 6-coordinate In and 6 4-coordinate oxygen atoms (hereinafter, 4-coordinate O) close to In is shown. Here, a structure in which only a metal atom shows an oxygen atom close to one is called a small group. The structure of Fig. 15(a) takes an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are four coordinates of O in the upper half and the lower half of FIG. 15(a). In the small group shown in Fig. 15A, the charge is 0.

Fig. 15(b) shows a structure having one 5-coordinate Ga, three 3-coordinate oxygen atoms close to Ga (hereafter, 3-coordinate O), and two 4-coordinate O adjacent to Ga. . All of the 3 coordination O is in the ab plane. In the upper half and lower half of FIG. 15(b), there are four coordinates of O, one for each. In addition, since In also takes the 5th coordinate, the structure shown in Fig. 15B can be taken. In the small group shown in Fig. 15B, the charge is 0.

15(c), a structure having one 4th coordinate Zn and 4 4th coordinate O close to Zn is shown. In Fig. 15(c), there is one 4th coordinate O in the upper half, and 3 4th O is in the lower half. Alternatively, there may be three four-coordinated O in the upper half of FIG. 15(c), and one four-coordinated O in the lower half. The small group shown in Fig. 15(c) has zero charge.

15(d), a structure having one 6-coordinate Sn and 6 4-coordinates O close to Sn is shown. In the upper half of FIG. 15(d), there are three four-coordinated O, and the lower half has three four-coordinated O. In the small group shown in Fig. 15D, the charge is +1.

15(e) shows a small group containing two Zn. In the upper half of Fig. 15(e), there is one 4th coordinate O, and in the lower half there is 1 4th coordinate O. In the small group shown in Fig. 15E, the charge is -1.

Here, the aggregate of a plurality of small groups is called a middle group, and the aggregate of a group among a plurality is called a large group (also called a unit cell).

Here, the rules for combining these small groups will be described. Three O of the upper half of the 6-coordinate In shown in Fig. 15(a) has three adjacent In each in the downward direction, and three O of the lower half each has three adjacent In in the upward direction. Have One O of the upper half of the Ga of 5 coordination shown in FIG. 15B has one adjacent Ga in the downward direction, and one O of the lower half has one adjacent Ga in the upward direction. One O of the upper half of the Zn of the 4th coordinate shown in FIG. 15(c) has one adjacent Zn in the downward direction, and three O of the lower half has three adjacent Zn in the upward direction. In this way, the number of O of the 4th coordinate in the upward direction of the metal atom and the number of adjacent metal atoms in the downward direction of the O are the same, and likewise, the number of O in the 4th coordinate in the downward direction of the metal atom and the O of the The number of adjacent metal atoms in the upward direction is the same. Since O is 4th coordination, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, when the sum of the number of O of 4 coordination in the upward direction of the metal atom and the number of O of 4 coordination in the downward direction of the other metal atom is 4, two small groups having metal atoms can be combined. have. For example, if the 6th coordination metal atom (In or Sn) combines the 4th coordination O with the lower half, because the 4th coordination O is 3, the 5th coordination metal atom (Ga or In) Or it is combined with any one of the four-coordinate metal atom (Zn).

The metal atom having these coordination numbers is bonded via O of 4 coordination in the c-axis direction. In addition, a plurality of small groups are combined to form a middle group so that the total charge of the layer structure is zero.

Fig. 16A shows a model diagram of a medium group constituting the layer structure of an In-Sn-Zn-based oxide. 16B shows a large group consisting of three medium groups. 16(c) shows the atomic arrangement when the layer structure of FIG. 16(b) is observed from the c-axis direction.

In FIG. 16A, for the sake of simplicity, the O of the third coordinate is omitted, and the O of the fourth coordinate represents only the number, for example, that there are four of the four coordinates O in the upper half and the lower half of Sn. It is shown as 3 of a round circle. Similarly, in FIG. 16(a), there are four coordinates of O in the upper half and the lower half, respectively, and are indicated as 1 in a round circle. Also in FIG. 16A, in the lower half, there is one 4th coordinate O, the upper half has 3 4th coordinate O, and the upper half has 1 4th coordinate O. Zn with three 4th coordinate O is shown in half.

In (a) of FIG. 16, in the middle group constituting the layer structure of the In-Sn-Zn-based oxide, Sn in the upper half and the lower half of each of the three O's in the order of three is from the top, O of the four's One by one combines In in the upper half and the lower half, the In combines Zn with three four-coordinates O in the upper half, and one four-coordinates O in the lower half of the Zn between them. Then, the 4th coordination O is combined with In in the upper half and the lower half by 3, and the In is combined with a small group consisting of 2 Zn with 1 4th coordination O in the upper half, and 1 of the half below this subgroup. It is a configuration in which three O's of four coordinations are interposed between three and four O's are combined with Sn in the upper half and lower half. A plurality of these middle groups are combined to form a large group.

Here, in the case of the O of the 3 th coordinate and the O of the 4 th coordinate, the charge per bond can be considered to be -0.667 and -0.5, respectively. For example, the charges of In (6th or 5th coordinate), Zn (4th coordinate), and Sn (5th or 6th coordinate) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, in order to form the layer structure containing Sn, the charge -1 to remove the charge +1 is required. As a structure that takes charge -1, as shown in Fig. 15(e), a small group containing two Zn can be mentioned. For example, if there is one small group containing two Zn with respect to one small group containing Sn, since the charge is lost, the total charge of the layer structure can be made zero.

Specifically, by repeating the large group shown in Fig. 16B, crystals of In-Sn-Zn-based oxide (In ₂ SnZn ₃ O ₈ ) can be obtained. In addition, the layer structure of the obtained In-Sn-Zn-based oxide can be represented by a composition formula of In ₂ SnZn ₂ O ₇ (ZnO) _m (m is 0 or a natural number).

In addition, in addition, In-Sn-Ga-Zn-based oxides, which are quaternary metal oxides, and In-Ga-Zn-based oxides (also referred to as IGZO), which are oxides of ternary metals, and In-Al-Zn-based oxides , Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In- Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, or binary metal In the case of using an oxide of In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, etc. It is the same.

For example, a model diagram of a medium group constituting the layer structure of In-Ga-Zn-based oxide is shown in Fig. 17A.

In (a) of FIG. 17, in the middle group constituting the layer structure of the In-Ga-Zn-based oxide, In in the upper half and the lower half of each of the three O's of three in order from the top, O of the four's Is bound to Zn in one upper half, with three four-coordinates O of the lower half of Zn interposed, one in four coordinations of O and Ga in the upper half and lower half, and Ga This is a configuration in which one of the four coordinates of O of the lower half is interposed, and three of the four coordinates of O are combined with In in the upper half and the lower half. A plurality of these middle groups are combined to form a large group.

17(b) shows a large group consisting of three medium groups. 17(c) shows the atomic arrangement when the layer structure of FIG. 17(b) is observed from the c-axis direction.

Here, since the charges of In (6 or 5 coordination), Zn (4 coordination), and Ga (5 coordination) are +3, +2, and +3, respectively, a small group containing any one of In, Zn, and Ga The charge becomes zero. Therefore, in the combination of these small groups, the total charge of the middle group is always zero.

In addition, the middle group constituting the layer structure of the In-Ga-Zn-based oxide is not limited to the middle group shown in Fig. 17(a), but the combination of the middle groups having different arrangements of In, Ga, and Zn. Large groups can also take it.

Specifically, by repeating the large group shown in Fig. 17B, crystals of an In-Ga-Zn-based oxide can be obtained. In addition, the layer structure of the obtained In-Ga-Zn-based oxide can be represented by a composition formula of InGaO ₃ (ZnO) _n (n is a natural number).

When n=1 (InGaZnO ₄ ), for example, the crystal structure shown in Fig. 18(a) can be taken. In addition, in the crystal structure shown in Fig. 18(a), as described in Fig. 15(b), since Ga and In take the 5th coordinate, a structure in which Ga is substituted with In can also be taken.

In addition, when n=2 (InGaZn ₂ O ₅ ), for example, the crystal structure shown in Fig. 18B can be taken. In addition, in the crystal structure shown in Fig. 18(b), as described in Fig. 15(b), since Ga and In take 5 positions, a structure in which Ga is substituted with In can also be taken.

In this embodiment, first, a first oxide semiconductor of 1 nm or more and 10 nm or less is formed on the base layer 102 by sputtering. The substrate temperature when forming the first oxide semiconductor is 200°C or higher and 400°C or lower.

Here, the sputtering device forming the oxide semiconductor will be described in detail below.

In the film formation chamber for forming the oxide semiconductor, it is preferable to make the rate of 1 x 10 ^-10 Pa·m ³ /sec or less, and accordingly, when the film is formed by sputtering, incorporation of impurities into the film can be reduced. .

In order to lower the leak rate, it is necessary to reduce not only the external leak but also the internal leak. An external leak is a gas flowing in from the outside of the vacuum system due to a minute hole or defective seal. The internal leak is caused by leakage from a compartment such as a valve in a vacuum gauge or discharge gas from an internal member. In order to reduce the leak rate to 1×10 ^-10 Pa·m ³ /sec or less, it is necessary to take countermeasures on both the outer and inner leaks.

In order to reduce the external leakage, the opening and closing portion of the deposition chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal material coated with iron fluoride, aluminum oxide or chromium oxide. Metal gaskets have higher adhesion compared to O-rings, which can reduce external leakage. In addition, by using a metal material coated with passivation such as iron fluoride, aluminum oxide, or chromium oxide, the emission gas containing hydrogen generated from the metal gasket can be suppressed, and internal leakage can also be reduced.

As a member constituting the inner wall of the film formation chamber, aluminum, chromium, titanium, zirconium, nickel, or vanadium with less emission gas containing hydrogen is used. Further, the above-mentioned materials may be coated with an alloy material containing iron, chromium, nickel, or the like and used. Alloy materials, including iron, chromium and nickel, are stiff, heat resistant, and suitable for processing. Here, if the surface irregularities of the member are reduced by polishing or the like in order to reduce the surface area, the emission gas can be reduced. Alternatively, the member of the above-described film forming apparatus may be coated with passivation such as iron fluoride, aluminum oxide, and chromium oxide.

Moreover, it is preferable to provide a sputter gas purifier immediately before introducing the sputter gas into the film formation chamber. At this time, the length of the pipe from the purifier to the deposition chamber is 5 m or less, preferably 1 m or less. By setting the length of the piping to 5 m or less or 1 m or less, the influence of the emission gas from the piping can be reduced depending on the length.

Exhaust of the film formation chamber may be performed by appropriately combining a rough pump such as a dry pump and a high vacuum pump such as a sputter ion pump, a turbo molecular pump, and a cryo pump. In addition, in order to remove residual moisture in the deposition chamber, it is preferable to use an adsorption-type vacuum pump, for example, a cryo pump, an ion pump, or a titanium reduction pump. Turbo-molecular pumps have excellent exhaustion of large-sized molecules, while low exhaustion capacity of hydrogen or water. Therefore, it is effective to combine a cryo pump with a high exhaust capacity of water and a sputter ion pump with a high exhaust capacity of hydrogen. Further, a cold trap may be added to the turbo molecular pump. The deposition chamber exhausted using an adsorption type vacuum pump such as a cryo pump is a compound containing a hydrogen atom such as a hydrogen atom or water (H ₂ O) (more preferably a compound containing a carbon atom). Since the back is exhausted, the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced.

Since the adsorbed substance present inside the film forming chamber is adsorbed on the inner wall, it does not affect the pressure in the film forming chamber, but causes gas emission when the film forming chamber is exhausted. For this reason, although it is not related to the leak rate and the exhaust rate, it is important to evacuate the adsorbent existing in the film formation chamber as much as possible by using a pump having a high exhaust capacity and evacuating in advance. In addition, the film forming chamber may be baked in order to accelerate the release of the adsorbent. By baking, the release rate of the adsorbate can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbent is removed while adding an inert gas, it is possible to further increase the release speed of water or the like, which is difficult to remove only by exhausting.

In the sputtering method, an RF power supply, an AC power supply, and a DC power supply can be appropriately used as the power supply for generating plasma.

An In-Ga-Zn-based oxide target for forming an In-Ga-Zn-based oxide material as an oxide semiconductor by sputtering is, for example, In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:1 [mol A target having a composition ratio of [number ratio] can be used. In addition, a target having a composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:2 [mol number ratio], or In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:4 [mol Water ratio], a target having a composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :ZnO=2:1:8 [mol number ratio] can also be used. In addition, the atomic number ratio is represented by In:Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3 or 3:1:4 -Ga-Zn-based oxide targets can be used. By forming an oxide semiconductor using the In-Ga-Zn-based oxide target having the above-described atomic ratio, polycrystalline or CAAC-OS is easily formed.

In addition, the In-Sn-Zn-based oxide can be referred to as ITZO. In addition, when the In-Sn-Zn-based oxide is formed as an oxide semiconductor by sputtering, the atomic ratio is preferably In:Sn:Zn=1:1:1, 2:1:3, 1:2:2 or An In-Sn-Zn-based oxide target represented by 20:45:35 is used. By forming an oxide semiconductor using the In-Sn-Zn-based oxide target having the above-described atomic ratio, polycrystalline or CAAC-OS is easily formed.

Further, the relative density of the metal oxide target for forming the oxide semiconductor is 90% or more and 100% or less, and preferably 95% or more and 99.9% or less. By using a metal oxide target having a high relative density, the formed oxide semiconductor layer can be formed into a dense film.

In addition, the sputtering gas suitably uses a rare gas (typically argon) atmosphere, an oxygen atmosphere, a mixed gas of a rare gas and oxygen. In addition, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed from the sputtering gas. For example, when argon is used as the sputtering gas, a purity of 9N, a dew point of -121°C, a content of H ₂ O of 0.1 ppb or less, a content of H _{2 of} 0.5 ppb or less is preferred, and when oxygen is used, a purity of 8N, The dew point -112°C, the amount of H ₂ O contained is 1 ppb or less, and the amount of H ₂ contained is 1 ppb or less.

Further, the substrate temperature at the time of film formation is 150°C or higher and 450°C or lower, preferably 200°C or higher and 350°C or lower. By forming a film while heating the substrate at 150°C or higher and 450°C or lower, preferably 200°C or higher and 350°C or lower, mixing of moisture (including hydrogen) into the film can be prevented.

By forming the film while heating the substrate, the impurity concentration of hydrogen, moisture, hydride or hydroxide contained in the formed oxide semiconductor can be reduced. In addition, damage due to sputtering is reduced. Then, while removing the residual moisture in the deposition chamber, hydrogen and a sputter gas from which moisture has been removed are added to form a first oxide semiconductor with a thickness of 1 nm or more and 10 nm or less, preferably 2 nm or more and 5 nm or less, using the target.

In this embodiment, as a target for an oxide semiconductor, an In-Ga-Zn-based oxide semiconductor target (In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:2 [mol number ratio]) is used as a substrate. The distance between the target and the target is 170 mm, the substrate temperature is 250°C, the pressure is 0.4 Pa, the direct current (DC) power source is 0.5 kW, and only oxygen, argon, or argon and oxygen are used as the sputter gas to form a first oxide having a thickness of 5 nm. Form a semiconductor.

Next, the first heat treatment is performed using nitrogen or dry air as the chamber atmosphere in which the substrate is placed. The temperature of the first heat treatment is 400°C or higher and 750°C or lower. The first oxide semiconductor is crystallized by the first heat treatment to become the first crystalline oxide semiconductor.

Although it also depends on the temperature of the first heat treatment, crystallization occurs from the film surface by the first heat treatment, crystal growth from the surface of the film toward the inside, and a C-axis oriented crystal is obtained. By the first heat treatment, a large amount of zinc and oxygen are collected on the surface of the film, and a graphene type two-dimensional crystal composed of zinc and oxygen having an hexagonal upper surface is formed on the outermost surface in a single layer or multiple layers, which is in the film thickness direction. It grows to overlap and becomes a lamination. When the temperature of the heat treatment is increased, crystal growth proceeds from the surface to the inside and from the inside to the bottom.

By the first heat treatment, oxygen in the base layer 102 is diffused to or near the interface with the first crystalline oxide semiconductor (±5 nm from the interface), thereby reducing oxygen deficiency of the first crystalline oxide semiconductor. Accordingly, the base layer 102 is oxygen in an amount exceeding the stoichiometric ratio at least in any one of the base layer 102 (in bulk) and the interface between the first crystalline oxide semiconductor and the base layer 102. It is preferred to exist.

Next, a second oxide semiconductor thicker than 10 nm is formed on the first crystalline oxide semiconductor. For the formation of the second oxide semiconductor, a sputtering method is used, and the substrate temperature at the time of film formation is 200°C to 400°C. When the substrate temperature at the time of film formation is 200°C or more and 400°C or less, alignment of the precursors occurs in the oxide semiconductor to be deposited on the surface of the first crystalline oxide semiconductor, so-called orderlyness can be achieved.

In this embodiment, an In-Ga-Zn-based oxide semiconductor target (In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:2 [mol number ratio]) is used as the target for the oxide semiconductor, and the substrate and The distance between targets is 170mm, substrate temperature 400℃, pressure 0.4Pa, DC (DC) power supply power 0.5kW, oxygen-only, argon-only, or argon and oxygen as a sputtering gas. To form a tabernacle.

Next, a second heat treatment is performed using nitrogen or dry air as the chamber atmosphere in which the substrate is placed. The temperature of the second heat treatment is 400°C or higher and 750°C or lower. A second crystalline oxide semiconductor is formed by the second heat treatment. The second heat treatment is performed under a nitrogen atmosphere, under an oxygen atmosphere, or under a mixed atmosphere of nitrogen and oxygen, thereby increasing the density of the second crystalline oxide semiconductor and reducing the number of defects. By the second heat treatment, crystal growth proceeds from the film thickness direction, that is, from the bottom to the inside, using the first crystalline oxide semiconductor as a nucleus to form a second crystalline oxide semiconductor. At this time, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are composed of the same element as homo growth. Or, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are composed of at least one or more different elements.

In this way, in the process of forming the oxide semiconductor, the incorporation of impurities such as hydrogen and moisture into the oxide semiconductor can be reduced by maximally suppressing the incorporation of impurities in the pressure in the deposition chamber, the rate of leakage in the deposition chamber, and the like. Hydrogen contained in the oxide semiconductor reacts with oxygen bound to a metal atom to become water, and at the same time, defects are formed in a lattice (or part where oxygen is released) from which oxygen is released.

For this reason, in the process of forming an oxide semiconductor, it is possible to reduce defects in the oxide semiconductor by greatly reducing impurities. From this, by using an oxide semiconductor made of CAAC-OS with high purity by removing impurities as much as possible, the amount of change in the threshold voltage before and after light irradiation to the transistor or BT test is small, so that stable electrical characteristics are obtained. Can have

In addition, after performing the second heat treatment, it is preferable to switch to an oxidizing atmosphere while maintaining the temperature and further perform the heat treatment. Oxygen defects in the oxide semiconductor can be reduced by heat treatment in an oxidizing atmosphere.

Moreover, the metal oxide which can be used for an oxide semiconductor has a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As described above, by using a metal oxide having a wide band gap, the off-state current of the transistor can be reduced.

Moreover, it is preferable to perform the process from the formation of the base layer 102 to the second heat treatment continuously without contacting the atmosphere. The process from the formation of the base layer 102 to the second heat treatment is preferably controlled under an atmosphere containing little hydrogen and moisture (inert atmosphere, reduced pressure atmosphere, dry air atmosphere, etc.), for example, moisture As for, it is set as the dry nitrogen atmosphere of dew point -40 degreeC or less, Preferably dew point -50 degreeC or less.

Next, a stack of an oxide semiconductor composed of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor is processed to form an island-shaped oxide semiconductor layer 103 (see Fig. 3(a)).

The oxide semiconductor can be processed by forming a mask having a desired shape on the oxide semiconductor and then etching the oxide semiconductor. The above-described mask can be formed using a method such as photolithography. Alternatively, the mask may be formed using a method such as an ink jet method or a printing method.

Further, the etching of the oxide semiconductor may be a dry etching method or a wet etching method. Of course, you may use these in combination.

In addition, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor obtained by the above production method are characterized by having a C-axis orientation. However, the first crystalline oxide semiconductor and the second crystalline oxide semiconductor are non-single crystal structures, not amorphous structures, and are crystalline oxide semiconductors having a C-axis orientation (CAAC-OS).

In addition, it is not limited to the two-layer structure of forming the second crystalline oxide semiconductor on the first crystalline oxide semiconductor, and the film formation and heat treatment for forming the third crystalline oxide semiconductor after the formation of the second crystalline oxide semiconductor The process may be repeated to form a stacked structure of three or more layers.

Like the oxide semiconductor layer 103, by using a stack of a first crystalline oxide semiconductor and a second crystalline oxide semiconductor for a transistor, a transistor having stable electrical characteristics and high reliability can be realized.

Next, a gate insulating layer 104 is formed on the oxide semiconductor layer 103. The gate insulating layer 104 may be a single layer of a material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxide nitride, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, tantalum oxide, or lanthanum oxide. It can be formed by lamination.

Further, as the gate insulating layer 104, hafnium silicate [HfSiO _x (x>0)], nitrogen-added hafnium silicate [HfSi _x O _y N _z (x>0, y>0, z>0)], By using high-k materials such as nitrogen-added hafnium aluminate [HfAl _x O _y N _z (x>0, y>0, z>0)], hafnium oxide, and yttrium oxide, practical (for example, The gate leak can be reduced by making the physical gate insulating film thick without changing the thickness of the gate insulating film (equivalent to silicon oxide). In addition, a high-k material and a stacked structure of any one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, and gallium oxide can be used. The thickness of the gate insulating layer 104 may be 1 nm or more and 300 nm or less, more preferably 5 nm or more and 50 nm or less.

The gate insulating layer 104 is formed by sputtering, CVD, or the like. In order to form the gate insulating layer 104, a film deposition method such as a high-density plasma CVD method using a μ-wave (for example, a frequency of 2.45 GHz) can be applied in addition to the sputtering method or plasma CVD method. In addition, the gate insulating layer 104 is not limited to a single layer, and may be stacked with different layers. Further, the gate insulating layer 104 is preferably an insulating layer containing oxygen in a portion in contact with the oxide semiconductor layer 103, particularly preferably an oxide insulating layer that releases oxygen by heating. For example, by using silicon oxide for the gate insulating layer 104, oxygen can be diffused in the oxide semiconductor layer 103 to reduce oxygen deficiency in the oxide semiconductor layer 103, thereby improving transistor characteristics. Can.

In the structure shown in the present embodiment, only the oxide semiconductor layer 103 is a structure that generates irregularities on the substrate, reducing the leakage current caused by the gate insulating layer 104 and increasing the breakdown voltage of the gate insulating layer 104. Can. Therefore, the transistor can be operated even when the gate insulating layer 104 is thinned down to around 5 nm. Further, by thinning the gate insulating layer 104, the short channel effect is reduced and the effect of increasing the operation speed of the transistor is exhibited.

Further, before forming the gate insulating layer 104, the surface of the oxide semiconductor layer 103 is exposed to plasma of an oxidizing gas such as oxygen, ozone, dinitrogen monoxide, and the surface of the oxide semiconductor layer 103 is oxidized to oxygen The defect may be reduced. In this embodiment, as the gate insulating layer 104, silicon oxide is formed on the oxide semiconductor layer 103 to a thickness of 100 nm.

Next, on the gate insulating layer 104, a conductive layer is formed using a sputtering method, a vacuum evaporation method, or a plating method, a mask is formed on the conductive layer, and the conductive layer is selectively etched to open the gate electrode 105. Form. As a mask formed on the conductive layer, a printing method, an ink jet method, or a photolithography method can be suitably used. The gate electrode 105 is formed by a gate electrode 105a contacting the gate insulating layer 104 and a gate electrode 105b stacked on the gate electrode 105a.

Materials for forming the gate electrode 105a include indium gallium zinc oxide (In-Ga-Zn-O) containing nitrogen, indium tin oxide (In-Sn-O) containing nitrogen, and nitrogen. Indium gallium oxide (In-Ga-O), indium zinc oxide (In-Zn-O) containing nitrogen, tin oxide (Sn-O) containing nitrogen, or indium oxide (In) containing nitrogen It is preferable to use -O) or a metal nitride (InN, ZnN, etc.).

These materials have a work function of 5 eV, preferably 5.5 eV or more, and a gate electrode 105a is provided between the gate electrode 105b and the gate insulating layer 104, and the gate electrode 105a is also gate insulating. By overlapping the oxide semiconductor layer 103 with the layer 104 interposed therebetween, the threshold voltage of the electrical characteristics of the transistor can be made positive, so that a normally-off switching element can be realized. For example, when using In-Ga-Zn-O containing nitrogen as the gate electrode 105a, at least a nitrogen concentration higher than that of the oxide semiconductor layer 103, specifically, an In-Ga having a nitrogen concentration of 7 atom% or more -Zn-O is used.

Materials for forming the gate electrode 105b include aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), and neodymium (Nd) ), a metal element selected from scandium (Sc), an alloy containing the above-described metal element as a component, an alloy combining the above-described metal elements, and a nitride of the above-described metal element. Further, a metal element selected from any one or a plurality of manganese (Mn), magnesium (Mg), zirconium (Zr), and beryllium (Be) may be used.

Note that the gate electrode 105b may have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure using aluminum containing silicon, a two-layer structure stacking titanium on aluminum, a two-layer structure stacking titanium on titanium nitride, a two-layer structure stacking tungsten on titanium nitride, and tungsten on tantalum nitride There are two-layer structure for stacking Cu, two-layer structure for stacking Cu on a Cu-Mg-Al alloy, titanium, and a three-layer structure for stacking aluminum on titanium and further forming titanium on it.

In addition, the gate electrode 105b includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide , It is also possible to apply a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added. Moreover, it can also be set as the laminated structure of the said electroconductive material and the said metal element.

In this embodiment, indium gallium zinc oxide containing nitrogen is used as the gate electrode 105a. In addition, a two-layer structure in which tungsten is stacked on titanium nitride is used as the gate electrode 105b (see Fig. 3(b)). In addition, when the end portion of the formed gate electrode 105 is tapered, it is preferable because the coatability of the layer formed later is improved.

Next, a source region 103a and a drain region 103b are formed by a self-matching process. Specifically, the dopant 106 is added to the oxide semiconductor layer 103 by an ion doping method or an ion implantation method using the gate electrode 105 as a mask. As the dopant 106 added to the oxide semiconductor layer 103, one or a plurality of elements of rare gas or hydrogen (H) can be used.

Hydrogen becomes an electron donor (donor) among the oxide semiconductors to n-type the oxide semiconductor. In addition, the rare gas element causes defects in the oxide semiconductor to n-type the oxide semiconductor. In addition, hydrogen tends to diffuse, and when hydrogen diffuses into the channel formation region, there is a concern that transistor characteristics may deteriorate. For this reason, it is preferable to use a rare gas element as the dopant 106 with good reliability of the semiconductor device.

Further, in the region where the gate electrode 105 of the oxide semiconductor layer 103 overlaps, the gate electrode 105 becomes a mask, and the dopant 106 is not added, and becomes the channel formation region 103c.

The source region 103a and the drain region 103b to which the dopant 106 is added become an n-type oxide semiconductor, and the resistivity is lower than that of the channel formation region 103c. For this reason, the resistance values of the source region 103a and the drain region 103b become small, making it possible to operate the transistor 100 at high speed. In addition, since the overlap between the source region 103a and the drain region 103b and the gate electrode 105 hardly occurs, and the parasitic capacitance can be reduced, the transistor 100 can be operated at a higher speed.

In addition, by using the gate electrode 105 as a mask, the gate insulating layer 104 on the oxide semiconductor layer 103 serving as a source region and a drain region is removed to expose the oxide semiconductor layer 103, and the exposed oxide semiconductor The dopant 106 may be added to the layer 103 to form the source region 103a and the drain region 103b. The gate insulating layer 104 on the oxide semiconductor layer 103 is removed under the condition that the oxide semiconductor layer 103 is difficult to be etched.

The dopant 106 can be added to the exposed oxide semiconductor layer 103 by ion doping or ion implantation. In addition, the addition of the dopant 106 may be performed by generating plasma in a gas atmosphere containing the element to be added and performing plasma treatment on the exposed portion of the oxide semiconductor layer 103. However, there is a fear that the addition by plasma treatment may cause the oxide semiconductor to be etched and thinned. For this reason, it is preferable to add the dopant 106 to the oxide semiconductor layer 103 by ion doping or ion implantation.

In addition, when the dopant 106 is added to the oxide semiconductor layer 103 by an ion doping method or an ion implantation method, it is carried out without leaving the gate insulating layer 104 without exposing the oxide semiconductor layer 103. desirable. By adding the dopant 106 through the gate insulating layer 104 and adding it to the oxide semiconductor layer 103, excessive damage to the oxide semiconductor layer 103 in addition of the dopant 106 can be reduced. In addition, since the interface between the oxide semiconductor layer 103 and the gate insulating layer 104 is kept clean, the characteristics and reliability of the transistor are improved. In addition, it is easy to control the addition depth (addition region) of the dopant 106, and the dopant 106 can be accurately added to the oxide semiconductor layer 103.

In this embodiment, xenon (Xe) is used as the dopant 106, and xenon is added to the oxide semiconductor layer 103 by passing through the gate insulating layer 104 by ion implantation. In addition, the concentration of xenon in the source region 103a and drain region 103b formed by the addition of xenon is 5 x 10 ¹⁹ atoms/cm ³ or more and 1 x 10 ²² atoms/cm ³ or less [Fig. 3]. (c).

After the dopant 106 is added, heat treatment may be performed at a temperature of 300°C or higher and 600°C or lower in an inert gas atmosphere such as nitrogen or rare gas under a reduced pressure atmosphere. In this embodiment, heat treatment at 450° C. for 1 hour is performed in a nitrogen atmosphere using an electric furnace that is one of the heat treatment devices.

Further, the heat treatment device is not limited to an electric furnace, and may be provided with a device for heating the object to be treated by heat conduction or heat radiation from a heat generating element such as a resistance heating element. For example, a Rapid Thermal Anneal (RTA) device such as a Gas Rapid Thermal Anneal (GRTA) device or a Lamp Rapid Thermal Anneal (LRTA) device may be used. The LRTA device is a device that heats an object by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halogen lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. A rare gas such as argon or an inert gas that does not react with the object to be treated by heat treatment such as nitrogen is used for the high-temperature gas.

For example, as a heat treatment, the substrate may be moved into an inert gas heated to a high temperature, heated for a few minutes, and then GRTA may be performed by moving the substrate and taking it out in an inert gas heated to a high temperature.

In the case of performing the heat treatment, it may be performed anytime after the addition of the dopant 106.

Further, when the dopant 106 is added by an ion doping method or an ion implantation method, the substrate may be heated while heating.

Next, the oxide semiconductor layer 103 and the gate electrode 105 are covered to form the insulating layer 107 and the insulating layer 108 by sputtering, CVD, or the like. The insulating layer 107 and the insulating layer 108 may be formed using materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride. . In addition, the insulating layer 107 and the insulating layer 108 can be used singly or in layers.

At this time, it is preferable that at least the insulating layer 107 uses a material that is difficult to release oxygen by heating. This is to avoid lowering the conductivity of the source region 103a and the drain region 103b. Specifically, a silane gas may be used as a main material by CVD, and an appropriate raw material gas may be mixed with nitrogen oxide gas, nitrogen gas, hydrogen gas, and rare gas to form a film. Further, the substrate temperature may be 300°C or higher and 550°C or lower. By using the CVD method, it is possible to make the material difficult to release oxygen by heating. In addition, when the silane gas is used as the main material, hydrogen remains in the insulating layer and the hydrogen diffuses, so that the conductivity of the source region 103a and the drain region 103b can be further increased. The hydrogen concentration in the insulating layer 107 may be 0.1 atomic% or more and 25 atomic% or less.

The thickness of the insulating layer 107 and the insulating layer 108 is 50 nm or more, preferably 200 nm or more and 500 nm or less. In this embodiment, silicon oxide having a film thickness of 300 nm is formed as the insulating layer 107, and aluminum oxide having a film thickness of 100 nm is formed as the insulating layer 108.

The insulating layer 108 is preferably formed using silicon nitride or aluminum oxide in order to prevent intrusion of impurities from the outside. In this embodiment, aluminum oxide having a film thickness of 100 nm is formed as the insulating layer 108 (see Fig. 3(d)). Note that either or both of the insulating layer 107 and the insulating layer 108 may be omitted.

After formation of the insulating layer 108, if necessary, heat treatment (temperature range 150°C or more and 650°C or less, preferably 200°C or more and 500°C or less) may be performed.

Next, a mask is formed on the insulating layer 108, and a portion of the gate insulating layer 104, the insulating layer 107, and the insulating layer 108 is selectively etched using the mask, and the source region 103a is then etched. And a contact hole 109 is formed by exposing a portion of the drain region 103b (see FIG. 4(a)).

Next, a conductive layer is formed over the insulating layer 108, a mask is formed over the conductive layer, and the source layer 110a and the drain electrode 110b are formed by selectively etching the conductive layer (FIG. 4) (b)]. As the conductive layer for forming the source electrode 110a and the drain electrode 110b, the same material as the gate electrode 105b can be applied.

In this embodiment, a conductive layer in which Cu is laminated on a Cu-Mg-Al alloy is used as a conductive layer for forming the source electrode 110a and the drain electrode 110b. By providing the Cu-Mg-Al alloy material in contact with the insulating layer 108, adhesion of the conductive layer can be improved.

The channel length of the transistor 100 corresponds to the length of the channel forming region 103c sandwiched between the source region 103a and the drain region 103b in FIG. 1B. Further, the channel length of the transistor 100 becomes almost equal to the width of the gate electrode 105.

Through the above process, even when the channel length is reduced by miniaturizing the transistor, the transistor 100 using the oxide semiconductor having good electrical characteristics and high reliability can be manufactured.

The transistor 140 has a low concentration region 103d and a low concentration region 103e in the oxide semiconductor layer 103. The transistor 140 can be produced by adding the dopant 106 to the oxide semiconductor layer 103 by dividing it into two times by adding the fabrication process of the side wall 111 to the fabrication process of the transistor 100.

The low concentration region 103d and the low concentration region 103e can be formed by a self-matching process using the gate electrode 105 as a mask. Specifically, after formation of the gate electrode 105, the gate electrode 105 is used as a mask, and the dopant 106 is added to the oxide semiconductor layer 103 in the same manner as the transistor 100 (first dope). Also called fair). As the dopant 106 added to the oxide semiconductor layer 103 in the first doping step, elements similar to the dopant 106 used in the transistor 100 can be used. In the first doping step, the concentration of the dopant 106 in the oxide semiconductor layer 103 is added so that it is 5×10 ¹⁸ atoms/cm ³ or more and less than 5×10 ¹⁹ atoms/cm ³ .

Next, a side wall 111 is formed on the side surface of the gate electrode 105. The side wall 111 can be produced by a known method.

Next, the dopant 106 is added to the oxide semiconductor layer 103 using the gate electrode 105 and the side wall 111 as masks (also referred to as a second doping process). As the dopant 106 added to the oxide semiconductor layer 103 in the second doping step, elements similar to the dopant 106 used in the transistor 100 can be used. In the second doping step, the concentration of the dopant 106 in the oxide semiconductor layer 103 is set to 5×10 ¹⁹ atoms/cm ³ or more and 1×10 ²² atoms/cm ³ or less.

In this way, the source region 103a, the drain region 103b, the low concentration region 103d, and the low concentration region 103e can be formed in the transistor 140. The low concentration region 103d and the low concentration region 103e have a lower dopant concentration and a higher resistivity than the source region 103a and the drain region 103b.

By forming the low-concentration region 103d and the low-concentration region 103e, deterioration of transistor characteristics and negative shift of the threshold voltage due to a short-channel effect can be reduced, and a more reliable transistor can be produced.

Further, the channel length of the transistor 140 corresponds to the length of the channel formation region 103c sandwiched between the low concentration region 103d and the low concentration region 103e in FIG. 2B. In addition, the channel length of the transistor 140 becomes almost equal to the width of the gate electrode 105.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)

In this embodiment, an example of a transistor having a configuration different from that of the transistor disclosed in Embodiment 1 will be described.

5(a) is a top view for explaining the configuration of the transistor 150, and FIG. 5(b) is a diagram for explaining a layered structure of a portion indicated by a chain line C1-C2 in FIG. 5(a). It is a cross section. In addition, in FIG. 5(a), the description of the substrate and the insulating layer is omitted.

In the transistor 150 illustrated in FIG. 5B, the stacking positions of the source electrode 110a and the drain electrode 110b are different from those of the transistor 100 disclosed in Embodiment 1. FIG. In the transistor 150, the source electrode 110a and the drain electrode 110b are formed on the base layer 102, and the oxide semiconductor layer 103 is formed on the base layer 102, the source electrode 110a and the drain electrode 110b. ) Is formed.

In the transistor 150, the source electrode 110a and the drain electrode 110b are connected to the source region 103a and the drain region 103b of the oxide semiconductor layer 103 without passing through the contact hole 109. Therefore, it is easy to increase the connection area and it is easy to reduce the contact resistance.

Note that the channel length of the transistor 150 corresponds to the length of the channel forming region 103c sandwiched between the source region 103a and the drain region 103b in Fig. 5B. In addition, the channel length of the transistor 150 becomes almost equal to the width of the gate electrode 105.

The transistor 160 shown in FIG. 6 has a side wall 111 on the side of the gate electrode 105 in addition to the configuration of the transistor 150, and overlaps the side wall 111 of the oxide semiconductor layer 103. The region has a low concentration region 103d and a low concentration region 103e. The low concentration region 103d is formed between the channel formation region 103c and the source region 103a, and the low concentration region 103e is formed between the channel formation region 103c and the drain region 103b. FIG. 6(a) is a top view for explaining the structure of the transistor 160, and FIG. 6(b) is a diagram for explaining a layered structure of a portion indicated by a chain line D1-D2 in FIG. 6(a). It is a cross section.

By forming the low-concentration region 103d or the low-concentration region 103e in the oxide semiconductor layer 103, the electric field generated between the channel formation region 103c and the source region 103a or the drain region 103b is relaxed to transistor Deterioration of characteristics can be reduced. In particular, relaxation of the electric field generated in the channel formation region 103c and the drain region 103b is effective for reducing deterioration of transistor characteristics. Further, by forming the low-concentration region 103d or the low-concentration region 103e, it is possible to suppress the short-channel effect accompanying the miniaturization of the transistor.

Note that the channel length of the transistor 160 corresponds to the length of the channel formation region 103c sandwiched between the low concentration region 103d and the low concentration region 103e in FIG. 6B. Further, the channel length of the transistor 160 becomes almost equal to the width of the gate electrode 105.

The transistor 170 shown in FIG. 7A is one type of a transistor having a bottom gate structure.

7A shows the cross-sectional structure of the transistor 170. In the transistor 170, a gate electrode 105 is formed on the substrate 101, and a gate insulating layer 104 is formed on the gate electrode 105. The gate electrode 105 has a structure in which the gate electrode 105a is stacked on the gate electrode 105b. The base layer described in Embodiment 1 may be provided between the substrate 101 and the gate electrode 105.

In addition, an oxide semiconductor layer 103 is formed on the gate insulating layer 104, and a channel protective layer 112, a source electrode 110a, and a drain electrode 110b are formed on the oxide semiconductor layer 103. The oxide semiconductor layer 103 includes a channel forming region 103c overlapping the channel protective layer 112, a source region 103a electrically connected to the source electrode 110a, and a drain electrode 110b electrically. It has a drain region 103b to be connected.

The channel protective layer 112 can be formed using the same material and method as the gate insulating layer 104. The thickness of the channel protective layer 112 may be 10 nm or more and 500 nm or less, more preferably 100 nm or more and 300 nm or less.

The source region 103a and the drain region 103b can be formed in the same manner as the transistor 100 using the channel protection layer 112 as a mask.

In addition, an insulating layer 108 is formed on the channel protection layer 112, the source electrode 110a, and the drain electrode 110b. The insulating layer 108 may be a stack of a plurality of insulating layers.

Note that the channel length of the transistor 170 corresponds to the length of the channel forming region 103c sandwiched between the source region 103a and the drain region 103b in Fig. 7A. In addition, the channel length of the transistor 170 becomes almost equal to the width of the channel protective layer 112.

7B shows a cross-sectional structure of the transistor 180. The transistor 180 has a structure in which a back gate electrode 115 and an insulating layer 113 are provided on the transistor 100. In the transistor 180, a back gate electrode 115 is formed on the base layer 102, and an insulating layer 113 is formed on the back gate electrode 115. In addition, the oxide semiconductor layer 103 of the transistor 180 is formed overlapping the back gate electrode 115 with the insulating layer 113 interposed therebetween.

The back gate electrode 115 is arranged to sandwich the channel formation region 103c of the oxide semiconductor layer 103 between the gate electrode 105 and the back gate electrode 115. The back gate electrode 115 is formed of a conductive layer and can function like the gate electrode 105. Also, by changing the potential of the back gate electrode 115, the threshold voltage of the transistor can be changed.

The back gate electrode 115 can be formed of the same material and method as the gate electrode 105b. Further, a layer similar to that of the gate electrode 105a may be provided between the back gate electrode 115 and the insulating layer 113.

The insulating layer 113 can be formed of the same material and method as the gate insulating layer 104. In addition, the base layer 102 may not be formed, and the insulating layer 113 may also serve as the base layer 102.

Note that the channel length of the transistor 180 corresponds to the length of the channel forming region 103c sandwiched between the source region 103a and the drain region 103b in FIG. 7B. Further, the channel length of the transistor 180 becomes almost equal to the width of the gate electrode 105.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)

In this embodiment, a method for forming an oxide semiconductor film made of CAAC-OS will be described below for methods other than those disclosed in the first embodiment.

First, an oxide semiconductor film having a thickness of 1 nm or more and 50 nm or less is formed on the base layer 102.

The substrate temperature at the time of film formation is 150°C or more and 450°C or less, preferably 200°C or more and 350°C or less. By forming the film while heating the substrate at 150°C or higher and 450°C or lower, preferably 200°C or higher and 350°C or lower, mixing of moisture (including hydrogen) and the like into the film can be prevented. Further, CAAC-OS, which is an oxide semiconductor film containing crystallinity, can be formed.

In addition, after the oxide semiconductor is formed, the substrate 101 is subjected to heat treatment to release hydrogen from the oxide semiconductor, and at the same time, part of the oxygen contained in the base layer 102 is used in the oxide semiconductor and the base layer 102. It is preferable to diffuse near the interface of the oxide semiconductor. In addition, by performing the heat treatment, an oxide semiconductor having CAAC-OS with higher crystallinity can be formed.

The temperature of the heat treatment is to release hydrogen from the oxide semiconductor, and at the same time release a part of the oxygen contained in the base layer 102, and also diffuse the oxide semiconductor, the temperature is preferably 200°C or higher. ) Is less than the distortion point, preferably 250°C or more and 450°C or less. By diffusing oxygen in the oxide semiconductor, oxygen deficiency in the oxide semiconductor can be reduced.

In addition, a rapid thermal annealing (RTA) device can be used for the heat treatment. By using RTA, heat treatment can be performed at a temperature equal to or higher than the distortion point of the substrate for a short time. Therefore, it is possible to shorten the time for forming the oxide semiconductor having a large ratio of the crystal region to the amorphous region.

The heat treatment can be performed in an inert gas atmosphere, and typically, it is preferable to perform it in a rare gas such as helium, neon, argon, xenon, krypton, or nitrogen atmosphere. Moreover, you may carry out in an oxygen atmosphere and a reduced pressure atmosphere. The treatment time is 3 minutes to 24 hours. An oxide semiconductor having a larger ratio of the crystalline region to the amorphous region can be formed as the treatment time is increased, but heat treatment exceeding 24 hours causes a decrease in productivity, which is not preferable.

By the above method, an oxide semiconductor made of CAAC-OS can be formed.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 4)

In this embodiment, the effect on the electrical characteristics of the transistor using the oxide semiconductors shown in the first and second embodiments will be described using a band diagram.

8 is a cross-sectional view of a transistor having a stacked structure equivalent to that of the transistor 100 shown in FIG. 1. Fig. 9 shows an energy band diagram (schematic diagram) in the cross section X1-X2 shown in Fig. 8. 9(b) shows a case where the voltage between the source and the drain is an equipotential (VD=0V). 8 is a transistor formed by an oxide semiconductor layer comprising a first oxide semiconductor region (referred to as OS1) and a pair of second oxide semiconductor regions (referred to as OS2) and a source electrode and a drain electrode (referred to as metal). All.

The channel formation region of the transistor in FIG. 8 is formed by OS1, and OS1 purifies and removes impurities such as moisture (including hydrogen) as much as possible from the film, thereby purifying and purifying oxygen. It is formed of an oxide semiconductor that is made intrinsic (i-type) by reducing, or infinitely close to intrinsic. By doing so, the Fermi level (Ef) can be set to the same level as the true Fermi level (Ei).

In addition, the source region and the drain region of the transistor in FIG. 8 are formed by a pair of OS2, and OS2 removes and removes impurities such as moisture (including hydrogen) from the film as much as possible, as in the above OS1. To make it highly purified and reduce oxygen deficiency in the film to make it intrinsic (i-type) or as an oxide semiconductor infinitely close to intrinsicity, and then add an element selected from at least one of hydrogen or rare gas By doing so, a donor or oxygen deficiency is generated and formed. Accordingly, the carrier density of OS2 is higher than that of OS1, and the position of the Fermi level is near the conduction band.

9(a) shows the vacuum level (referred to as Evac), the first oxide semiconductor region (referred to as OS1), the second oxide semiconductor region (referred to as OS2), and the source electrode and drain electrode (referred to as metal). It is a relation of band structure. Here, IP represents an ionization potential, Ea represents an electron affinity, Eg represents an energy gap, and Wf represents a work function. In addition, Ec is the lower end of the conduction band, Ev is the upper end of the valence band, and Ef is the Fermi level. In addition, 1 is OS1, 2 is OS2, and m is metal, respectively. Here, Wf_m is assumed to be 4.1 eV (such as titanium) as a metal.

OS1 is an i-type or substantially i-type oxide semiconductor, and since the carrier density is very low, Ef_1 is assumed to be approximately in the center of Ec and Ev. Further, OS2 is an n-type oxide semiconductor having a high carrier density, and Ec_2 and Ef_2 roughly coincide. The oxide semiconductors shown in OS1 and OS2 are known to have an energy gap (Eg) of 3.15eV and an electron affinity (Ea) of 4.3eV.

As shown in Fig. 9(b), when the channel formation region OS1 and the source region and the drain region OS2 contact, carrier movement occurs so that the Fermi levels coincide, and the band ends of OS1 and OS2 are bent. . Further, even when OS2 and the metal which is the source electrode and the drain electrode are in contact, the carrier moves so that the Fermi level coincides, and the band end of OS2 is bent.

Thus, by forming OS2, which is an n-type oxide semiconductor, between OS1 serving as a channel formation region and metal serving as a source electrode and a drain electrode, the contact between the oxide semiconductor and the metal can be made ohmic, and the contact resistance is reduced. I can do it. As a result, the on-state current of the transistor can be increased.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 5)

Fig. 10A shows an example of a circuit diagram of a storage element (hereinafter, also referred to as a memory cell) constituting a semiconductor device. The memory cell is composed of a transistor 1160 using a material other than an oxide semiconductor for the channel formation region and a transistor 1162 using an oxide semiconductor for the channel formation region.

A transistor 1162 using an oxide semiconductor as a channel formation region can be fabricated according to the first embodiment.

As shown in Fig. 10A, one of the gate electrode of the transistor 1160 and the source electrode or the drain electrode of the transistor 1162 are electrically connected. Further, the first wiring (1st Line: also called source line) and the source electrode of the transistor 1160 are electrically connected, and the second wiring (2nd Line: also called bit line) and the drain electrode of the transistor 1160 , Electrically connected. Then, the third wiring (3rd Line: also called the first signal line) and the other of the source electrode or drain electrode of the transistor 1162 are electrically connected, and the fourth wiring (4th Line: also referred to as the second signal line) The gate electrode of the transistor 1162 is electrically connected.

Since the transistor 1160 using a material other than an oxide semiconductor, for example, single crystal silicon, in the channel formation region is capable of sufficiently high-speed operation, the use of the transistor 1160 allows reading and reading of stored contents at high speed. In addition, the transistor 1162 using an oxide semiconductor for the channel formation region has a characteristic that the off current is small compared to the transistor 1160. For this reason, by turning off the transistor 1162, it is possible to maintain the potential of the gate electrode of the transistor 1160 over a very long time.

By utilizing the characteristic that the potential of the gate electrode can be maintained, information can be written, maintained, and read as follows.

First, the writing and maintenance of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned on, and the transistor 1162 is turned on. Thereby, the potential of the third wiring is supplied to the gate electrode of the transistor 1160 (write). Thereafter, the potential of the gate electrode of the transistor 1160 is maintained (holding) by setting the potential of the fourth wiring to a potential where the transistor 1162 is turned off and turning the transistor 1162 off.

Since the off current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is maintained for a long time. For example, if the potential of the gate electrode of the transistor 1160 is a potential that turns the transistor 1160 on, the on state of the transistor 1160 is maintained over a long period of time. In addition, if the potential of the gate electrode of the transistor 1160 is a potential that turns off the transistor 1160, the off state of the transistor 1160 is maintained for a long time.

Next, reading of information will be described. As described above, when a predetermined potential (low potential) is supplied to the first wiring in a state where the on state or the off state of the transistor 1160 is maintained, the second state according to the on state or the off state of the transistor 1160 The potential of the wiring takes a different value. For example, when the transistor 1160 is turned on, the potential of the second wiring decreases with respect to the potential of the first wiring. Further, when the transistor 1160 is in the off state, the potential of the second wiring does not change.

As described above, the information can be read by comparing the potential of the second wiring with a predetermined potential while the information is held.

Next, rewriting of information will be described. The rewriting of information is performed similarly to the writing and holding of the information. That is, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned on, and the transistor 1162 is turned on. Thereby, the potential of the third wiring (potential relating to new information) is supplied to the gate electrode of the transistor 1160. Thereafter, by setting the potential of the fourth wiring to a potential at which the transistor 1162 is turned off and turning the transistor 1162 off, a new information is maintained.

In this way, the memory cell according to the disclosed invention can directly rewrite information by writing information again. For this reason, the erase operation required in the flash memory or the like is unnecessary, and a decrease in the operation speed due to the erase operation can be suppressed. That is, high-speed operation of a semiconductor device having memory cells is realized.

10(b) shows an example of a circuit diagram of a memory cell that has developed FIG. 10(a).

The memory cell 1100 shown in FIG. 10B includes a first wiring SL (source line), a second wiring BL (bit line), and a third wiring S1 (first signal line). ), fourth wiring (S2) (second signal line), fifth wiring (WL) (word line), transistor 1164 (first transistor), transistor 1161 (second transistor), It is composed of a transistor 1163 (third transistor). The transistor 1164 and the transistor 1163 use materials other than an oxide semiconductor for the channel formation region, and the transistor 1161 uses an oxide semiconductor for the channel formation region.

Here, one of the gate electrode of the transistor 1164 and the source electrode or the drain electrode of the transistor 1161 are electrically connected. Further, the first wiring SL and the source electrode of the transistor 1164 are electrically connected, and the drain electrode of the transistor 1164 and the source electrode of the transistor 1163 are electrically connected. Further, the second wiring BL and the drain electrode of the transistor 1163 are electrically connected, and the third wiring S1 and the other of the source electrode or the drain electrode of the transistor 1161 are electrically connected. , The fourth wiring S2 and the gate electrode of the transistor 1161 are electrically connected, and the fifth wiring WL and the gate electrode of the transistor 1163 are electrically connected.

Next, the operation of the circuit will be described in detail.

When writing to the memory cell 1100, the first wiring SL is 0V, the fifth wiring WL is 0V, the second wiring BL is 0V, and the fourth wiring S2 is 2V. . When writing data "1", the third wiring S1 is set to 2V, and when writing data "0", the third wiring S1 is set to 0V. At this time, the transistor 1163 is in an off state, and the transistor 1161 is in an on state. Further, at the end of writing, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0 V and the transistor 1161 is turned off.

As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1164 is about 2V after writing data "1", and the potential of node A is about 0V after writing data "0". In node A, electric charge according to the potential of the third wiring S1 is accumulated. The off-state current of the transistor 1161 is smaller than that of the transistor using the single crystal silicon in the channel formation region, and thus the potential of the gate electrode of the transistor 1164 Is maintained over a long time.

Next, when reading the memory cell, the first wiring SL is 0 V, the fifth wiring WL is 2 V, the fourth wiring S2 is 0 V, and the third wiring S1 is 0 V, The read circuit connected to the second wiring BL is put into an operating state. At this time, the transistor 1163 is turned on, and the transistor 1161 is turned off.

Since the transistor 1164 is in the off state when the data "0", that is, the node A is about 0V, the resistance between the second wiring BL and the first wiring SL is high. On the other hand, since the transistor 1164 is in the on state when the data "1", that is, the node A is about 2V, the resistance between the second wiring BL and the first wiring SL is low. The read circuit can read data "0" and "1" from the difference in the resistance state of the memory cell. Further, the second wiring BL at the time of writing is set to 0V, but it may be charged in a floating state or a potential of 0V or higher. The third wiring S1 at the time of reading is set to 0 V, but it may be charged in a floating state or a potential of 0 V or higher.

Note that the data "1" and the data "0" are definitions for convenience, and vice versa. In addition, the above-mentioned operation voltage is an example. The operating voltage is such that the transistor 1164 is turned off in the case of data "0", the transistor 1164 is turned in in the case of data "1", and the transistor 1161 is turned on at the time of writing. , It may be selected so that it is in an off state except during writing, and that the transistor 1163 is turned on during reading. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuit may be used.

In this embodiment, for the sake of simplicity, a memory cell having a minimum storage unit (1 bit) has been described, but the configuration of the memory cell is not limited to this. A more advanced semiconductor device can also be configured by appropriately connecting a plurality of memory cells. For example, it is possible to construct a NAND-type or NOR-type semiconductor device using a plurality of the memory cells. The configuration of the wiring is also not limited to Fig. 10(a) or Fig. 10(b) and can be changed as appropriate.

Fig. 11 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having an m×n bit storage capacity.

The semiconductor device illustrated in FIG. 11 includes m fifth and fourth wirings, n second and third wirings, and a plurality of memory cells 1100 (1, 1) to 1100 (m, n). The m cell (row) x n (horizontal) m (n is a natural number) matrix of memory cell arrays 1110 arranged in a matrix shape, and the second and third wiring driving circuit 1111, It is comprised of peripheral circuits, such as a 4 wiring and 5th wiring drive circuit 1113, and a readout circuit 1112. A refresh circuit or the like may be provided as another peripheral circuit.

A memory cell 1100 (i, j) is considered as a representative of each memory cell. Here, the memory cells 1100 (i, j) (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) are the second wiring BL, j, and the third wiring S1 ( j), the fifth wiring (WL)(i) and the fourth wiring (S2)(i), and the first wiring, respectively. The first wiring potential Vs is supplied to the first wiring. In addition, the second wiring (BL) 1 to (BL) (n) and the third wiring (S1) (1) to (S1) (n) are the second wiring and the third wiring driving circuit 1111 and read In the circuit 1112, the fifth wiring WL (1) to (WL) (m) and the fourth wiring S2 (1) to (S2) (m) are the fourth wiring and the fifth wiring driving circuit ( 1113).

The operation of the semiconductor device shown in Fig. 11 will be described. In this configuration, writing and reading are performed for each row.

When writing to the memory cells 1100 (i, 1) to (1100) (i, n) in the i-th row, the first wiring potential Vs is set to 0 V and the fifth wiring WL (i) is set. 0V, the second wirings BL(1) to (BL)(n) are set to 0V, and the fourth wirings S2(i) are set to 2V. At this time, the transistor 1161 is turned on. In the third wirings S1 (1) to (S1) (n), the column for writing data "1" is 2V, and the column for writing data "0" is 0V. Further, at the end of writing, before the potential of the third wirings S1 (1) to (S1) (n) changes, the transistor 1161 is turned off with the fourth wiring S2 (i) set to 0V. do. In addition, the non-selected fifth wiring WL is 0 V, and the non-selected fourth wiring S2 is 0 V.

As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1164 of the memory cell that has written data "1" is about 2 V, and node A of the memory cell has been written data "0". The potential of is about 0V. Further, the potential of node A of the non-selected memory cell does not change.

When reading the memory cells 1100 (i, 1) to (1100) (i, n) in the i-th row, the first wiring potential Vs is set to 0 V and the fifth wiring WL (i) is set. 2V, the fourth wiring (S2) (i) is 0V, the third wiring (S1) (1) to (S1) (n) is 0V, the second wiring (BL) (1) to (BL) (n ), the read circuit connected to is put into an operating state. In the reading circuit, for example, data "0" and "1" can be read from the difference in the resistance state of the memory cell. In addition, the non-selected fifth wiring WL is 0 V, and the non-selected fourth wiring S2 is 0 V. Further, the second wiring BL at the time of writing is set to 0V, but it may be charged in a floating state or a potential of 0V or higher. The third wiring S1 at the time of reading is set to 0 V, but it may be charged in a floating state or a potential of 0 V or higher.

Note that the data "1" and the data "0" are definitions for convenience, and vice versa. In addition, the above-mentioned operation voltage is an example. The operating voltage is such that the transistor 1164 is turned off in the case of data "0", the transistor 1164 is turned in in the case of data "1", and the transistor 1161 is turned on at the time of writing. , It may be selected so that it is in an off state except during writing, and that the transistor 1163 is turned on during reading. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuit may be used.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 6)

In this embodiment, an example of a circuit diagram of a memory cell having a capacitive element is shown. The memory cell 1170 shown in FIG. 12(a) includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, and a fifth wiring WL ), a transistor 1171 (first transistor), a transistor 1172 (second transistor), and a capacitor 1173. The transistor 1171 uses a material other than an oxide semiconductor for the channel formation region, and the transistor 1172 uses an oxide semiconductor for the channel formation region.

Here, the gate electrode of the transistor 1171, one of the source electrode or the drain electrode of the transistor 1172, and one electrode of the capacitor 1173 are electrically connected. In addition, the source electrode of the first wiring SL and the transistor 1171 is electrically connected, the drain electrode of the second wiring BL and the transistor 1171 is electrically connected, and the third wiring S1 And, the other of the source electrode or the drain electrode of the transistor 1172 is electrically connected, and the gate electrode of the fourth wiring S2 and the transistor 1172 are electrically connected, and the fifth wiring WL The other electrode of the capacitive element 1173 is electrically connected.

Next, the operation of the circuit will be described in detail.

When writing to the memory cell 1170, the first wiring SL is 0V, the fifth wiring WL is 0V, the second wiring BL is 0V, and the fourth wiring S2 is 2V. . When writing data "1", the third wiring S1 is set to 2V, and when writing data "0", the third wiring S1 is set to 0V. At this time, the transistor 1172 is turned on. Further, at the end of the writing, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0V to turn off the transistor 1172.

As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 1171 is about 2V after the data "1" is written, and the potential of the node A is about 0V after the data "0" is written. do.

When reading the memory cell 1170, the first wiring SL is 0V, the fifth wiring WL is 2V, the fourth wiring S2 is 0V, and the third wiring S1 is 0V, The read circuit connected to the second wiring BL is put into an operating state. At this time, the transistor 1172 is turned off.

The state of the transistor 1171 when the fifth wiring WL is 2V will be described. The potential of the node A that determines the state of the transistor 1171 includes a capacitance C1 between the fifth wiring WL and the node A, and a capacitance C2 between the gate electrode of the transistor 1171 and the source electrode and the drain electrode. Depends on

In addition, although the third wiring S1 at the time of reading is set to 0V, it may be charged in a floating state or a potential of 0V or higher. Data "1" and data "0" are definitions for convenience, and vice versa.

The potential of the third wiring S1 at the time of writing is data "0" in a range where the transistor 1172 is turned off after writing and the transistor 1171 is turned off when the fifth wiring potential is 0V. The potentials of "and "1" may be selected respectively. The fifth wiring potential at the time of reading may be selected such that the transistor 1171 is turned off when the data is "0" and the transistor 1171 is turned on when the data is "1". Also, the threshold voltage of the transistor 1171 is an example. Any threshold may be used as long as the state of the above-described transistor 1171 is not changed.

Further, an example of a NOR type semiconductor memory device using a selection transistor having a first gate electrode and a second gate electrode and a memory cell having a capacitive element will be described with reference to FIG. 12B.

A semiconductor device according to an aspect of the present invention shown in FIG. 12B is a memory having a plurality of memory cells arranged in a matrix shape in I rows (I is a natural number of 2 or more) and J columns (J is a natural number). A cell array is provided.

The memory cell array shown in FIG. 12B includes a plurality of memory cells 1180 arranged in a matrix shape in row i (i is a natural number of 3 or more) and j column (j is a natural number of 3 or more), i words Line WL (word line WL_1 to word line WL_i), i capacity lines CL (capacity line CL_1 to capacity line CL_i), and i gate lines BGL (gate) Line BGL_1 to gate line BGL_i], j bit lines BL (bit lines BL_1 to bit lines BL_j), and source lines SL.

Further, each of the plurality of memory cells 1180 (memory cells 1180 (M, N) (where M is a natural number of 1 or more and i or less, N is a natural number of 1 or more and j or less)) is a transistor ( 1181) (M, N), a capacitive element 1183 (M, N), and a transistor 1182 (M, N).

In addition, in a semiconductor memory device, the capacitive element is constituted by a first capacitive electrode, a second capacitive electrode, and a dielectric layer overlapping the first capacitive electrode and the second capacitive electrode. In the capacitive element, electric charges accumulate in accordance with the voltage applied between the first capacitive electrode and the second capacitive electrode.

The transistors 1181 (M, N) are N-channel transistors, and have a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. Note that in the semiconductor memory device of the present embodiment, the transistor 1181 does not necessarily have to be an N-channel transistor.

One of the source electrode and the drain electrode of the transistor 1181 (M, N) is connected to the bit line BL_N, and the first gate electrode of the transistor 1181 (M, N) is connected to the word line WL_M. The second gate electrode of the transistor 1181 (M, N) is connected to the gate line BGL_M. By setting one of the source electrode and the drain electrode of the transistor 1181 (M, N) to be connected to the bit line BL_N, data can be selectively read for each memory cell.

The transistors 1181 (M, N) function as selection transistors in the memory cells 1180 (M, N).

As the transistors 1181 (M and N), a transistor using an oxide semiconductor for the channel formation region can be used.

Transistors 1182 (M, N) are P-channel transistors. In addition, in the semiconductor memory device of this embodiment, the transistor 1182 does not necessarily have to be a P-channel transistor.

One of the source electrode and the drain electrode of the transistor 1182 (M, N) is connected to the source line SL, and the other of the source electrode and the drain electrode of the transistor 1182 (M, N) is a bit line. It is connected to (BL_N), and the gate electrodes of the transistors 1182 (M, N) are connected to the other of the source and drain electrodes of the transistors 1181 (M, N).

The transistors 1182 (M, N) function as output transistors in the memory cells 1180 (M, N). As the transistor 1182 (M, N), for example, a transistor using single crystal silicon for the channel formation region can be used.

The first capacitor electrodes of the capacitor elements 1183 (M, N) are connected to the capacitor line CL_M, and the second capacitor electrodes of the capacitor elements 1183 (M, N) are the transistors 1181 (M, N) is connected to the other of the source electrode and the drain electrode. In addition, the capacitor elements 1183 (M, N) have a function as an accumulated capacitor.

The voltages of each of the word lines WL_1 to WL_i are controlled by, for example, a driving circuit using a decoder.

The voltage of each of the bit lines BL_1 to the bit lines BL_j is controlled by, for example, a driving circuit using a decoder.

The voltage of each of the capacitor lines CL_1 to CL_i is controlled by, for example, a driving circuit using a decoder.

The voltages of each of the gate lines BGL_1 to BGL_i are controlled using, for example, a gate line driving circuit.

The gate line driving circuit is configured by, for example, a circuit including a diode and a first capacitor electrode and a capacitor element electrically connected to the diode anode and the gate line BGL.

By adjusting the voltage of the second gate electrode of the transistor 1181, the threshold voltage of the transistor 1181 can be adjusted. Therefore, the threshold voltage of the transistor 1181 functioning as the selection transistor can be adjusted to make the current flowing between the source electrode and the drain electrode of the transistor 1181 in an off state very small. Therefore, the data retention period in the memory circuit can be lengthened. Further, since the voltage required for writing and reading data can be made lower than that of a conventional semiconductor device, power consumption can be reduced.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 7)

In the present embodiment, an example of a semiconductor device using the transistor shown in the above-described embodiment will be described with reference to FIG. 13.

Fig. 13A shows an example of a semiconductor device having a structure corresponding to so-called DRAM (Dynamic Random Access Memory). The memory cell array 1120 shown in FIG. 13A has a configuration in which a plurality of memory cells 1130 are arranged in a matrix shape. Further, the memory cell array 1120 has m first wirings and n second wirings. In addition, in this embodiment, a 1st wiring is called a bit line BL, and a 2nd wiring is called a word line WL.

The memory cell 1130 is composed of a transistor 1131 and a capacitive element 1132. The gate electrode of the transistor 1131 is connected to the first wiring (word line WL). Further, one of the source electrode or the drain electrode of the transistor 1131 is connected to the second wiring (bit line BL), and the other of the source electrode or the drain electrode of the transistor 1131 is an electrode of the capacitor element. It is connected to one side of. In addition, the other end of the electrode of the capacitive element is connected to the capacitor line CL to supply a constant potential. The transistor shown in the above-described embodiment is applied to the transistor 1131.

The transistor using the oxide semiconductor shown in the above-described embodiment for the channel formation region has a feature that the off-state current is smaller than that of the transistor using the single crystal silicon for the channel formation region. For this reason, when the transistor is applied to the semiconductor device shown in Fig. 13A, which is recognized as a so-called DRAM, it is possible to obtain a substantially nonvolatile memory.

13B shows an example of a semiconductor device having a configuration corresponding to so-called static random access memory (SRAM). The memory cell array 1140 shown in FIG. 13B can be configured such that a plurality of memory cells 1150 are arranged in a matrix shape. In addition, the memory cell array 1140 has a plurality of first wires (word line WL), second wires (bit line BL), and third wires (inverted bit line /BL).

The memory cell 1150 has a first transistor 1151, a second transistor 1152, a third transistor 1153, a fourth transistor 1154, a fifth transistor 1155, and a sixth transistor 1156. have. The first transistor 1151 and the second transistor 1152 function as selection transistors. In addition, one of the third transistor 1153 and the fourth transistor 1154 is an n-channel transistor (here, the fourth transistor 1154), and the other is a p-channel transistor (here, the third transistor 1153) ]to be. That is, the CMOS circuit is composed of the third transistor 1153 and the fourth transistor 1154. Similarly, a CMOS circuit is composed of the fifth transistor 1155 and the sixth transistor 1156.

The first transistor 1151, the second transistor 1152, the fourth transistor 1154, and the sixth transistor 1156 are n-channel transistors, and the transistor shown in the above-described embodiment can be applied. The third transistor 1153 and the fifth transistor 1155 are p-channel transistors, and materials other than an oxide semiconductor (for example, single crystal silicon) are used for the channel formation region.

The structure, method, etc. shown in this embodiment can be used in appropriate combination with the structure, method, etc. shown in other embodiments.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 8)

A CPU (Central Processing Unit) can be configured by using at least a part of a transistor using an oxide semiconductor as a channel formation region.

14A is a block diagram showing a specific configuration of the CPU. The CPU shown in Fig. 14(a) includes an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, and a timing controller on the substrate 1190. (1195), a register 1196, a register controller 1197, a bus interface (Bus I/F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I/F) 1189. . As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1187 may be provided on separate chips. Of course, the CPU shown in Fig. 14(a) is merely an example in which the configuration is simplified, and the actual CPU has various configurations according to its use.

Instructions input to the CPU through the bus interface 1199 are input to the instruction decoder 1191, decoded, and then transmitted to the ALU controller 1192, interrupt controller 1194, register controller 1187, and timing controller 1195. Is entered.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1194 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. In addition, the interrupt controller 1194 processes an interrupt request from an external input/output device or peripheral circuit during the program execution of the CPU based on its priority and mask state. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates signals that control the timing of operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1191, the interrupt controller 1194, and the register controller 1179. For example, the timing controller 1195 is provided with an internal clock generator for generating an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits.

In the CPU shown in Fig. 14A, a storage element is provided in the register 1196. As the storage element of the register 1196, the storage element described in Embodiment 5 can be used.

In the CPU shown in Fig. 14A, the register controller 1179 selects the holding operation in the register 1196 in accordance with the instruction from the ALU 1191. That is, in the memory element of the register 1196, it is selected whether to hold the data by the phase inversion element or the data by the capacitive element. When data retention by the phase inversion element is selected, supply of a power supply voltage to the storage element in the register 1196 is performed. When the retention of data in the capacitor element is selected, rewriting of data to the capacitor element is performed, and the supply of the power supply voltage to the storage element in the register 1196 can be stopped.

As for the power supply stop, as shown in Fig. 14(b) or Fig. 14(c), a switching element is provided between the storage element group and a node to which the power supply potential VDD or power supply potential VSS is supplied. It can be performed by providing. The circuits of Figs. 14(b) and 14(c) will be described below.

14(b) and 14(c) show an example of the configuration of a memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region in a switching element that controls supply of a power supply potential to the memory element. .

The storage device shown in FIG. 14B has a switching element 1141 and a storage element group 1143 having a plurality of storage elements 1142. Specifically, the storage element described in Embodiment 5 can be used for each storage element 1142. A high-level power supply potential VDD is supplied to each storage element 1142 of the storage element group 1143 via a switching element 1141. In addition, the potential of the signal IN and the potential of the low-level power supply potential VSS are supplied to each storage element 1142 of the storage element group 1143.

In Fig. 14B, a transistor having an oxide semiconductor in a channel formation region is used as the switching element 1141, and the switching is controlled by the signal SigA supplied to the gate electrode.

In addition, in FIG. 14B, although the switching element 1141 has a structure having only one transistor, it is not particularly limited and may have a plurality of transistors. When the switching element 1141 has a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in combination of series and parallel.

In Fig. 14B, the supply of the high-level power supply potential VDD to each storage element 1142 of the storage element group 1143 is controlled by the switching element 1141, but switching The element 1141 may control the supply of the low-level power source potential VSS.

14C shows an example of a storage device in which a low-level power supply potential VSS is supplied to each storage element 1142 included in the storage element group 1143 via a switching element 1141. Shows. The switching element 1141 can control the supply of the low-level power supply potential VSS to each memory element 1142 included in the memory element group 1143.

It is recommended that a switching element is provided between the memory element group and a node to which the power supply potential VDD or the power supply potential VSS is supplied, to retain data even when the supply of the power supply voltage is stopped by temporarily stopping the operation of the CPU. It is possible to reduce power consumption. Specifically, for example, the operation of the CPU can be stopped while the user of the personal computer is stopping inputting information to an input device such as a keyboard, thereby reducing power consumption.

Here, the CPU is described as an example, but it can be applied to LSIs such as a DSP (Digital Signal Processor), a custom LSI, and a field programmable gate array (FPGA).

This embodiment can be implemented in appropriate combination with any of the other embodiments.

100: transistor 101: substrate
102: base layer 103: oxide semiconductor layer
104: gate insulating layer 105: gate electrode
106: dopant 107: insulating layer
108: insulating layer 109: contact hole
111: side wall 112: channel protective layer
113: insulating layer 115: back gate electrode
140: transistor 150: transistor
160: transistor 170: transistor
180: transistor 190: transistor
1100: memory cell 1110: memory cell array
1111: wiring driving circuit 1112: circuit
1113: wiring driving circuit 1120: memory cell array
1130: memory cell 1131: transistor
1132: capacitive element 1140: memory cell array
1141: switching element 1142: memory element
1143: memory element group 1150: memory cell
1151: transistor 1152: transistor
1153: transistor 1154: transistor
1155: transistor 1156: transistor
1160: transistor 1161: transistor
1162: transistor 1163: transistor
1164 transistor 1170 memory cell
1171: transistor 1172: transistor
1173: capacitive element 1180: memory cell
1181: transistor 1182: transistor
1183: capacitive element 1189: ROM interface
1190: Substrate 1191: ALU
1192: ALU controller 1193: instruction decoder
1194: Interrupt controller 1195: Timing controller
1196: register 1197: register controller
1198: bus interface 1199: ROM
103a: source region 103b: drain region
103c: Channel formation region 103d: Low concentration region
103e: low concentration region 105a: gate electrode
105b: gate electrode 110a: source electrode
110b: drain electrode

Claims (19)

delete delete As a semiconductor device,
It includes a first transistor and a second transistor,
The first transistor
A semiconductor layer comprising monocrystalline silicon, and
First gate electrode
Including,
The second transistor
The first insulating layer,
An oxide semiconductor layer on the first insulating layer, including a pair of regions interposed through a channel formation region,
A second insulating layer over the oxide semiconductor layer,
A second gate electrode on the second insulating layer, and
A third insulating layer over the second gate electrode
Including,
The first gate electrode is electrically connected to one of the pair of regions,
The first insulating layer contains oxygen,
The third insulating layer includes silicon oxide,
The pair of regions has a lower resistivity than the channel formation region,
The pair of regions includes at least one element selected from rare gas and hydrogen at a higher concentration than the channel forming region,
The first insulating layer is a semiconductor device capable of supplying oxygen to the oxide semiconductor layer. According to claim 3,
The first insulating layer is silicon oxide, the excess of oxygen is a semiconductor device. According to claim 3,
The oxide semiconductor layer comprises In, Ga, and Zn, a semiconductor device. The method of claim 5,
The oxide semiconductor layer includes a crystal region in which the c-axis is aligned parallel to a normal vector of the surface of the oxide semiconductor layer. According to claim 3,
A semiconductor device in which the concentration of the at least one element in the pair of regions is 5×10 ¹⁹ atoms/cm ³ or more and 1×10 ²² atoms/cm ³ or less. delete According to claim 3,
The second gate electrode includes a first layer including tantalum nitride and a second layer including tungsten over the first layer. The semiconductor device according to claim 3, wherein the third insulating layer contains hydrogen in a concentration of 0.1 atomic% or more and 25 atomic% or less. According to claim 3,
A fourth insulating layer over the third insulating layer
Additionally,
The fourth insulating layer comprises aluminum oxide, a semiconductor device. A method for manufacturing a semiconductor device,
Forming a first insulating layer,
Forming an oxide semiconductor layer on the first insulating layer,
Forming a second insulating layer on the oxide semiconductor layer,
Forming a gate electrode on the second insulating layer,
Forming a third insulating layer on the gate electrode, and
By using the gate electrode as a mask, at least one element selected from rare gas and hydrogen is passed through the second insulating layer and added to the oxide semiconductor layer by doping or ion implantation to form a pair of regions. Steps to
Including,
The first insulating layer contains oxygen,
The third insulating layer includes silicon oxide,
The oxide semiconductor layer includes In, Ga, and Zn,
The pair of regions is interposed through the channel formation region of the oxide semiconductor layer,
The gate electrode overlaps the channel formation region, the method of manufacturing a semiconductor device. The method of claim 12,
The method of manufacturing a semiconductor device, wherein the concentration of the at least one element in the pair of regions is 5×10 ¹⁹ atoms/cm ³ or more and 1×10 ²² atoms/cm ³ or less. The method of claim 12,
The third insulating layer is formed by a CVD method with a substrate temperature in a range of 300°C or higher and 550°C or lower. The method of claim 12,
The third insulating layer contains hydrogen in a concentration of 0.1 atomic% or more and 25 atomic% or less, a method of manufacturing a semiconductor device. The method of claim 12,
Forming a fourth insulating layer comprising aluminum oxide on the third insulating layer
A method of manufacturing a semiconductor device further comprising a. According to claim 3,
A semiconductor device in which the amount of oxygen emitted from the first insulating layer in the temperature rising gas spectroscopy is 3.0×10 ²⁰ atoms/cm ³ or more when converted into oxygen atoms. The method of claim 12,
The method of manufacturing a semiconductor device in which the amount of oxygen emitted from the first insulating layer in the temperature rising gas spectroscopy is 3.0×10 ²⁰ atoms/cm ³ or more when converted into oxygen atoms. The method of claim 12,
The oxide semiconductor layer is formed by sputtering,
The oxide semiconductor layer comprises a crystal region in which the c-axis is aligned parallel to a normal vector of the surface of the oxide semiconductor layer.

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