KR102197953B1 - Stereoscopic image display device - Google Patents

Abstract

The present invention provides a stereoscopic image display device, wherein a plurality of data lines to which a data voltage is supplied, a plurality of scan control lines to which a scan pulse is supplied, a plurality of sensing control lines to which a gate pulse is supplied, and a reference voltage are supplied. A display panel including a plurality of reference lines and a plurality of pixels; And setting the driving mode of the display panel to a 3D display mode or a 2D display mode, driving the display panel in a data addressing period and a light emission period in a set 3D display mode or 2D display mode, and a data addressing period of the 3D display mode. And a panel driver configured to turn off all of the plurality of pixels and simultaneously emit the plurality of pixels during a light emission period of the 3D display mode.

Description

Stereoscopic image display device {STEREOSCOPIC IMAGE DISPLAY DEVICE}

The present invention relates to a stereoscopic image display device, and more particularly, to a stereoscopic image display device capable of preventing interference between a left-eye image and a right-eye image.

A stereoscopic image display device is a device that separately displays a right-eye image and a left-eye image having Binocular Parallax to each of the viewer's right and left eyes. That is, the stereoscopic image display device allows the right-eye image to be recognized only in the viewer's right eye and the left-eye image to be recognized only in the viewer's left eye, thereby allowing the viewer to view a 3D (Dimension) image with a three-dimensional effect. Such a 3D image display device may be classified into a spectacle method for wearing glasses and a glasses-free method for not wearing glasses.

The spectacle method realizes a stereoscopic image with glasses equipped with a liquid crystal shutter. This liquid crystal shutter method shows different images in each of the left and right eyes. That is, the liquid crystal shutter type stereoscopic image display device alternately drives the left-eye liquid crystal shutter and the right-eye liquid crystal shutter of the glasses so as to alternately display the left-eye image and the right-eye image. The right eye image passing through the liquid crystal shutter is separated and provided to the viewer.

Although such a liquid crystal shutter type stereoscopic image display device provides a three-dimensional effect by separating the left-eye image and the right-eye image, the left-eye image and the right-eye image are mixed by the sequential light emission method, resulting in crosstalk that appears as a double image. There is a problem in that the quality of a stereoscopic image is deteriorated. In order to solve this problem, Korean Patent Application Publication No. 10-2011-0013693 (hereinafter referred to as "prior patent document") discloses a shutter type 3D display that drives pixels in a simultaneous light emission method instead of a black frame insertion technology. Are doing.

However, the prior patent document prevents interference between the left-eye image and the right-eye image by controlling the simultaneous emission or non-emission of the pixels through the swing of the driving power supply ELVDD supplied to the pixel. ), a high specification power circuit is required, and reliability decreases due to an increase in the load of the power circuit.

In addition, since the prior patent document charges the threshold voltage of the driving transistor in the capacitor using the transistor and the capacitor included in the pixel, when displaying an image at a frame driving frequency of 120 Hz or higher, the threshold voltage of the driving transistor is charged to the capacitor. Due to this decrease, there is a problem that it is difficult to compensate the threshold voltage of the driving transistor.

The present invention has been conceived to solve the above-described problem, and it is an object of the present invention to provide a stereoscopic image display device capable of preventing interference between a left-eye image and a right-eye image by using a pixel switching operation.

In addition, an object of the present invention is to provide a stereoscopic image display device in which a threshold voltage of a driving transistor included in a pixel is sensed externally and compensated through data correction.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those of ordinary skill in the art from such technology and description.

A stereoscopic image display device according to the present invention for achieving the above-described technical problem includes a plurality of data lines to which a data voltage is supplied, a plurality of scan control lines to which a scan pulse is supplied, a plurality of sensing control lines to which a gate pulse is supplied, and A display panel including a plurality of reference lines to which a reference voltage is supplied and a plurality of pixels; And setting the driving mode of the display panel to a 3D display mode or a 2D display mode, driving the display panel in a data addressing period and a light emission period in a set 3D display mode or 2D display mode, and a data addressing period of the 3D display mode. And a panel driver configured to turn off all of the plurality of pixels and simultaneously emit the plurality of pixels during a light emission period of the 3D display mode.
Each of the plurality of pixels includes an organic light-emitting device; A first switching transistor for supplying the data voltage to the first node by connecting a data line to the first node in response to the scan pulse; A driving transistor that is driven according to a voltage difference between a data voltage supplied to the first node and a reference voltage supplied to a second node connected to the organic light emitting device to control a current flowing through the organic light emitting device; A second switching transistor supplying the reference voltage to a second node; And a capacitor connected between the first node and the second node.
A gate electrode of the driving transistor is connected to the first node, and a source electrode of the driving transistor and an anode electrode of the organic light emitting device are connected to the second node.
In the data addressing period of the 3D display mode, the second switching transistor of each of the pixels is turned on to supply the reference voltage to the second node, and the second switching transistor of each of the pixels is turned on in the emission period of the 3D display mode. The switching transistor is turned off to cut off the reference voltage supplied to the second node.

The reference voltage may be lower than a threshold voltage of the organic light emitting device.

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According to the present invention, a black image is inserted between the left-eye image and the right-eye image by simultaneously turning off or simultaneously emitting organic light-emitting elements of all pixels by simply switching the switching transistor included in the pixel to prevent interference between the left-eye image and the right-eye image. There is an effect that it can be prevented.

In addition, according to the present invention, it is possible to implement both a black frame insertion technology and a simultaneous light emission method simply by switching a switching transistor included in a pixel without swinging a power source.

In addition, according to the present invention, by externally sensing the threshold voltage of the driving transistor included in each pixel through the sensing mode and compensating through data correction, it is possible to improve image quality defects such as spots due to the threshold voltage deviation of the driving transistor. It works.

1 is a diagram illustrating a 3D image display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for describing a structure of a pixel shown in FIG. 1.
3 is a block diagram illustrating a column driver illustrated in FIG. 1.
FIG. 4 is a block diagram illustrating a sensing line driver illustrated in FIG. 1.
5 is a driving waveform diagram of a typical pixel in a sensing mode in the stereoscopic image display device according to the present invention.
6 is a driving waveform diagram of a typical pixel in a 2D display mode in the stereoscopic image display device according to the present invention.
7 is a diagram illustrating an operation of one pixel in a data addressing period shown in FIG. 6.
FIG. 8 is a diagram illustrating an operation of one pixel in the emission period illustrated in FIG. 6.
9 is a driving waveform diagram in a 3D display mode in the stereoscopic image display device according to the present invention.

The meaning of the terms described in this specification should be understood as follows.

Singular expressions should be understood as including plural expressions unless clearly defined differently in context, and terms such as "first" and "second" are used to distinguish one element from other elements, The scope of rights should not be limited by these terms.

It is to be understood that terms such as "comprise" or "have" do not preclude the presence or addition of one or more other features or numbers, steps, actions, components, parts, or combinations thereof.

The term “at least one” is to be understood as including all possible combinations from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” means 2 among the first item, the second item, and the third item as well as each of the first item, the second item, or the third item. It means a combination of all items that can be presented from more than one.

Hereinafter, preferred embodiments of a stereoscopic image display device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram for describing a 3D image display device according to an exemplary embodiment of the present invention, and FIG. 2 is a diagram for describing a structure of a pixel illustrated in FIG. 1.

1 and 2, a stereoscopic image display device according to an exemplary embodiment of the present invention includes a display panel 100 and a panel driver 200.

The display panel 100 includes first to mth (where m is a natural number) scan control lines SL1 to SLm, first to mth sensing control lines SSL1 to SSLm, and first to nth (but, n is a natural number greater than m) data lines DL1 to DLn, first to nth reference lines RL1 to RLn, a plurality of high potential voltage lines PL, low potential voltage lines LVL, and a plurality of pixels Includes (P).

Each of the first to m-th scan control lines SL1 to SLm is formed in parallel to have a predetermined interval along a first direction, that is, a horizontal direction of the display panel 100.

Each of the first to mth sensing control lines SSL1 to SSLm is formed at regular intervals to be parallel to each of the scan control lines SL1 to SLm.

The first to nth data lines DL1 to DLn are in the second direction of the display panel 100, that is, vertically, so as to cross the scan control lines SL1 to SLm and the sensing control lines SSL1 to SSLm. They are formed side by side to have a certain interval along the direction.

Each of the first to nth reference lines RL1 to RLn is formed at regular intervals to be parallel to each of the data lines DL1 to DLn. Each of the first to nth reference lines RL1 to RLn is individually connected to a pixel P formed on each horizontal line corresponding to a length direction of each of the scan control lines SL1 to SLm, and each of the data It is commonly connected to the pixels P formed on each vertical line corresponding to the length direction of the lines DL1 to DLn. That is, each of the first to nth reference lines RL1 to RLn is commonly connected to the pixels P formed in the pixel column of the display panel 100, and is formed in the pixel row of the display panel 100. It is individually connected to each of the (P)s.

Each of the plurality of high potential voltage lines PL is formed at regular intervals to be parallel to each of the data lines DL1 to DLn. Here, each of the plurality of high potential voltage lines PL may be formed at regular intervals to be parallel to each of the scan control lines SL1 to SLm. Each of the plurality of high potential voltage lines PL is provided with a high potential from an external high potential voltage supply unit (not shown) through a driving power common line (not shown) formed above and/or below the display panel 100. Receives voltage (EVdd).

The low-potential voltage line LVL is formed in a cylindrical shape on the entire surface of the display panel 100 or is constant so as to be parallel to each of the data lines DL1 to DLn or the scan control lines SL1 to SLm. It can also be formed at intervals. The low potential voltage line LVL receives a low potential voltage EVss from an external low potential voltage supply unit (not shown).

Each of the plurality of pixels P is formed for each pixel area defined by each of the first to m-th scan control lines SL1 to SLm crossing each other and each of the first to nth data lines DL1 to DLn. do. Here, each of the plurality of pixels P may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. At least three adjacent pixels among the plurality of pixels P constitute one unit pixel displaying one image. For example, each unit pixel may be formed of an adjacent red pixel, a green pixel, a blue pixel, and a white pixel, or may be formed of an adjacent red pixel, a green pixel, and a blue pixel.

Each of the plurality of pixels P includes an organic light-emitting device OLED and a pixel circuit PC.

The pixel circuit PC may include a first switching transistor Tsw1, a second switching transistor Tsw2, the driving transistor Tdr, and a capacitor Cst. Here, the transistors Tsw1, Tsw2, and Tdr are N-type thin film transistors TFT and may be a-Si TFT, poly-Si TFT, oxide TFT, organic TFT, or the like.

The first switching transistor Tsw1 is switched by the scan pulse SP supplied to the scan control line SL to apply voltages Vdata and Vsen supplied to the data line DL according to the mode to the driving transistor Tdr. To the gate electrode. To this end, the first switching transistor Tsw1 includes a gate electrode connected to an adjacent scan control line SL, a first electrode connected to an adjacent data line DL, and a first node that is a gate electrode of the driving transistor Tdr. and a second electrode connected to (n1). Here, the first and second electrodes of the first switching transistor Tsw1 may be a source electrode or a drain electrode according to a current direction.

The second switching transistor Tsw2 is switched by a gate pulse GP supplied to the sensing control line SSL to apply a voltage Vref or Vpre supplied to the reference line RL according to the mode as the driving transistor Tdr. It is supplied to the second node n2 which is the source electrode of. To this end, the second switching transistor Tsw2 includes a gate electrode connected to an adjacent sensing control line SSL, a first electrode connected to an adjacent reference line RL, and a second electrode connected to a second node n2. do. Here, the first and second electrodes of the second switching transistor Tsw2 may be a source electrode or a drain electrode according to a current direction.

The capacitor Cst includes a gate electrode and a source electrode of the driving transistor Tdr, that is, first and second electrodes connected between the first and second nodes n1 and n2. The first electrode of the capacitor Cst is connected to the first node n1, and the second electrode of the capacitor Cst is connected to the second node n2. The capacitor Cst charges a voltage difference between the voltages supplied to each of the first and second nodes n1 and n2 according to the switching of each of the first and second switching transistors Tsw1 and Tsw2, and then The driving transistor Tdr is driven according to the set voltage.

The driving transistor Tdr is driven according to a voltage difference between a gate voltage and a source voltage to control an amount of current flowing from the high potential voltage line PL to the organic light emitting diode OLED. To this end, the driving transistor Tdr includes a gate electrode connected to the first node n1, a source electrode connected to the second node n2, and a drain electrode connected to a high potential voltage line PL.

The organic light-emitting device OLED emits monochromatic light having a luminance corresponding to the data current Ioled by emitting light by the data current Ioled flowing when the driving transistor Tdr is driven. To this end, the organic light-emitting device OLED includes a first electrode (eg, an anode electrode) connected to the second node n2, an organic layer (not shown) formed on the first electrode, and a second electrode connected to the organic layer. It includes an electrode (eg, a cathode electrode). In this case, the organic layer may be formed to have a structure of a hole transport layer/organic emission layer/electron transport layer or a hole injection layer/hole transport layer/organic emission layer/electron transport layer/electron injection layer. Furthermore, the organic layer may further include a functional layer for improving the luminous efficiency and/or lifespan of the organic emission layer. In addition, the second electrode may be connected to a low potential power line LVL or may be a low potential power line LVL.

The panel driver 200 sets the driving mode of the display panel 100 to a 3D display mode or a 2D display mode, and causes the display panel 100 to emit light with a data addressing period according to the set 3D display mode or 2D display mode. Drive in section. In this case, when the driving frequency of the vertical synchronization signal, which is the frame driving frequency, is 120 Hz, the driving frequency of each of the data addressing period and the emission period may be set to 240 Hz, but is not limited thereto.

In the data addressing period of the 3D display mode, the panel driver 200 supplies a reference voltage Vref to the second node n2 of each of the plurality of pixels P to supply all of the plurality of pixels P. Turn it off. That is, the panel driver 200 turns on the second switching transistors Tsw2 of all the pixels P during the data addressing period of the 3D display mode, so that the reference voltage is lower than the threshold voltage of the corresponding organic light emitting diode OLED. (Vref) is supplied to the anode electrode of the organic light-emitting device OLED to turn off the organic light-emitting devices OELD of all the pixels P. In addition, in the light emission period of the 3D display mode, the panel driver 200 cuts off the reference voltage Vref supplied to the second node n2 of each of the plurality of pixels P. ) Simultaneously. That is, the panel driver 200 turns off the second switching transistor Tsw2 of all the pixels P during the light emission period of the 3D display mode so that current flows through the corresponding organic light emitting device OLED. The organic light emitting device (OLED) of (P) is simultaneously emitted. Accordingly, in the 3D display mode, the panel driver 200 performs data addressing in the state in which all the pixels P are turned off in the data addressing period, and displays images on all the pixels P at the same time in the light emission period. Prevents interference between the image and the right eye image.

In the data addressing period of the 2D display mode, the panel driver 200 sequentially supplies the data voltage Vdata to the pixels P formed on the corresponding horizontal line for each horizontal period, and simultaneously supplies the data voltage Vdata to the pixels P. 2 A reference voltage Vref is supplied to the node n2 so that the data voltage Vdata and the reference voltage Vref are stored in the capacitor Cst of the pixel P. Accordingly, in the data addressing period of the 2D display mode, the organic light emitting diodes (OLED) of the pixels P formed on each horizontal line are not all turned off like the data addressing period of the 3D display mode, It is sequentially turned off in units of horizontal lines according to the addressing section. And, in the light emission period of the 2D display mode, the panel driver 200 cuts off the data voltage Vdata and the reference voltage Vref supplied to the corresponding pixels P after the addressing period of each horizontal line. The organic light-emitting device OLED of the pixel P is emitted by the voltage stored in the capacitor Cst of the pixel P. Accordingly, in the emission period of the 2D display mode, the organic light-emitting elements (OLED) of the pixels P formed on each horizontal line do not emit light at the same time as in the emission period of the 3D display mode, and one horizontal line within the frame The light is sequentially emitted as a unit, and light is emitted before the data addressing period of the next frame.

Additionally, the panel driver 200 sets the driving mode of the display panel 100 to a sensing mode.

The sensing mode may be defined as driving a pixel to sense a driving characteristic value of the driving transistor Tdr for each pixel, that is, a threshold voltage, and such a sensing mode is a user setting of a stereoscopic image display device before product shipment, and a stereoscopic image display device. It may be performed at a user's setting or every set period after product shipment of the product, and the set period may be a power on/off time point of the stereoscopic image display device.

In the sensing mode, the panel driver 200 senses a threshold voltage of the driving transistor for each pixel through each of the plurality of reference lines RL1 to RLn formed on the display panel 100 to receive sensing data Sdata. And corrects the data voltage for each pixel to be supplied to the corresponding pixel P in the data address period of the 2D display mode or the 3D display mode based on the sensing data Sdata.

The panel driving unit 200 includes a timing control unit 210, a voltage supply unit 220, a column driving unit 230, a scan line driving unit 240, a sensing line driving unit 250, and a shutter driving signal generation unit 260. ).

The timing controller 210 sets the driving mode of the display panel 100 to a 3D display mode or a 2D display mode based on a timing synchronization signal (TSS) or a user manipulation signal input from an external driving system (or image processing device). Alternatively, the sensing mode is set and input data for each pixel is aligned to generate pixel data for each pixel, and the data control signal DCS corresponding to the set driving mode, the first and second row control signals RCS1, RCS2), a liquid crystal shutter control signal LSCS, and a light emission control signal ECS.

In the sensing mode, the timing controller 210 operates the driving transistor Tdr of each pixel P in a source follow mode for each pixel driving period of a horizontal line, so as to reduce the threshold of the driving transistor Tdr for each pixel. The sensing pixel data DATA for sensing the voltage Vth_Tdr, the data control signal DCS, and the emission control signal ECS are generated. In this case, the sensing pixel data DATA may have a gray scale value corresponding to a set target voltage for operating the driving transistor Tdr in the source follower mode.

In the 2D display mode, the timing controller 210 generates a data compensation value based on the threshold voltage Vth_Tdr of the driving transistor Tdr for each pixel stored in the memory unit M in the sensing mode, , The input data for each pixel Idata is corrected according to the data compensation value to generate the pixel data DATA for each pixel, and the generated pixel data DATA for each pixel is transferred to the column driver 230. And a data control signal DCS corresponding to the 2D display mode, first and second row control signals RCS1 and RCS2, and an emission control signal ECS based on an input timing synchronization signal TSS. Generate.

Meanwhile, when one unit pixel formed on the display panel 100 is composed of a red pixel, a green pixel, a blue pixel, and a white pixel, the timing control unit 210 determines the brightness and/or driving of each pixel P. Based on the four-color data conversion method (RGB to RWGB) set according to the luminance characteristics of each unit pixel according to the characteristics, the input data of red, green, and blue (Idata) is converted into four color data of red, green, blue and white. And correcting the converted four-color data according to the threshold voltage (Vth_Tdr) of the driving transistor Tdr included in each of the red, green, blue, and white pixels to generate pixel-specific pixel data DATA. I can. In this case, the timing controller 210 converts red, green, and blue input data (Idata) into red according to the data conversion method disclosed in Korean Patent Laid-Open No. 10-2013-0060476 or 10-2013-0030598. , Green, blue and white data can be converted into four colors.

In the 3D display mode, the timing control unit 210 arranges the pixel-specific input data (Idata) corresponding to the left-eye image or the right-eye image input from the outside to fit the pixel arrangement structure of the display panel 100, When data DATA is generated and provided to the column driver 230, the data control signal DCS corresponding to the 3D display mode and the first and second data are generated based on the input timing synchronization signal TSS. Row control signals RCS1 and RCS2, and emission control signals ECS are generated. Here, as in the 2D display mode, the timing control unit 210 includes the left eye image or the left eye image based on the threshold voltage Vth_Tdr of the driving transistor Tdr for each pixel stored in the memory unit M by the sensing mode. The pixel data DATA for each pixel may be generated by correcting the input data Idata for each pixel corresponding to the right eye image.

In addition, in the 3D display mode, the timing controller 210 includes the left eye liquid crystal shutter of the 3D image glasses (not shown) based on the pixel-specific input data Idata and the timing synchronization signal TSS input from the outside. A liquid crystal shutter control signal LSCS for alternately driving the right-eye liquid crystal shutter in units of frames is generated.

The voltage supply unit 220 generates a gate-on voltage (Von) and a gate-off voltage (Voff) using an external input power source (Vin), respectively, to the scan line driver 240 and the sensing line driver 250. Supply. Here, the gate-on voltage Von has a voltage level for turning on the switching transistors Tsw1 and Tsw2 of the pixel P, and the gate-off voltage Voff turns the switching transistors Tsw1 and Tsw2. -It has a voltage level to turn it off.

The column driver 230 is connected to the first to nth data lines DL1 to DLn and the first to nth reference lines RL1 to RLn, and is in a display mode according to the mode control of the timing controller 210. Or it operates in sensing mode.

In the display mode, the column driver 230 responds to the data control signal DCS from the timing controller 210, in response to the 2D display mode or 3D input from the timing controller 210 in units of one horizontal period. The pixel data DATA for each pixel in the display mode is converted into a data voltage Vdata and supplied to the data lines DL1 to DLn, and a reference voltage Vref is supplied to the reference lines RL1 to RLn. And, in the sensing mode, the column driver 230 drives each pixel through reference lines RL1 to RLn in response to a data control signal DCS in a sensing mode supplied from the timing controller 210. The sensing data Sdata is generated by sensing a voltage (or a source voltage) corresponding to the current flowing through the transistor Tdr, and the generated sensing data Sdata is provided to the timing controller 210.

The scan line driver 240 is connected to one side and/or the other side of each of the first to mth scan control lines SL1 to SLm. The scan line driver 240 uses a gate-on voltage (Von) and a gate-off voltage (Voff) supplied from the voltage supply unit 220, and provides a 3D display mode and a 2D display from the timing controller 210. The first to m-th scan pulses SP1 to SPm having a gate-on voltage Von of a pulse width set according to the first row control signal RCS1 of the mode or sensing mode are generated. It is sequentially supplied to the control lines SL1 to SLm.

The sensing line driver 250 is connected to one side and/or the other side of each of the first to mth sensing control lines SSL1 to SSLm. During the data addressing period of the 3D display mode, the sensing line driver 250 turns on the second switching transistors Tsw2 of all pixels P according to the emission control signal ECS. The first to mth gate pulses GP1 to GPm of (Von) are simultaneously supplied to the first to mth sensing control lines SSL1 to SSLm. In addition, the sensing line driver 250 turns off the gates for simultaneously turning off the second switching transistors Tsw2 of all pixels P according to the emission control signal ECS during the emission period of the 3D display mode. The first to mth gate pulses GP1 to GPm of voltage Voff are simultaneously supplied to the first to mth sensing control lines SSL1 to SSLm. In addition, in the 2D display mode or the sensing mode, the sensing line driver 250 has a pulse width set for data addressing in units of one horizontal period according to the second row control signal RCS2 and the emission control signal ECS. First to m-th gate pulses GP1 to GPm having a gate-on voltage Von of are sequentially generated and sequentially supplied to the m-th sensing control lines SSL1 to SSLm.

The shutter driving signal generation unit 260 alternately drives the left-eye liquid crystal shutter or the right-eye liquid crystal shutter of the 3D image glasses in response to the liquid crystal shutter control signal LSCS supplied from the timing control unit 210. A liquid crystal shutter driving signal LSDS is generated, and the generated liquid crystal shutter driving signal LSDS is transmitted to the 3D image glasses according to a short-range wireless communication method. Accordingly, the glasses for 3D images receive the liquid crystal shutter driving signal LSDS transmitted from the shutter driving signal generator 260 and open the left-eye liquid crystal shutter or the right-eye liquid crystal shutter according to the received liquid crystal shutter driving signal LSDS. By alternately driving in units of frames, the left-eye image displayed on the display panel 100 passes through only the left-eye liquid crystal shutter and is provided to the left eye of the viewer, and the right-eye image displayed on the display panel 100 passes through only the right-eye liquid crystal shutter. It should be provided to the viewer's right eye.

3 is a block diagram illustrating a column driver illustrated in FIG. 1.

1 to 3, a column driver 230 according to the present invention includes a data driver 232, a switching unit 234, and a sensing unit 236.

The data driver 232 is supplied from the timing controller 210 in response to a data control signal DCS supplied from the timing controller 210 according to the 3D display mode, the 2D display mode, or the sensing mode. The pixel data (or sensing pixel data) DATA for one horizontal line is converted into a data voltage Vdata and supplied to the corresponding data lines DL1 to DLn. That is, the data driver 232 subdivides a plurality of gamma voltages (RGV) supplied from the outside to generate a plurality of gray voltages, and sequentially sequentially generates pixel data for one horizontal line according to the data control signal DCS. And a gray voltage corresponding to the gray value of the sampled pixel data among a plurality of gray voltages as the data voltage Vdata, and supplied to the corresponding data line DL.

In the 3D display mode or the 2D display mode, the switching unit 234 applies a reference voltage Vref supplied from an external source to a plurality of reference lines in response to a data control signal DCS supplied from the timing controller 210. It is supplied to (RL1 to RLn). In addition, in the sensing mode, in response to the data control signal DCS supplied from the timing controller 210, the switching unit 234 applies a precharging voltage Vpre supplied from the outside to a plurality of reference lines RL1. To RLn) to initialize each of the plurality of reference lines RL1 to RLn to a precharging voltage Vpre, and then connect each of the plurality of reference lines RL1 to RLn to the sensing unit 236. To this end, the switching unit 234 according to an example may be configured to include first to n-th switching circuits 234a to 234n connected to each of the plurality of reference lines RL1 to RLn and the sensing unit 236. In addition, the switching circuits 234a to 234n may be multiplexers. Meanwhile, the precharging voltage Vpre may be replaced with the reference voltage Vref.

In the sensing mode, the sensing unit 236 is connected to a plurality of reference lines RL1 to RLn through the switching unit 234, respectively, to sense voltages of each of the plurality of reference lines RL1 to RLn, and sense The sensing data Sdata for each pixel corresponding to the voltage is generated and provided to the timing controller 210. To this end, the sensing unit 236 is connected to a plurality of reference lines RL1 to RLn through the switching unit 234, respectively, to analog-digital convert a sensing voltage to generate the sensing data Sdata for each pixel. The first to nth analog-to-digital converters 236a to 236n may be included.

FIG. 4 is a block diagram illustrating a sensing line driver illustrated in FIG. 1.

1 to 4, the sensing line driver 250 according to the present invention includes a gate pulse generator 252 and a voltage selector 254.

The gate pulse generator 252 responds to the second row control signal RCS2 supplied from the timing controller 210, and the gate-on voltage Von has a pulse width set for data addressing in units of one horizontal period. The first to mth gate pulses GP1 to GPm having) are sequentially generated and output. For example, the gate pulse generator 252 generates first to m-th shift signals by sequentially shifting a start signal having the pulse width among the second row control signals RCS2 according to a clock signal. And, using the gate-on voltage (Von) and the gate-off voltage (Voff) supplied from the voltage supply unit 220, each of the first to mth shift signals to the first to mth gate pulses (GP1 to GPm). Level shifted and output sequentially.

The voltage selector 254 responds to the emission control signal ECS from the timing control unit 210, the output signal of the gate pulse generator 252, a gate-on voltage Von, and a gate-off voltage Voff. ) Is selected and supplied to the sensing control line (SSL1 to SSLm).

Specifically, the voltage selector 254 includes first to m-th gate pulses GP1 to GPm of a gate-on voltage Von according to the emission control signal ECS supplied to the data addressing period of the 3D display mode. Is simultaneously supplied to the first to m-th sensing control lines SSL1 to SSLm to turn on the second switching transistor Tsw2 of all the pixels P.

In addition, the voltage selector 254 receives the first to m-th gate pulses GP1 to GPm of the gate-off voltage Voff according to the emission control signal ECS supplied to the emission period of the 3D display mode. The second switching transistors Tsw2 of all the pixels P are simultaneously turned off by simultaneously supplying the first to mth sensing control lines SSL1 to SSLm.

In addition, the voltage selector 254 includes first to m-th gate pulses GP1 to GP1 to be supplied from the gate pulse generator 252 according to the emission control signal ECS supplied to the 2D display mode or the sensing mode. GPm) is sequentially supplied to the mth sensing control lines SSL1 to SSLm to sequentially turn on the second switching transistor Tsw2 for each pixel formed on each horizontal line in units of one horizontal period.

As described above, the voltage selection unit 254 includes first to m-th selection circuits M1 to Mm.

Each of the first to m-th selection circuits M1 to Mm includes a control terminal to which the emission control signal ECS is supplied, a first input terminal to which the gate-on voltage Von is supplied, and the gate-off voltage Voff. The second input terminal is supplied, a third input terminal supplied with the gate pulse GP from the gate pulse generator 252, and an output terminal connected to the sensing control line SSL. Each of the first to m-th selection circuits M1 to Mm may be a multiplexer.

Each of the first to m-th selection circuits M1 to Mm is the gate-on voltage Von supplied to the first input terminal according to the emission control signal ECS supplied to the data addressing period of the 3D display mode. Is selected and supplied to the corresponding sensing control line SSL during the data addressing period of the 3D display mode.

In addition, each of the first to m-th selection circuits M1 to Mm has the gate-off voltage Voff supplied to the second input terminal according to the emission control signal ECS supplied to the emission period of the 3D display mode. ) To supply to the corresponding sensing control line SSL during the light emission period of the 3D display mode.

In addition, each of the first to m-th selection circuits M1 to Mm selects a gate pulse GP supplied to a third input terminal according to the emission control signal ECS supplied to the 2D display mode or the sensing mode. Thus, they are sequentially supplied to the m-th sensing control lines SSL1 to SSLm.

5 is a driving waveform diagram of a typical pixel in a sensing mode in the stereoscopic image display device according to the present invention.

A method of driving a stereoscopic image display device according to the present invention in a sensing mode will be described with reference to FIGS. 1 to 5.

In the sensing mode, the pixel P is driven in the first to third periods t1, t2, and t2.

In the first period t1, the first switching transistor Tsw1 is turned on by the scan pulse SP of the gate-on voltage Von, and the sensing data voltage Vsen supplied to the data line DL. It is supplied to the first node n1, that is, the gate electrode of the driving transistor Tdr, and the second switching transistor Tsw2 is turned on by the gate pulse GP of the gate-on voltage Von to turn on the reference line ( The precharging voltage Vpre (or reference voltage Vref) supplied to RL is supplied to the second node n2, that is, the source electrode of the driving transistor Tdr. At this time, in order to prevent the organic light-emitting device OLED from emitting light when the driving transistor Tdr is driven according to the sensing data voltage Vsen, the first switching transistor Tsw1 is a second switching transistor Tsw2. It is preferable to turn on later a certain time. Accordingly, during the first period t1, the source voltage of the driving transistor Tdr and the reference line RL are initialized to the precharging voltage Vpre. In this case, the organic light-emitting device OLED does not emit light by the precharging voltage Vpre supplied to the second node n2 through the second switching transistor Tsw2.

Subsequently, in the second period t2, in a state in which each of the first and second switching transistors Tsw1 and Tsw2 operates in a linear driving mode by a gate-on voltage Von, the switching unit ( According to the switching of 234, the reference line RL is converted to a floating state. Accordingly, the driving transistor Tdr operates in the source follower mode by the sensing data voltage Vsen, which is a bias voltage supplied to the gate electrode, and thus, the sensing data voltage is applied to the floating reference line RL. The difference voltage Vsen-Vth between (Vsen) and the threshold voltage (Vth_Tdr) of the driving transistor Tdr is charged.

Subsequently, in the third period t3, the second switching transistor Tsw2 is generated by the gate pulse GP of the gate-off voltage Voff while the turn-on state of the first switching transistor Tsw1 is maintained. Is turned off, and at the same time, the reference line RL is connected to the sensing unit 236 by the switching unit 234. Accordingly, the sensing unit 236 senses the voltage charged in the reference line RL, converts the sensed voltage to analog-digital, generates sensing data Sdata, and provides it to the timing controller 210. .

Accordingly, the timing control unit 210 is based on the sensing data Sdata provided from the sensing unit 236 and the sensing data voltage Vsen in the third period t3, and the driving transistor Tdr The threshold voltage Vth_Tdr of is calculated, and the calculated threshold voltage Vth_Tdr of the driving transistor Tdr is stored in the memory unit M. In this case, the threshold voltage Vth_Tdr of the driving transistor Tdr may be a voltage obtained by subtracting the sensing voltage of the sensing unit 236 from the sensing data voltage Vsen.

6 is a driving waveform diagram of a typical pixel in a 2D display mode in a 3D image display device according to the present invention, and FIG. 7 is a diagram illustrating an operation of one pixel in the data addressing period shown in FIG. 6, and FIG. 6 is a diagram illustrating an operation of one pixel in the emission period shown in FIG. 6.

A method of driving a 3D image display device according to the present invention in a 2D display mode will be described with reference to FIGS. 6 to 8.

In the 2D display mode, one pixel is driven in the data addressing period DAT and the light emission period ET.

First, as shown in FIGS. 6 and 7, in the data addressing period DAT, the first switching transistor Tsw1 is turned on by the scan pulse SP of the gate-on voltage Von, so that the data line The display data voltage Vdata supplied to the (DL) is supplied to the first node n1, that is, the gate electrode of the driving transistor Tdr, and is applied to the second node by the gate pulse GP of the gate-on voltage Von. The switching transistor Tsw2 is turned on and the reference voltage Vref supplied to the reference line RL is supplied to the second node n2, that is, the source electrode of the driving transistor Tdr.

In the data addressing period DAT, the display data voltage Vdata charged in the capacitor Cst includes a voltage for compensating for the threshold voltage Vth_dr of the corresponding driving transistor Tdr. In addition, in order to prevent the organic light-emitting device OLED from emitting light when the driving transistor Tdr is driven according to the display data voltage Vdata, the first switching transistor Tsw1 is a second switching transistor Tsw2. It is preferable to turn on later a certain time. Accordingly, during the data addressing period DAT, the difference between the display data voltage Vdata and the reference voltage Vref in the capacitor Cst connected to the first node n1 and the second node n2 The voltage (Vdata-Vref) is charged. At this time, the organic light-emitting device OLED does not emit light by the reference voltage Vref supplied to the second node n2 through the second switching transistor Tsw2.

Subsequently, as shown in FIGS. 6 and 8, in the light emission period ET, the first and second switching transistors (the first and second switching transistors) are respectively driven by the scan pulse SP and the gate pulse GP of the gate-off voltage Voff. Tsw1 and Tsw2) are turned off, respectively. Accordingly, the driving transistor Tdr is turned on by the voltage Vdata-Vref stored in the capacitor Cst. Accordingly, the data current Ioled determined by the difference voltage Vdata-Vref between the display data voltage Vdata and the reference voltage Vref by the turned-on driving transistor Tdr is the organic light emitting diode By flowing through (OLED), the organic light emitting element (OLED) emits light in proportion to the flowing data current (Ioled). That is, in the light emission period ET, when the first and second switching transistors Tsw1 and Tsw2 are turned off, a current flows through the driving transistor Tdr, and the organic light-emitting device OLED is As light emission starts, the voltage of the second node n2 increases, and the voltage of the first node n1 increases by the voltage of the second node n2 by the capacitor Cst. The gate-source voltage Vgs of the driving transistor Tdr is continuously maintained by the voltage so that the organic light-emitting device OLED continues to emit light until the data addressing period DAT of the next frame. Here, the current Ioled flowing through the organic light emitting diode OLED is not affected by a change in the threshold voltage of the corresponding driving transistor Tdr by the display data voltage Vdata including the compensation voltage.

Meanwhile, according to the present invention, in the above-described data addressing period DAT, when the second switching transistor Tsw2 is turned off before the first switching transistor Tsw1 by a set time difference Δt, the driving transistor Tdr ) Can be compensated for changes in mobility characteristics. Specifically, when the second switching transistor Tsw2 is first turned off while the first switching transistor Tsw1 is turned on, the driving transistor Tdr moves according to the display data voltage Vdata. As a result, the source voltage of the driving transistor Tdr increases, and the gate-source voltage Vgs of the driving transistor Tdr decreases due to the increase of the source voltage, and the current flowing through the organic light emitting diode OLED. Is decreased, thereby compensating for a change in mobility characteristics of the driving transistor Tdr.

9 is a driving waveform diagram in a 3D display mode in the stereoscopic image display device according to the present invention.

A method of driving a stereoscopic image display device according to the present invention in a 3D display mode will be described with reference to FIGS. 1, 4, and 9 as follows.

In the 3D display mode, the display panel 100 drives each frame displaying the left-eye image LI or the right-eye image RI in the data addressing period DAT and the emission period ET. Here, the driving frequency of one frame may be 120 Hz, and the driving frequency of each of the data addressing period DAT and the light emission period ET may be 240 Hz.

First, in the data addressing section DAT of the first frame F1 for displaying the left eye image LI, the first to mth scan control lines SL1 to SLm are provided by the scan line driver 240. The first to mth scan pulses SP1 to SPm of the gate-on voltage Von shifted in units of one horizontal period are sequentially supplied. In addition, the data voltage Vdata of the left-eye image is supplied to each of the first to nth data lines DL1 to DLn every one horizontal period so as to be synchronized with each of the first to mth scan pulses SP1 to SPm. Simultaneously, the first to mth gate pulses GP1 of the gate-on voltage Von selected by the voltage selector 254 of the sensing line driver 250 are applied to the first to mth sensing control lines SSL1 to SSLm. To GPm) are supplied simultaneously. Accordingly, in the data addressing period DAT, the data voltage Vdata and the reference voltage Vref of the left eye image are supplied to each pixel P in units of horizontal lines from the first horizontal line to the m-th horizontal line. Accordingly, as shown in FIG. 7, the difference voltage Vdata-Vref between the data voltage Vdata of the left-eye image and the reference voltage Vref is stored in the capacitor Cst of each pixel P. At this time, since the reference voltage Vref is supplied to the second node n2 of all the pixels P, including the pixel P for which data addressing has already been completed, as well as the pixel P for which data addressing has not been performed. During the data addressing period DAT, current does not flow through the organic light emitting diodes OLEDs of all the pixels P due to the reference voltage Vref. As a result, in the data addressing period DAT, while data is sequentially addressed from the first horizontal line to the m-th horizontal line, the organic light emitting diodes OLED of all the pixels P are turned off.

In addition, during the data addressing period (DAT), the shutter driving signal generator 260 transmits an off-state (OFF) liquid crystal shutter driving signal (LSDS), whereby the left eye liquid crystal shutter and the right eye Each of the liquid crystal shutters is turned off, so the user perceives a black image.

First, in the light emission section ET of the first frame F1 for displaying the left eye image LI, the scan line driving T unit 240 is in the first to mth scan control lines SL1 to SLm. Accordingly, the first to m-th scan pulses SP1 to SPm of the gate-off voltage Voff are supplied. At the same time, the first to mth sensing control lines SSL1 to SSLm have first to mth gate pulses GP1 of the gate-off voltage Voff selected by the voltage selector 254 of the sensing line driver 250. To GPm) are supplied simultaneously. Accordingly, in the emission period ET, the second switching transistors Tsw2 of all the pixels P are simultaneously turned off, and thus, as shown in FIG. 8, the capacitor Cst of each pixel P ), the driving transistor Tdr is driven by the voltage stored in the driving transistor Tdr and current flows through the corresponding organic light emitting device OLED, so that the organic light emitting devices OLED of all the pixels P simultaneously emit light, and the organic light emitting device OLED ) Is maintained until the data addressing period of the next frame.

The shutter driving signal generator 260 transmits a liquid crystal shutter driving signal LSDS for turning on the left-eye liquid crystal shutter L_SG so as to be synchronized with the light emission period ET, and thereby, the left eye liquid crystal shutter of the 3D image glasses. Only (L_SG) is turned on, and as a result, the user perceives the left-eye image LI displayed on the display panel 100 through the left-eye liquid crystal shutter L_SG.

Next, in the data addressing period DAT of the second frame F2 for displaying the right eye image RI, the data voltage Vdata of the right eye image is applied to the first to nth data lines ( Except for supplying the data to each of the DL1 to DLn, the description thereof will be omitted since it is the same as the data addressing period DAT of the first frame F1.

Next, the light emission section ET of the second frame F2 for displaying the right eye image RI is a liquid crystal shutter driving signal for the shutter driving signal generator 260 to turn on the right eye liquid crystal shutter R_SG. Except for transmitting (LSDS), since it is the same as the light emission period ET of the first frame F1, a description thereof will be omitted. Accordingly, in the light emission section ET of the second frame F2, only the right eye liquid crystal shutter R_SG of the 3D image glasses is turned on, and thus the user displays the right eye liquid crystal shutter R_SG. The right eye image RI displayed on the panel 100 is recognized.

As described above, in the stereoscopic image display device according to the present invention, the organic light emitting device OLED of all the pixels P is turned off at the same time by simply switching the second switching transistor Tsw2 of all the pixels P. By simultaneously emitting light, a black image can be inserted between the left-eye image and the right-eye image to prevent interference between the left-eye image and right-eye image. Can be implemented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical matters of the present invention. It will be obvious to those who have the knowledge of. Therefore, the scope of the present invention is indicated by the claims to be described later, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

100: display panel 200: panel driver
210: timing control unit 220: voltage supply unit
230: column driver 232: data driver
234: switching unit 236: sensing unit
240: scan line driver 250: sensing line driver
252: gate pulse generator 254: voltage selector
260: shutter driving signal generation unit

Claims (11)

Including a plurality of data lines supplied with a data voltage, a plurality of scan control lines supplied with a scan pulse, a plurality of sensing control lines supplied with a gate pulse, a plurality of reference lines supplied with a reference voltage, and a plurality of pixels Display panel; And
When the driving mode of the display panel is set to a 3D display mode or a 2D display mode, the display panel is driven in a data addressing period and a light emitting period in the set 3D display mode or 2D display mode, and in the data addressing period of the 3D display mode And a panel driver configured to turn off all of the plurality of pixels and simultaneously emit light of the plurality of pixels in an emission period of the 3D display mode,
Each of the plurality of pixels,
Organic light emitting device;
A first switching transistor for supplying the data voltage to the first node by connecting a data line to a first node in response to the scan pulse;
A driving transistor that is driven according to a voltage difference between a data voltage supplied to the first node and a reference voltage supplied to a second node connected to the organic light emitting device to control a current flowing through the organic light emitting device;
A second switching transistor supplying the reference voltage to a second node; And
A capacitor connected between the first node and the second node,
A gate electrode of the driving transistor is connected to the first node, a source electrode of the driving transistor and an anode electrode of the organic light emitting device are connected to the second node,
In the data addressing period of the 3D display mode, the second switching transistor of each of the pixels is turned on to supply the reference voltage to the second node, and the second switching transistor of each of the pixels is turned on in the emission period of the 3D display mode. The 3D image display device, wherein the switching transistor is turned off to cut off the reference voltage supplied to the second node. The method of claim 1,
The 3D image display device, wherein the reference voltage is lower than a threshold voltage of the organic light emitting device. delete delete The method of claim 1,
Wherein the panel driver sequentially supplies scan pulses to the plurality of scan control lines in a data addressing period of the 3D display mode or the 2D display mode. The method according to any one of claims 1, 2 and 5,
The panel driver sets a driving mode of the display panel to a sensing mode,
In the sensing mode, a driving characteristic value of the driving transistor for each pixel is sensed through each of the plurality of reference lines to generate sensing data, and based on the sensing data in a data addressing period of the 3D display mode or the 2D display mode. A stereoscopic image display device, characterized in that the corrected data voltage for each pixel is supplied to the corresponding pixel. The method of claim 1,
The panel driving unit,
The driving mode of the display panel is set to the 3D display mode or the 2D display mode, and input data for each pixel are aligned to generate pixel data for each pixel, and a data control signal corresponding to the set driving mode, first and second A timing controller for generating a two row control signal, a liquid crystal shutter control signal, and a light emission control signal;
A scan line driver generating the scan pulse according to the first row control signal and supplying the scan pulse to a corresponding scan control line;
A sensing line driver generating the gate pulse according to the second row control signal, selecting one of the gate pulse, a gate-on voltage, and a gate-off voltage according to the emission control signal, and supplying the selected one to a corresponding sensing control line;
A column driver for converting the pixel data for each pixel into a data voltage according to the data control signal, supplying the data to a corresponding data line, and supplying the reference voltage to a corresponding reference line; And
In response to the liquid crystal shutter control signal, a shutter driving signal generator configured to transmit a shutter driving signal for alternately driving the left-eye liquid crystal shutter and the right-eye liquid crystal shutter of the 3D glasses according to the image displayed in the light emission section. 3D image display device, characterized in that. The method of claim 7,
The sensing line driver,
A gate pulse generator sequentially generating the gate pulses according to the second row control signal; And
A voltage selector having a plurality of selection circuits for selecting one of a gate-on voltage, a gate-off voltage, and a gate pulse supplied from the gate pulse generator according to the emission control signal and supplying it to a corresponding sensing control line. A stereoscopic image display device comprising: The method of claim 8,
Each of the plurality of selection circuits,
During the data addressing period of the 3D display mode, the gate-on voltage is selected and supplied to a corresponding sensing control line,
During the emission period of the 3D display mode, the gate-off voltage is selected and supplied to the sensing control line,
3D image display device, characterized in that the gate pulse is selected in the 2D display mode and supplied to a corresponding sensing control line. The method according to any one of claims 7 to 9,
The column driver,
A data driver converting the pixel data for each pixel into a data voltage and supplying the data to a corresponding data line;
A sensing unit generating sensing data by sensing a driving characteristic value of the driving transistor for each pixel through each of the plurality of reference lines; And
A switching unit for supplying the reference voltage to each of the plurality of reference lines or connecting the sensing unit to each of the plurality of reference lines,
The timing control unit generates the pixel data for each pixel by correcting the input data for each pixel based on the sensing data. A plurality of data lines each including a plurality of data lines supplied with a data voltage, a plurality of scan control lines supplied with a scan pulse, a plurality of sensing control lines supplied with a gate pulse, a plurality of reference lines supplied with a reference voltage, and a light emitting element A display panel on which pixels of are arranged; And
A panel driver configured to turn off all of the plurality of pixels in a data addressing period in which the data voltage is supplied to the data line, and simultaneously emit the plurality of pixels in a light emission period in which current flows through the light emitting device
Each of the plurality of pixels,
A first switching transistor for supplying the data voltage to the first node by connecting a data line to a first node in response to the scan pulse;
A driving transistor that is driven according to a voltage difference between a data voltage supplied to the first node and a reference voltage supplied to a second node connected to the light emitting device to control a current flowing through the light emitting device;
A second switching transistor supplying the reference voltage to a second node; And
A capacitor connected between the first node and the second node,
A gate electrode of the driving transistor is connected to the first node, a source electrode of the driving transistor and an anode electrode of the light emitting device are connected to the second node,
The second switching transistor of each of the pixels is turned on during the data addressing period to supply the reference voltage to the second node, and the second switching transistor of each of the pixels is turned off during the emission period 2. The stereoscopic image display device, wherein the reference voltage supplied to the two nodes is cut off.

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