KR102270602B1 - Display Device and Driving Method thereof - Google Patents

Abstract

The present invention provides a display device including a display panel, a data driver, and a bias circuit. The display panel displays an image. The data driver is located on one side of the display panel and supplies data signals through data lines of the display panel. The bias circuit unit is located on the other side of the display panel, predicts delay and loss of the data signal, and compensates the data line with a bias voltage corresponding to the amount.

Description

Display Device and Driving Method thereof

The present invention relates to a display device and a driving method thereof.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form, a driver for driving the display panel, and a timing controller for controlling the driver. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel and a data driver that supplies a data signal to the display panel.

Some of the above-described display devices, for example, a liquid crystal display device or an organic light emitting display device, are implemented as (ultra) large display devices. In the case of a (ultra) large display device, a delay and loss of a data signal is induced by an RC load of a data line when the display panel is driven. When the delay and loss of the data signal is caused, the data signal is not charged or the data signal is weakly charged in the sub-pixels of the display panel.

For this reason, in the related art, a double bank method has been proposed in which data drivers are installed on the upper and lower portions of the display panel in order to reduce the RC load by half, and the data signals are supplied from both sides.

However, in the conventionally proposed double bank method, since the data driver is further installed on the upper or lower portion of the display panel, the data driver as well as the source board (S-PCB), the connector (Connector), and the cable (FFC) There was a problem of causing an increase in the number of parts, such as, etc.

The present invention for solving the problems of the above-mentioned background art is to improve the display quality by preventing the delay and loss of the data signal by the RC load of the data line as well as the problem that the data signal is not charged or is weakly charged. will be. In addition, the present invention is to reduce the manufacturing cost when implementing a (ultra) large display device.

As a means of solving the above problems, the present invention provides a display device including a display panel, a data driver, and a bias circuit. The display panel displays an image. The data driver is located on one side of the display panel and supplies data signals through data lines of the display panel. The bias circuit unit is located on the other side of the display panel, predicts delay and loss of the data signal, and compensates the data line with a bias voltage corresponding to the amount.

After obtaining and sampling the data signal through the data lines, the bias circuit unit may generate a bias voltage corresponding to a compensation value of the data voltage based thereon.

By analyzing the slew rate of the data signal, the bias circuit unit predicts the maximum rate of change and the tendency to change of the data voltage formed by the data signal, and the slew rate at which the compensation value of the data voltage can be extracted. You can create data values.

The bias circuit unit is connected to the ends of the data lines located on the opposite side to the data driver and includes a sampling unit for sampling the data signal, and an AD converter for converting the analog sampling value transmitted from the sampling unit into a digital sampling value. And, based on the digital sampling value transmitted from the AD converter, the slew rate of the data signal is analyzed to predict the maximum rate of change and the tendency of the data voltage formed by the data signal, and based on this, the data voltage is compensated. It may include a slew rate analyzer that generates a slew rate data value from which a value can be extracted, and a DA converter that generates a bias voltage in response to the slew rate data value transmitted from the slew rate analyzer.

The DA converter may extract a bias data value corresponding to the slew rate data value from the lookup table and generate a bias voltage based on the extracted bias data value.

The bias circuit unit may be attached to the display panel in the form of chip-on-glass or chip-on-film.

In another aspect, the present invention provides a method of driving a display device. A method of driving a display device includes: sampling a data signal; analyzing a slew rate for the data signal; generating a bias voltage corresponding to the slew rate; and displaying an image based on the data signal and the bias voltage.

The present invention has the effect of improving display quality by preventing delay and loss of data signals due to RC load of data lines as well as problems of not charging or weakly charging data signals. In addition, the present invention has the effect of reducing the manufacturing cost by designing the data driver with a single bank structure capable of compensating (or halving) the RC load when implementing a (ultra) large display device.

1 is a block diagram schematically showing a display device;
FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1;
3 is an exemplary diagram of a module configuration of a display device according to the prior art;
4 is a diagram schematically illustrating a driving concept of a display device according to an embodiment of the present invention;
5 is a block diagram showing the configuration of the bias circuit shown in FIG.
6 is a waveform diagram for explaining a driving method of a bias circuit unit;
7 is a waveform diagram for explaining a method of driving a display device according to an embodiment of the present invention;
8 is a first exemplary diagram illustrating a configuration of a module of a display device based on an embodiment of the present invention;
9 is a second exemplary diagram illustrating a configuration of a module of a display device based on an embodiment of the present invention;

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

For the display device of the present invention described below, a display panel such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and a plasma display panel may be selected, but is not limited thereto. However, in the following description, a display device based on an organic light emitting display panel will be described as an example for convenience of explanation.

FIG. 1 is a block diagram schematically illustrating a display device, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel illustrated in FIG. 1 .

As shown in FIG. 1 , the display device includes an image supply unit 110 , a timing controller 120 , a gate driver 130 , a data driver 140 , and a display panel 150 .

The image supply unit 110 processes the data signal and outputs it together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The image supply unit 110 transmits a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and a data signal to the timing controller 120 through a low voltage differential signaling (LVDS) interface or a transition minimized differential signaling (TMDS) interface. ) is supplied to

The timing controller 120 receives the data signal DATA from the image supplier 110 , and a gate timing control signal GDC for controlling the operation timing of the gate driver 130 and the operation timing of the data driver 140 . and output a data timing control signal DDC for controlling the .

The timing controller 120 outputs the data signal DATA together with the gate timing control signal GDC and the data timing control signal DDC through a communication interface (eg, EPI), and the gate driver 130 and the data driver ( 140) to control the operation timing.

The gate driver 130 outputs a gate signal (or a scan signal) while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120 . The gate driver 130 includes a level shifter and a shift register.

The gate driver 130 supplies a gate signal to the sub-pixels SP included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 in the form of a gate in panel (Gate In Panel). A portion of the gate driver 130 formed in the gate-in-panel method is a shift register.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the digital signal into an analog signal in response to the gamma reference voltage and outputs it .

The data driver 140 supplies the data signal DATA to the sub-pixels SP included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 is formed in the form of an integrated circuit (IC).

The display panel 150 displays an image corresponding to the gate signal supplied from the gate driver 130 and the data signal DATA supplied from the data driver 140 . The display panel 150 includes sub-pixels SP that emit light by itself or control external light to display an image.

As shown in FIG. 2 , one sub-pixel is supplied through the switching thin film transistor SW and the switching thin film transistor SW connected to (or formed at the intersection of) the gate line GL1 and the data line DL1. A pixel circuit PC operating in response to the data signal DATA is included. The sub-pixels SP are composed of a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 150 is configured as a liquid crystal display panel, it is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB (Electrically Controlled Birefringence) mode. implemented in mode. When the display panel 150 is configured as an organic light emitting display panel, it is implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

On the other hand, a liquid crystal display device or an organic light emitting display device is implemented as a (ultra) large display device. In the case of a (ultra) large display device, a delay and loss of a data signal is induced by an RC load of a data line when the display panel is driven. When the delay and loss of the data signal is caused, the data signal is not charged or the data signal is weakly charged in the sub-pixels of the display panel.

3 is an exemplary diagram of a module configuration of a display device according to the related art.

As shown in FIG. 3 , in the related art, data drivers 140LU, 140RU, 140LL, and 140RL are installed on the upper and lower portions of the display panel 150 in order to halve the RC load, and data signals are supplied from both sides. A double bank (Bank 1, Bank 2; Double Bank) method has been proposed.

However, in the conventionally proposed double bank (Bank 1, Bank 2) method, since the data driver 140LU, 140RU or 140LL, 140RL is further installed on the upper or lower portion of the display panel 150 , the data driver as well as the source substrate (S-PCB), connectors (CNTU or CNTL), cables (CABU or CABL), etc., there is a problem that causes an increase in the number of parts, resulting in an increase in cost.

In FIG. 3 , 130L and 130R are left and right gate drivers, and 131L and 131R are left and right flexible substrates on which left and right gate drivers 130L and 130R are mounted, respectively. In addition, 141LU, 141RU, 141LL, and 141RL are upper left, upper right, lower left, and lower right flexible substrates on which data driving units 140LU, 140RU, 140LL, and 140RL are mounted, respectively. And the C-PCB is a control board on which the image supply unit 110 is mounted, and 145LU, 145RU, 145LL, and 145RL are upper left and upper right flexible substrates (141LU, 141RU), and lower left and lower right flexible substrates (141LL, 141RL). ) to electrically connect each of them.

As described above, the conventionally proposed double bank (Bank 1, Bank 2) method inevitably leads to an increase in cost, and research to improve it is required.

4 is a diagram schematically illustrating a driving concept of a display device according to an exemplary embodiment of the present invention, FIG. 5 is a block diagram illustrating the configuration of the bias circuit shown in FIG. 4, and FIG. 6 is the driving of the bias circuit. It is a waveform diagram for explaining a method, and FIG. 7 is a waveform diagram for explaining a method of driving a display device according to an embodiment of the present invention.

As shown in FIG. 4 , in the display device according to an embodiment of the present invention, the data driver 140 is installed on one side (eg, the upper part, but may be the lower part) of the display panel 150 , and the display panel A bias circuit unit 170 is installed on the other side of 150 (eg, a lower portion, but may be an upper portion).

The bias circuit unit 170 measures a slew rate with respect to the data signal DATA output from the data driver 140 installed on the display panel 150 and outputs a bias voltage BIAS based thereon. . The bias circuit unit 170 operates based on a voltage output from a power supply unit included in the display device, such as the data driver 140 .

In order to halve the RC load, the bias circuit unit 170 replaces the data driver 140 with a bias voltage (slew rate) based on a slew rate for the data signal DATA in the lower portion of the display panel 150 . BIAS) is printed. The bias voltage BIAS corresponds to a kind of compensation voltage of the data signal DATA.

The data driver 140 outputs the data signals DATA through input ends of the data lines DL1 to DLn, respectively. The bias circuit unit 170 serves to compensate the delay and loss of the data signal DATA supplied through the data lines DL1 to DLn by the RC load in a line-by-line manner. do. For this reason, the bias circuit unit 170 is respectively connected to distal ends of the data lines DL1 to DLn.

5 , the bias circuit unit 170 includes a sampling unit 172 (Sampling), an AD conversion unit ® ADC, a slew rate analysis unit 176 (Slew Rate), and a DA conversion unit 178 (DAC). and a lookup table 179 (LUT).

The sampling unit 172 (Sampling) is connected line by line to end portions of the data lines DL1 to DLn. The sampling unit 172 (Sampling) acquires the data signal DATA output through the data driving unit 140 for each line and then samples it.

The sampling unit 172 (Sampling) may use a sample & hold circuit, but is not limited thereto. The sampling unit 172 (Sampling) transfers sampling values for the data signals to the AD conversion unit 174 ADC.

The AD converter ® ADC is connected to the sampling unit 172 (Sampling). The AD conversion unit 174 ADC converts the analog sampling value transmitted from the sampling unit 172 Sampling into a digital form. The AD converter ® ADC transmits the digitally converted sampling value to the slew rate analyzer 176 (Slew Rate).

The slew rate analyzer 176 (Slew Rate) is connected to the AD converter ® ADC. The slew rate analyzer 176 (Slew Rate) is a slew rate for the data signal DATA output from the data driver 140 based on the digital sampling value transmitted from the AD converter 174 ADC. ) is analyzed.

The slew rate analyzer 176 analyzes the slew rate of the data signal DATA, and predicts the maximum rate of change and the tendency of the data voltage forming the data signal DATA.

The slew rate analyzer 176 predicts the maximum rate of change of the data voltage and the tendency of the change, and based on this, a compensation value ( It generates and outputs a slew rate data value from which a target voltage or compensation voltage can be extracted.

The DA converter 178 (DAC) is connected to the slew rate analyzer 176 (Slew Rate) and the lookup table 179 (LUT). The DA converter 178 (DAC) refers to the slew rate data value transmitted from the slew rate analyzer 176 and the lookup table 179 (LUT) to obtain a compensation value (target voltage or compensation voltage) of the data voltage. A corresponding bias voltage BIAS is generated and output.

The lookup table 179 (LUT) has bias data value(s) suitable for the slew rate of the display device through an engineering process. The bias data value(s) corresponds to a compensation value (a target voltage or a compensation voltage) of a data voltage that is delayed and lost by an RC load by the data line. The DA converter 178 (DAC) converts the bias data value(s) stored in the lookup table 179 (LUT) into a bias voltage BIAS and outputs it. The lookup table 179 (LUT) is composed of memory or registers.

On the other hand, the slew rate analyzer 176 (Slew Rate) is a data voltage that is delayed and lost by the RC load by the data line based on the trend data on the maximum change rate and change of the data voltage, unlike the method described above. It is possible to directly calculate the compensation value (target voltage or compensation voltage) of . In this case, the lookup table 179 (LUT) may be deleted, but a delay in generating and outputting the bias voltage BIAS may be caused due to a delay in the operation time depending on the performance of the device.

The waveform shown in FIG. 6 represents the result of obtaining the data signals DATA of various grayscales from the lower part of the display panel 150 . Referring to the characteristics of the data signal DATA based on the drawings, it can be seen that the slew rate of the data voltage varies according to the target voltage.

Referring to the characteristics of the data signal DATA based on the drawings, it can be seen that the target voltage (compensation voltage) can be predicted when the time axis called one horizontal period 1H is divided into predetermined intervals and sampling is performed during the predetermined interval. . The bias circuit unit 170 predicts the delay and loss of the data signal using these characteristics, and compensates the data signal by the amount of the bias voltage.

4 to 7 , the bias circuit unit 170 obtains and samples the data signal DATA from the lower portion of the display panel 150 , and then based on the obtained data signal DATA, a compensation value (target voltage or compensation voltage) of the data voltage. ) and generate and output a bias voltage BIAS corresponding to the .

The bias circuit unit 170 divides one horizontal period 1H into M-th (M is an integer greater than or equal to 2), and performs sampling and biasing operations during this period. For example, the bias circuit unit 170 divides one horizontal period (1H) into a sampling period (ST) for sampling, a biasing period (BT) for biasing, and a floating period (FT) in which its own channel is placed in a floating state. and perform a separate operation during this section.

The bias circuit unit 170 receives the data signal DATA using its own sampling unit 172 (Sampling), the AD conversion unit ® ADC, and the slew rate analysis unit 176 during the sampling period ST. This is the period to analyze the slew rate for During the sampling period ST, the data driver 140 outputs the data signal DATA through the data lines DL1 to DLn.

The sampling step (S110) and the step of analyzing the slew rate (S120) of the data signal include a sampling unit 172 (Sampling), an AD conversion unit 174 ADC, and a slew rate analysis unit 176 (Slew Rate). made by

The bias circuit unit 170 uses its DA converter 178 (DAC) and the lookup table 179 (LUT) to bias the data voltage compensation value (target voltage or compensation voltage) during the biasing period BT. Generates and outputs a voltage (BIAS). During the sampling period ST, the data driver 140 outputs the data signal DATA through the data lines DL1 to DLn.

The bias voltage generation step S130 corresponding to the slew rate is performed by the DA converter 178 (DAC) and the lookup table 179 (LUT).

The bias circuit unit 170 floats (disconnects) the data lines DL1 to DLn connected thereto during the floating period FT and stops (or stops) driving of its own circuits. During the sampling period ST, the data driver 140 may or may not output the data signal DATA through the data lines DL1 to DLn.

When the bias voltage BIAS is output from the bias circuit unit 170 , a data voltage is formed in the capacitors of each sub-pixel together with the data signal thereafter. Then, each sub-pixel is driven in response to the data voltage, and a specific image is displayed on the display panel.

Hereinafter, an example in which a module of a display device is configured based on an embodiment of the present invention will be described.

8 is a first exemplary diagram illustrating a configuration of a module of a display device based on an exemplary embodiment of the present invention, and FIG. 9 is a second exemplary diagram illustrating a configuration of a module of a display device based on an exemplary embodiment of the present invention.

[Example 1]

1, 4, and 8, according to the first exemplary embodiment of the present invention, data driving units 140LU, 140RU, 140LL, and 140RL are provided on the upper portion of the display panel 150 to reduce the RC load by half. is installed, and a bias circuit unit 170 is installed under the display panel 150 .

Like the data driver 140 , the bias circuit unit 170 may be formed in the form of one integrated circuit (IC), and may be formed in plurality according to the resolution (size) of the display panel.

According to the first exemplary embodiment of the present invention, the data driver 140 is implemented in a single bank (Bank 1) method formed only on the upper portion of the display panel 150 . Instead, a bias circuit unit 170 is provided under the display panel 150 to predict the delay and loss of the data signal and compensate for the delay and loss of the data signal by the amount corresponding to the bias voltage.

Unlike the data driver 140 , the bias circuit unit 170 is mounted on a lower bezel area of the display panel 150 . That is, the bias circuit unit 170 is attached to the substrate constituting the display panel 150 in the form of a chip on glass.

When the display device is implemented in this way, it is possible to prevent and solve the problem of cost increase due to the increase of parts such as the source board, connector, cable, etc. in order to further install the data driver in the lower part, thereby reducing the cost in manufacturing the display device. can be realized

In FIG. 8 , 130L and 130R are left and right gate drivers, and 131L and 131R are left and right flexible substrates on which left and right gate drivers 130L and 130R are mounted, respectively. And 141LU, 141RU, 141LL, and 141RL are upper left and upper right flexible substrates on which data drivers 140LU and 140RU are mounted, respectively. In addition, the C-PCB is a control board on which the image supply unit 110 is mounted, and 145LU and 145RU are connection units that electrically connect the upper left and upper right flexible substrates 141LU and 141RU, respectively.

[2nd example]

1, 4, and 9, according to the second exemplary embodiment of the present invention, data driving units 140LU, 140RU, 140LL, and 140RL are provided on the upper portion of the display panel 150 to halve the RC load. is installed, and a bias circuit unit 170 is installed under the display panel 150 .

Like the data driver 140 , the bias circuit unit 170 may be formed in the form of one integrated circuit (IC), and may be formed in plurality according to the resolution (size) of the display panel.

According to the second exemplary embodiment of the present invention, the data driver 140 is implemented in a single bank (Bank 1) method formed only on the upper portion of the display panel 150 . Instead, a bias circuit unit 170 is provided under the display panel 150 to predict the delay and loss of the data signal and compensate for the delay and loss of the data signal by the amount corresponding to the bias voltage.

Similar to the data driver 140 , the bias circuit unit 170 is mounted on the flexible substrates 171LL and 171RL attached to the lower portion of the display panel 150 . That is, the bias circuit unit 170 is attached to the substrate connected to the display panel 150 in the form of a chip on film.

When the display device is implemented in this way, it is possible to prevent and solve the problem of cost increase due to the increase of parts such as the source board, connector, cable, etc. in order to further install the data driver in the lower part, thereby reducing the cost in manufacturing the display device. can be realized

In FIG. 9 , 130L and 130R are left and right gate drivers, and 131L and 131R are left and right flexible substrates on which left and right gate drivers 130L and 130R are mounted, respectively. And 141LU, 141RU, 141LL, and 141RL are upper left and upper right flexible substrates on which data drivers 140LU and 140RU are mounted, respectively. In addition, the C-PCB is a control board on which the image supply unit 110 is mounted, and 145LU and 145RU are connection units that electrically connect the upper left and upper right flexible substrates 141LU and 141RU, respectively.

As described above, the present invention has the effect of improving the display quality by preventing the data signal from being charged or being weakly charged, as well as by preventing the delay and loss of the data signal due to the RC load of the data line. In addition, the present invention has the effect of reducing the manufacturing cost by designing the data driver with a single bank structure capable of compensating (or halving) the RC load when implementing a (ultra) large display device.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

110: image supply unit 120: timing control unit
130: gate driver 140: data driver
150: display panel 170: bias circuit unit
172: sampling unit 174: AD conversion unit
176: slew rate analysis unit 178: DA conversion unit
179: lookup table

Claims (7)

a display panel for displaying an image;
a data driver positioned at one side of the display panel and configured to supply a data signal through data lines of the display panel; and
and a bias circuit unit located on the other side of the display panel, predicting delay and loss of the data signal and compensating the data lines with a bias voltage by the amount;
the bias circuit
and generating the bias voltage corresponding to a compensation value of the data voltage based on the data signal obtained and sampling through the data lines. delete According to claim 1,
the bias circuit
By analyzing a slew rate for the data signal, a slew rate capable of predicting the maximum rate of change and a tendency to change of the data voltage formed by the data signal, and extracting a compensation value of the data voltage based thereon A display device for generating data values. According to claim 1,
the bias circuit
a sampling unit connected to ends of data lines positioned on a side opposite to the data driving unit and sampling the data signal;
an AD converter converting the analog sampling value transmitted from the sampling unit into a digital sampling value;
Based on the digital sampling value transmitted from the AD converter, the slew rate of the data signal is analyzed to predict the maximum rate of change and the tendency of the data voltage formed by the data signal, and based on this, the data voltage a slew rate analysis unit generating a slew rate data value capable of extracting a compensation value of
and a DA converter configured to generate the bias voltage in response to the slew rate data value transmitted from the slew rate analyzer. 5. The method of claim 4,
The DA conversion unit
and extracting a bias data value corresponding to the slew rate data value from a lookup table and generating the bias voltage based on the extracted bias data value. According to claim 1,
the bias circuit
A display device, characterized in that attached to the display panel in the form of a chip-on-glass or chip-on-film. obtaining and sampling a data signal through the data lines;
analyzing a slew rate of the data signal;
predicting the delay and loss of the data signal based on the slew rate and generating a bias voltage corresponding to a compensation value of the data voltage by the amount; and
and displaying an image based on the data signal and the bias voltage.

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