KR102283377B1 - Display device and gate driving circuit thereof - Google Patents

Abstract

The present invention relates to a display device and a gate driving circuit thereof. The gate driving circuit receives a gate start pulse and a gate shift clock and includes a shift register having flip-flops cascaded, buffers supplying an output signal of the flip-flop to gate lines, and responding to a first switch control signal a first switch for connecting adjacent gate lines, a second switch for connecting gate lines to the buffers in response to a second switch control signal, and an output of the gate start pulse, the gate shift clock, and the flip-flop; and a logic operation element for generating the first and second switch control signals using the gate output enable signal.

Description

DISPLAY DEVICE AND GATE DRIVING CIRCUIT THEREOF

The present invention relates to a display device and a gate driving circuit thereof.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (OLED Display), Plasma Display Panel (PDP), Electrophoretic Display Device (EPD) Various flat panel display devices are being developed. A liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. In an active matrix driving type liquid crystal display device, a thin film transistor (hereinafter, referred to as “TFT”) is formed for each pixel.

The liquid crystal display includes a display panel, a data driving circuit for supplying data signals to data lines of the display panel, and a gate driving circuit for supplying gate signals (or scan signals) to gate lines (or scan lines) of the display panel. circuit, and a control circuit for these driving circuits, a light source driving circuit for driving the light source of the backlight unit, and the like.

The gate driving circuit sequentially supplies a gate signal from a first gate line to a last gate line during one frame period to sequentially select lines of the pixel array. In general, a gate drive circuit includes a plurality of gate drive integrated circuits (ICs).

1 shows an example of a gate driving circuit. 2 shows a control signal and a gate signal for controlling the gate driving circuit.

1 and 2 , the gate driving circuit includes a shift register, a level shifter (LS), and the like.

The shift register shifts a gate start pulse (GSP) at each timing of a gate shift clock (GSC) using a plurality of cascadedly connected flip-flops (FF). The first flip-flop FF outputs the input, that is, the gate start pulse GSP, at the timing of the rising edge of the first clock of the gate shift clock GSC. The second flip-flop FF outputs the input, that is, the output of the first flip-flop FF, at the timing of the rising edge of the second clock of the gate shift clock GSC. Q1 is an output signal of the first flip-flop FF, and Q2 is an output signal of the second flip-flop FF. The output of the shift register is supplied to the level shifter LS through the AND gate AND.

Each of the AND gates 11 generates an output by logically multiplying the output signals Q1 and Q2 of the flip-flop Q and the inverted signal of the gate output enable signal (Gate Output Enable, GOE). The gate output enable signal GOE is inverted by the inverter NOT and supplied to the first input terminal of the AND gate AND. The AND gate AND supplies the outputs Q1 and Q2 of the flip-flop FF to the level shifter LS when the gate output enable signal GOE is a low logic voltage (L), When the gate output enable signal GOE is a high logic voltage (H), 0 (zero or low) is output.

The level shifter LS shifts the input voltage level to the operating voltage of the TFTs of the pixel array. The output signal of the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is a voltage higher than the threshold voltage of the TFT, and the gate low voltage VGL is a voltage higher than the threshold voltage of the TFT.

The output signal of the level shifter LS is supplied to the gate lines of the display panel through the buffer BUF. In FIG. 2 , OUT1 and OUT2 are gate signals output from the gate driving circuit through the buffer BUT. The TFT is turned on according to the gate signal from the gate line to supply the data signal from the data line to the pixel electrode.

The gate driving circuit increases the gate signal by charging the voltage of the gate line from VGL to VGH at the rising edge of the gate signal as shown in FIG. 3 . The gate driving circuit causes the gate signal to fall by discharging the voltage of the gate line from VGH to VGL at the falling edge of the gate signal as shown in FIG. 3 . Therefore, the gate driving circuit generates a voltage of the gate signal between VGH and VGL, and therefore power consumption is large. In FIG. 3 , “GIC output voltage” is the driving voltage of the gate drive IC and is the same as the driving voltage of the buffer BUF. The driving voltage of the buffer BUF is generated between VGL and VGH.

When the current consumption of VGH increases, the voltage of VHG may drop due to wiring resistance of the display panel. The voltage drop on VHG drops the amount of pixel charge on a particular line, resulting in line-shaped noise. The voltage drop of VGH mainly occurs between neighboring gay drive ICs, resulting in a horizontal block dim phenomenon.

One horizontal period is a period in which data is written in pixels of one line in the display panel. One horizontal period is inversely proportional to the number of lines of the display panel. The load on the gate line is proportional to the wiring resistance or parasitic capacitance of the gate line. 1 When the horizontal taim is shortened or the load of the gate line is increased, the slew rate of the gate signal is lowered. When the slew rate of the gate signal is lowered, the pixel fill rate is lowered, so the image quality is deteriorated. The slew rate is defined as the maximum rate of change of the output voltage. A low slew rate means that the output voltage does not reach the target voltage within the desired time.

As shown in FIG. 4 , when the resolution of the display device increases or the load on the gate line increases, the slew rate of the gate signal decreases. In FIG. 4 , reference numeral '11' denotes a gate signal having a high slew rate, and '12' denotes a gate signal having a low slew rate. When the slew rate of the gate signal is low, the gate signal does not reach the target voltage VGH within one horizontal period. Accordingly, when the slew rate of the gate signal is lowered, the gate voltage of the TFT is lowered, resulting in lowering of the charging amount of the pixel.

The present invention provides a display device capable of lowering power consumption of a gate driving circuit, increasing a slew rate, and reducing a voltage drop of a gate signal, and a gate driving circuit thereof.

A display device according to the present invention includes: a display panel including pixels arranged in a matrix form by an intersecting structure of data lines and gate lines; and a gate driver receiving a gate start pulse, a gate shift clock, and a gate output enable signal, generating a sequentially shifted gate signal, and supplying the gate signal to the gate lines.

The gate driver receives the gate start pulse and the gate shift clock and includes a shift register having flip-flops that are connected subordinately, buffers supplying an output signal of the flip-flop to gate lines, and a first switch control signal. A first switch for connecting neighboring gate lines in response, a second switch for connecting gate lines to the buffers in response to a second switch control signal, and outputs of the gate start pulse, the gate shift clock, and the flip-flop and a logic operation element for generating the first and second switch control signals using the gate output enable signal.

The present invention generates a switch control signal for controlling the charge share in the gate driving circuit and performs charge sharing at the rising edge and the falling edge of the gate signal using the switch control signal. As a result, according to the present invention, power consumption of the gate driving circuit can be lowered, the slew rate of the gate signal can be increased, and the voltage drop of the gate signal can be reduced.

1 is a circuit diagram showing a conventional gate driving circuit.
FIG. 2 is a waveform diagram showing a control signal and a gate signal of the gate driving circuit shown in FIG. 1 .
FIG. 3 is a waveform diagram showing a driving voltage of the gate driving circuit shown in FIG. 1 .
4 is a diagram illustrating a relationship between a slew rate of a gate signal and a resolution of a display device.
5 is a block diagram illustrating a display device according to an embodiment of the present invention.
6 is a diagram illustrating a charge share period of a gate signal and a driving period of the gate driver.
7 and 8 are diagrams illustrating an operating principle of a gate driver according to an embodiment of the present invention.
9 is a waveform diagram showing the operation of the gate driver according to the first embodiment of the present invention.
FIG. 10 is a circuit diagram illustrating a gate driver generating the same gate signal as in FIG. 9 .
11 is a waveform diagram showing the operation of the gate driver according to the second embodiment of the present invention.
12 is a circuit diagram illustrating a gate driver generating the same gate signal as in FIG. 11 .

The display device of the present invention may be implemented as a flat panel display device capable of realizing color, such as a liquid crystal display device (LCD), an organic light emitting diode display device (OLED Display), and a plasma display panel (PDP).

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 5 , the display device of the present invention includes a display panel 100 on which a pixel array is formed, and a display panel driving circuit for writing input image data to the display panel 100 . In FIG. 6 , a back light unit and a driving unit thereof are omitted.

The input image is displayed on the pixel array of the display panel 100 . The pixels of the pixel array are arranged in a matrix form defined by a cross structure of the data lines DL and the gate lines GL. Each of the pixels may include a pixel electrode 10 to which a data voltage is supplied, one or more TFTs operating as a switch element and/or a driving element, and one or more capacitors Cst. The pixels may be connected to a common electrode 2 . A common voltage Vcom is applied to the common electrode 2 to the pixels.

The display panel driving circuit includes a data driver 102 , a gate driver 103 , and a timing controller 101 .

The data driver 102 includes a plurality of source drive ICs. The source drive ICs convert the input image data received from the timing controller 101 into positive/negative gamma compensation voltages to output positive/negative data signals. The data signals output from the source drive ICs are supplied to the data lines S1 to Sm. Each of the source drive ICs inverts the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 101 and outputs the inverted polarity to the data lines S1 to Sm.

The gate driver 103 supplies a gate signal to the n (n is a positive integer) gate lines G1 to Gn under the control of the timing controller 101 . The gate driver may include a plurality of gate drive ICs. The IC in which the gate driver 103 is integrated may be bonded to the display panel 100 through a tape automated bonding (TAB) process and connected to the gate lines G1 to Gn. Also, the gate driver 103 may be directly formed on the surface of the substrate of the display panel 100 on which the pixel array is formed by using a gate in panel (GIP) process.

The gate driver 103 induces a charge share (CS) of the gate lines by connecting neighboring gate lines for a preset period t1 at each of the rising edge and the falling edge of the gate signal. The gate driver 103 supplies the gate signal to the gate line GL in a state in which the gate lines are separated from each other during the t2 period other than the t1 period. The gate driver 103 repeats this operation to generate a gate signal, and sequentially shifts the gate signal and supplies it to the gate lines GL.

A timing controller (TCON) 101 receives timing signals Vsync, Hsync, DE, and CLK synchronized with input image data from a host system (HOST) 104 . The timing controller 101 transmits the input image data received from the host system 110 to the data driver 102 . The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock CLK. The timing controller 101 includes a source timing control signal SDC and a gate timing control signal that control operation timings of the data driver 102 and the gate driver 103 based on the timing signals Vsync, Hsync, DE, and CLK. (GDC) occurs.

The source timing control signal (SDC) includes a source start pulse (Source Start Pulse, SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), and a source output enable signal (Source Output Enable, SOE) and the like. The source start pulse SSP controls the start timing of the shift register built in the data driver 102 . The source sampling clock SSC controls the sampling timing of data. The polarity control signal POL controls the polarity of the data signal output from the data driver 102 . The source output enable signal SOE controls output timing and charge sharing timing of the data signal.

The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP controls the start timing of the shift register. The gate shift clock GSC controls the shift timing of the shift register. The gate output enable signal GOE defines a charge share timing and a gate high voltage output timing in each of the gate signals.

The host system 104 may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

FIG. 6 is a diagram illustrating a charge share period t1 of a gate signal and a driving period t2 of the gate driver 103 .

The charge share period t1 is a period in which the gate lines GL are charged/discharged with an average voltage when no output is generated from the buffer BUF of the gate driver 103 and the gate lines GL are shorted to each other. am. The driving period t2 of the gate driver 103 is a period in which the gate lines GL are separated and the gate lines GL are charged/discharged with a voltage generated through the buffer BUF of the gate driver 103 . .

As shown in FIG. 6, the present invention precharges the voltage of the gate lines up to an intermediate potential between VGH and VGL, for example, (VGH-VGL)/2 by using the charge share (CS) during the period t1 from the rising edge of the gate signal. make it When the gate lines are connected to each other at the rising edge of the gate signal, the voltages of the gate lines are averaged by charge sharing (CS), and the voltage of the gate lines rapidly rises to approximately (VGH-VGL)/2. Subsequently, the present invention connects the gate line to the buffer BUF that outputs the VGH voltage for t2 at the rising edge of the gate signal to rapidly increase the voltage of the gate line GL from (VGH-VGL)/2 to VGH. In the present invention, since the gate driver 103 is driven only during the t2 period at the rising edge of the gate signal, power consumption of the gate driver 103 can be significantly reduced. During the t2 period, the gate signal has a swing width that is only 1/2 of that of the prior art, so that the slew rate is increased.

According to the present invention, as shown in FIG. 6 , the voltage of the gate lines is precharged up to a potential between VGH and VGL, for example, (VGH-VGL)/2 by using the charge share CS during t1 at the falling edge of the gate signal. When the gate lines are connected to each other at the falling edge of the gate signal, the voltage of the gate lines is averaged by charge sharing (CS), and the voltage of the gate line is rapidly lowered to approximately (VGH-VGL)/2. Connect the gate line to the buffer (BUF) that outputs VGL during t2 at the falling edge of the signal to quickly lower the voltage of the gate line (GL) from (VGH-VGL)/2 to VGL. In the present invention, since the gate driver 103 is driven only during the t2 period at the falling edge of the gate signal, power consumption of the gate driver 103 can be significantly reduced. During the t2 period, the gate signal has a swing width that is only 1/2 of that of the prior art, so that the slew rate is increased.

7 and 8 are diagrams illustrating an operation principle of a gate driver.

7 and 8 , the gate driver 103 sequentially shifts the gate signal using a shift register under the control of the timing controller 101 .

The gate driver 103 turns on the first switch S1 at the rising edge of the gate signal during the t1 period under the control of the timing controller 101 . At the rising edge of the gate signal, the gate lines GL are short-circuited to each other during the t1 period, so that the charge share CS rises to approximately (VGH-VGL)/2. At the rising edge of the gate signal, the voltage of the gate line rises through charge sharing without voltage supply from the gate driver 103 . The gate driver 103 turns on the second switch S2 for a period t2 under the control of the timing controller 101 to supply a voltage to the gate line GL through the second switch S2 to supply the voltage of the gate line. to VGH.

The gate driver 103 generates first and second switch control signals defining periods t1 and t2 using a logic operation element. The gate driver 103 turns on the first switch S1 at the falling edge of the gate signal during the period t1 under the control of the timing controller 101 . At the falling edge of the gate signal, the gate lines GL are short-circuited to each other during the t1 period and charge-share CS is lowered from VGH to approximately (VGH-VGL)/2. At the falling edge of the gate signal, the voltage of the gate line is lowered by charge sharing without voltage supply from the gate driver 103 . The gate driving unit 103 turns on the second switch S2 for a period t2 under the control of the timing controller 101 to discharge a voltage to the gate line GL through the second switch S2 to obtain the voltage of the gate line. lower to VGL.

The data driver 102 controls the switches S1 and S2 by generating the switch control signals C1 and C2 defining periods t1 and t2 as shown in FIGS. 9 to 12 .

9 is a waveform diagram showing the operation of the gate driver 103 according to the first embodiment of the present invention. FIG. 10 is a circuit diagram illustrating the gate driver 103 that generates the gate signal as shown in FIG. 9 .

9 and 10 , the gate driver 103 includes a shift register, a level shifter LS, a NOT gate, an AND gate, an AND gate, a NOR gate, and a buffer BUF. .

The gate driver 103 operates by receiving the GSP, GSC, and GOE from the timing controller 101 . The shift register includes a plurality of flip-flops FF that are cascadedly connected. GSP and GSC are input to the shift register. GSP is generated once during one frame period and is input to the first flip-flop (FF) of the shift register. The output signal of the previous flip-flop FF is input to the data input terminal of the other flip-flops FF. GSC is generated as many as the number of lines of the display panel. One period of GSC is one horizontal period. GSC is supplied to the clock terminals of all flip-flops and is also input to the NOT gate (NOT). GOE is input to the AND gate (AND).

The shift register shifts the GSP at each clock timing of the GSC using a plurality of cascadedly connected flip-flops. The first flip-flop FF outputs the input, ie, GSP, at the timing of the rising edge of the first clock of the GSC. The second flip-flop FF outputs the output of the first flip-flop FF at the timing of the rising edge of the second clock of the GSC. The third flip-flop FF outputs the output of the second flip-flop FF at the timing of the rising edge of the third clock of the GSC. Q1 is an output signal of the first flip-flop FF, and Q2 is an output signal of the second flip-flop FF. Q3 is an output signal of the third flip-flop FF. The outputs Q1, Q2, and Q3 of the shift register are input to the level shifter LS and also to the AND gate AND.

The NOT gate NOT inverts the gate shift clock GSC and supplies it to the AND gate AND.

The AND gate AND outputs a first switch control signal C1 defining t1 at which the charge share CS is performed. t1 is a period in which GOE = High AND GSC = Low AND (GSP or Q = high) as shown in FIG. 9 . Here, Hig is a high logic period and Low is a low logic period. AND is a logical product operation. GSP or Q = high means when the gate start pulse (GSP) or the output outputs (Q1, Q2, Q3) of the flip-flop (FF) are high logic. The first AND gate AND outputs the first switch control signal C1 by performing an OR operation on GOE, /GSC, and GSP. /GSC stands for inverted gate shift clock. The remaining AND gate AND outputs the first switch control signal C1 by performing an OR operation on GOE, /GSC, and Qn (n is a natural number). The output of the AND gate AND is input to the control terminal of the first switch S1 through the level shifter LS and is also input to the adjacent NOR gate NOR.

The NOR gate NOR generates a second switch control signal C2 defining a t2 period. The period t2 is the remaining period excluding the period t1. Accordingly, the NOR gate NOR receives the output of the adjacent AND gate AND performs an NOR operation to output the second switch control signal C2 . The output of the NOR gate NOR is input to the control terminal of the second switch S2 through the level shifter LS.

The level shifter LS shifts the input voltage level to the operating voltage of the TFTs of the pixel array. The output signal of the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is a voltage higher than the threshold voltage of the TFT, and the gate low voltage VGL is a voltage higher than the threshold voltage of the TFT.

On the other hand, the level shifter LS is connected to the input terminal of the shift register in the case of the GIP circuit. Accordingly, in the GIP circuit, the level shifter LS may be omitted on the substrate of the display panel.

The first switch S1 performs the charge share CS at each of the rising and falling edges of the gate signals OUT1 , OUT2 , and OUT3 in response to the first switch control signal C1 for a period t1 . VGH or the last output signal Carry of the front-stage gate drive IC is supplied to the first switch S1 connected to the first output terminal. The remaining first switches S1 connect adjacent output terminals. The first switches S1 are simultaneously turned on in response to the first switch control signal C1 to short-circuit all output terminals to perform a charge share CS. Since the output terminals of the gate driver 103 are connected to the gate lines GL, when the output terminals are short-circuited, the voltage of the gate lines GL increases or decreases to an intermediate potential between VGH and VGL by charge sharing. During the t1 period, the second switches S2 maintain an off state.

The second switch S2 responds to the second switch control signal C2 at each of the rising edges and the falling edges of the gate signals OUT1, OUT2, and OUT3. Supply VGH or VGL to the output terminals. The second switches S2 are sequentially turned on in synchronization with the sequentially generated outputs Q1, Q2, and Q3 of the shift register. Accordingly, the gate signal maintains the VGH potential according to the VGH input through the buffer BUF during the t2 period after the t1 period of the rising edge, and is input through the buffer BUF during the t2 period after the t1 period of the falling edge. Keep the VGL potential according to the VGL. During the t2 period, the first switches S1 maintain an off state.

11 is a waveform diagram showing the operation of the gate driver 103 according to the second embodiment of the present invention. 12 is a circuit diagram illustrating the gate driver 103 that generates the gate signal as shown in FIG. 11 .

11 and 12 , the gate driver 103 includes a shift register, a level shifter LS, a NOT gate NOT, a first AND gate AND1, a second AND gate AND2, and an OR gate OR ), a third AND gate NOR gate NOR, a buffer BUF, and the like.

The gate driver 103 operates by receiving the GSP, GSC, and GOE from the timing controller 101 . The shift register includes a plurality of flip-flops FF that are cascadedly connected. GSP and GSC are input to the shift register. GSP is generated once during one frame period and is input to the first flip-flop (FF) of the shift register. The output signal of the previous flip-flop FF is input to the data input terminal of the other flip-flops FF. GSC is generated as many as the number of lines of the display panel. One period of GSC is one horizontal period. GSC is supplied to the clock terminals of all flip-flops and is also input to the NOT gate (NOT). GOE is input to the AND gate (AND).

The shift register shifts the GSP at each clock timing of the GSC using a plurality of cascadedly connected flip-flops. The first flip-flop FF outputs the input, ie, GSP, at the timing of the rising edge of the first clock of the GSC. The second flip-flop FF outputs the output of the first flip-flop FF at the timing of the rising edge of the second clock of the GSC. The third flip-flop FF outputs the output of the second flip-flop FF at the timing of the rising edge of the third clock of the GSC. Q1 is an output signal of the first flip-flop FF, and Q2 is an output signal of the second flip-flop FF. Q3 is an output signal of the third flip-flop FF. The outputs Q1, Q2, and Q3 of the shift register are input to the level shifter LS and also input to the first and second AND gates AND1 and AND2.

The NOT gate NOT inverts the gate shift clock GSC and supplies it to the second AND gate AND2.

The first AND gate AND1 performs an AND operation on GSC and the output Qn of the n (n is a natural number)-th flip-flop FF to detect a section in which GSC = High AND Qn = High. The second AND gate AND2 performs an AND operation on the inverted GSC and the output Qn-1 of the n-1 th flip-flop FF to detect a section in which GSC = Low AND Qn-1 = High. Qn-1 is the output of the n-1 th flip-flop FF.

The OR gate OR outputs a result obtained by performing an OR operation on the output of the first AND gate AND1 and the output of the second AND gate AND2 .

The third AND gate AND3 outputs the first switch control signal C1 defining t1 at which the charge share CS is performed. The first third AND gate AND3 outputs a first switch control signal C1 by performing an AND operation on GOE and GSP. The remaining third AND gate AND outputs the first switch control signal C1 by performing an OR operation on the output of the GOE and the OR gate OR. The output of the third AND gate AND3 is input to the control terminal of the first switch S1 through the level shifter LS and is also input to the adjacent NOR gate NOR.

The NOR gate NOR generates a second switch control signal C2 defining a t2 period. The period t2 is the remaining period excluding the period t1. Accordingly, the NOR gate NOR receives the output of the adjacent third AND gate AND3 as an input and performs an NOR operation to output the second switch control signal C2 . The output of the NOR gate NOR is input to the control terminal of the second switch S2 through the level shifter LS.

The level shifter LS shifts the input voltage level to the operating voltage of the TFTs of the pixel array. The output signal of the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH is a voltage higher than the threshold voltage of the TFT, and the gate low voltage VGL is a voltage higher than the threshold voltage of the TFT.

On the other hand, the level shifter LS is connected to the input terminal of the shift register in the case of the GIP circuit. Accordingly, in the GIP circuit, the level shifter LS may be omitted on the substrate of the display panel.

The first switch S1 performs the charge share CS at each of the rising and falling edges of the gate signals OUT1 , OUT2 , and OUT3 in response to the first switch control signal C1 for a period t1 . VGH or the last output signal Carry of the front-stage gate drive IC is supplied to the first switch S1 connected to the first output terminal. The remaining first switches S1 connect adjacent output terminals. The first switches S1 are simultaneously turned on in response to the first switch control signal C1 to short-circuit all output terminals to perform a charge share CS. Since the output terminals of the gate driver 103 are connected to the gate lines GL, when the output terminals are short-circuited, the voltage of the gate lines GL increases or decreases to an intermediate potential between VGH and VGL by charge sharing. During the t1 period, the second switches S2 maintain an off state.

The second switch S2 responds to the second switch control signal C2 at each of the rising edges and the falling edges of the gate signals OUT1, OUT2, and OUT3. Supply VGH or VGL to the output terminals. The second switches S2 are sequentially turned on in synchronization with the sequentially generated outputs Q1, Q2, and Q3 of the shift register. Accordingly, the gate signal maintains the VGH potential according to the VGH input through the buffer BUF during the t2 period after the t1 period of the rising edge, and is input through the buffer BUF during the t2 period after the t1 period of the falling edge. Keep the VGL potential according to the VGL. During the t2 period, the first switches S1 maintain an off state.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 102: data driver
103: gate driver 101: timing controller
104: host system FF: flip-flop of shift register
LS: level shifter BUF: buffer
NOT : NOT gate AND : AND gate
OR: OR gate NOR: NOR gate
S1: first switch S2: second switch

Claims (8)

a display panel including pixels arranged in a matrix form by an intersecting structure of data lines and gate lines; and
a gate driver receiving a gate start pulse, a gate shift clock, and a gate output enable signal, generating a sequentially shifted gate signal, and supplying the gate signal to the gate lines;
The gate driver,
a shift register including flip-flops to which the gate start pulse and the gate shift clock are input and are connected to each other;
buffers supplying an output signal of the flip-flop to gate lines;
a first switch connecting adjacent gate lines in response to a first switch control signal;
a second switch coupling gate lines to the buffers in response to a second switch control signal; and
and a logic operation element configured to generate the first and second switch control signals using the gate start pulse, the gate shift clock, an output of the flip-flop, and the gate output enable signal. The method of claim 1,
the first switch control signal defines a first period within a period of a rising edge and a falling edge of the gate signal;
The second switch control signal defines a second period excluding the first period,
the first switch is turned on for a first period,
The second switch is turned on for a second period. 3. The method of claim 2,
The logic operation element is
a NOT gate for inverting the gate shift clock;
an AND gate generating the first switch control signal by performing an OR operation on an output of the NOT gate, an output of the gate start pulse or the flip-flop, and the gate output enable signal; and
A display device comprising: a NOR gate that receives outputs of adjacent AND gates and performs an NOR operation to generate the second switch control signal. 3. The method of claim 2,
The logic operation element is
a NOT gate for inverting the gate shift clock;
a first AND gate for performing an OR operation on the gate shift clock and an output of an n (n is a natural number)-th flip-flop;
a second AND gate for performing an OR operation on the output of the NOT gate and the output of the n-1 th flip-flop;
an OR gate configured to perform an OR operation on outputs of the first AND gate and the second AND gate;
a third AND gate for generating the first switch control signal by logically multiplying the gate output enable signal and the gate start pulse or by logically multiplying the gate output enable signal and the OR gate output; and
A display device comprising: a NOR gate that receives outputs of adjacent AND gates and performs an NOR operation to generate the second switch control signal. a shift register to which a gate start pulse and a gate shift clock are input and having flip-flops cascaded;
buffers supplying an output signal of the flip-flop to gate lines;
a first switch connecting adjacent gate lines in response to a first switch control signal;
a second switch coupling gate lines to the buffers in response to a second switch control signal; and
and a logic operation element for generating the first and second switch control signals using the gate start pulse, the gate shift clock, an output of the flip-flop, and a gate output enable signal. 6. The method of claim 5,
the first switch control signal defines a first period within a rising edge and a falling edge period of the gate signal output from the gate driving circuit;
The second switch control signal defines a second period excluding the first period,
the first switch is turned on for a first period,
and the second switch is turned on for a second period. 7. The method of claim 6,
The logic operation element is
a NOT gate for inverting the gate shift clock;
an AND gate generating the first switch control signal by performing an OR operation on an output of the NOT gate, an output of the gate start pulse or the flip-flop, and the gate output enable signal; and
A gate driving circuit for a display device, comprising: a NOR gate that receives outputs of adjacent AND gates and performs an NOR operation to generate the second switch control signal. 7. The method of claim 6,
The logic operation element is
a NOT gate for inverting the gate shift clock;
a first AND gate for performing an OR operation on the gate shift clock and an output of an n (n is a natural number)-th flip-flop;
a second AND gate for performing an OR operation on the output of the NOT gate and the output of the n-1 th flip-flop;
an OR gate configured to perform an OR operation on outputs of the first AND gate and the second AND gate;
a third AND gate for generating the first switch control signal by logically multiplying the gate output enable signal and the gate start pulse or by logically multiplying the gate output enable signal and the OR gate output; and
A gate driving circuit for a display device, comprising: a NOR gate that receives outputs of adjacent AND gates and performs an NOR operation to generate the second switch control signal.

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